1 //===- SystemZInstrInfo.td - SystemZ Instruction defs ---------*- tblgen-*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the SystemZ instructions in TableGen format.
12 //===----------------------------------------------------------------------===//
14 //===----------------------------------------------------------------------===//
15 // SystemZ Instruction Predicate Definitions.
16 def IsZ10 : Predicate<"Subtarget.isZ10()">;
18 include "SystemZInstrFormats.td"
20 //===----------------------------------------------------------------------===//
22 //===----------------------------------------------------------------------===//
23 class SDTCisI8<int OpNum> : SDTCisVT<OpNum, i8>;
24 class SDTCisI16<int OpNum> : SDTCisVT<OpNum, i16>;
25 class SDTCisI32<int OpNum> : SDTCisVT<OpNum, i32>;
26 class SDTCisI64<int OpNum> : SDTCisVT<OpNum, i64>;
28 //===----------------------------------------------------------------------===//
30 //===----------------------------------------------------------------------===//
31 def SDT_SystemZCall : SDTypeProfile<0, -1, [SDTCisPtrTy<0>]>;
32 def SDT_SystemZCallSeqStart : SDCallSeqStart<[SDTCisI64<0>]>;
33 def SDT_SystemZCallSeqEnd : SDCallSeqEnd<[SDTCisI64<0>, SDTCisI64<1>]>;
34 def SDT_CmpTest : SDTypeProfile<0, 2, [SDTCisSameAs<0, 1>]>;
35 def SDT_BrCond : SDTypeProfile<0, 2,
36 [SDTCisVT<0, OtherVT>,
38 def SDT_SelectCC : SDTypeProfile<1, 3,
39 [SDTCisSameAs<0, 1>, SDTCisSameAs<1, 2>,
41 def SDT_Address : SDTypeProfile<1, 1,
42 [SDTCisSameAs<0, 1>, SDTCisPtrTy<0>]>;
44 //===----------------------------------------------------------------------===//
45 // SystemZ Specific Node Definitions.
46 //===----------------------------------------------------------------------===//
47 def SystemZretflag : SDNode<"SystemZISD::RET_FLAG", SDTNone,
48 [SDNPHasChain, SDNPOptInFlag]>;
49 def SystemZcall : SDNode<"SystemZISD::CALL", SDT_SystemZCall,
50 [SDNPHasChain, SDNPOutFlag, SDNPOptInFlag]>;
51 def SystemZcallseq_start :
52 SDNode<"ISD::CALLSEQ_START", SDT_SystemZCallSeqStart,
53 [SDNPHasChain, SDNPOutFlag]>;
54 def SystemZcallseq_end :
55 SDNode<"ISD::CALLSEQ_END", SDT_SystemZCallSeqEnd,
56 [SDNPHasChain, SDNPOptInFlag, SDNPOutFlag]>;
57 def SystemZcmp : SDNode<"SystemZISD::CMP", SDT_CmpTest, [SDNPOutFlag]>;
58 def SystemZucmp : SDNode<"SystemZISD::UCMP", SDT_CmpTest, [SDNPOutFlag]>;
59 def SystemZbrcond : SDNode<"SystemZISD::BRCOND", SDT_BrCond,
60 [SDNPHasChain, SDNPInFlag]>;
61 def SystemZselect : SDNode<"SystemZISD::SELECT", SDT_SelectCC, [SDNPInFlag]>;
62 def SystemZpcrelwrapper : SDNode<"SystemZISD::PCRelativeWrapper", SDT_Address, []>;
65 include "SystemZOperands.td"
67 //===----------------------------------------------------------------------===//
70 def ADJCALLSTACKDOWN : Pseudo<(outs), (ins i64imm:$amt),
72 [(SystemZcallseq_start timm:$amt)]>;
73 def ADJCALLSTACKUP : Pseudo<(outs), (ins i64imm:$amt1, i64imm:$amt2),
75 [(SystemZcallseq_end timm:$amt1, timm:$amt2)]>;
77 let usesCustomDAGSchedInserter = 1 in {
78 def Select32 : Pseudo<(outs GR32:$dst), (ins GR32:$src1, GR32:$src2, i8imm:$cc),
81 (SystemZselect GR32:$src1, GR32:$src2, imm:$cc))]>;
82 def Select64 : Pseudo<(outs GR64:$dst), (ins GR64:$src1, GR64:$src2, i8imm:$cc),
85 (SystemZselect GR64:$src1, GR64:$src2, imm:$cc))]>;
89 //===----------------------------------------------------------------------===//
90 // Control Flow Instructions...
93 // FIXME: Provide proper encoding!
94 let isReturn = 1, isTerminator = 1, isBarrier = 1, hasCtrlDep = 1 in {
95 def RET : Pseudo<(outs), (ins), "br\t%r14", [(SystemZretflag)]>;
98 let isBranch = 1, isTerminator = 1 in {
99 let isBarrier = 1 in {
100 def JMP : Pseudo<(outs), (ins brtarget:$dst), "j\t{$dst}", [(br bb:$dst)]>;
102 let isIndirectBranch = 1 in
103 def JMPr : Pseudo<(outs), (ins GR64:$dst), "br\t{$dst}", [(brind GR64:$dst)]>;
106 let Uses = [PSW] in {
107 def JE : Pseudo<(outs), (ins brtarget:$dst),
109 [(SystemZbrcond bb:$dst, SYSTEMZ_COND_E)]>;
110 def JNE : Pseudo<(outs), (ins brtarget:$dst),
112 [(SystemZbrcond bb:$dst, SYSTEMZ_COND_NE)]>;
113 def JH : Pseudo<(outs), (ins brtarget:$dst),
115 [(SystemZbrcond bb:$dst, SYSTEMZ_COND_H)]>;
116 def JL : Pseudo<(outs), (ins brtarget:$dst),
118 [(SystemZbrcond bb:$dst, SYSTEMZ_COND_L)]>;
119 def JHE : Pseudo<(outs), (ins brtarget:$dst),
121 [(SystemZbrcond bb:$dst, SYSTEMZ_COND_HE)]>;
122 def JLE : Pseudo<(outs), (ins brtarget:$dst),
124 [(SystemZbrcond bb:$dst, SYSTEMZ_COND_LE)]>;
129 //===----------------------------------------------------------------------===//
130 // Call Instructions...
134 // All calls clobber the non-callee saved registers. Uses for argument
135 // registers are added manually.
136 let Defs = [R0D, R1D, R2D, R3D, R4D, R5D, R14D] in {
137 def CALLi : Pseudo<(outs), (ins i64imm:$dst, variable_ops),
138 "brasl\t%r14, $dst", [(SystemZcall imm:$dst)]>;
139 def CALLr : Pseudo<(outs), (ins ADDR64:$dst, variable_ops),
140 "basr\t%r14, $dst", [(SystemZcall ADDR64:$dst)]>;
143 //===----------------------------------------------------------------------===//
144 // Miscellaneous Instructions.
147 let isReMaterializable = 1 in
148 // FIXME: Provide imm12 variant
149 // FIXME: Address should be halfword aligned...
150 def LA64r : Pseudo<(outs GR64:$dst), (ins laaddr:$src),
152 [(set GR64:$dst, laaddr:$src)]>;
153 def LA64rm : Pseudo<(outs GR64:$dst), (ins i64imm:$src),
154 "larl\t{$dst, $src}",
156 (SystemZpcrelwrapper tglobaladdr:$src))]>;
158 let neverHasSideEffects = 1 in
159 def NOP : Pseudo<(outs), (ins), "# no-op", []>;
161 //===----------------------------------------------------------------------===//
164 // FIXME: Provide proper encoding!
165 let neverHasSideEffects = 1 in {
166 def MOV32rr : Pseudo<(outs GR32:$dst), (ins GR32:$src),
169 def MOV64rr : Pseudo<(outs GR64:$dst), (ins GR64:$src),
172 def MOV128rr : Pseudo<(outs GR128:$dst), (ins GR128:$src),
174 "\tlgr\t${dst:subreg_odd}, ${src:subreg_odd}\n"
175 "\tlgr\t${dst:subreg_even}, ${src:subreg_even}",
177 def MOV64rrP : Pseudo<(outs GR64P:$dst), (ins GR64P:$src),
179 "\tlr\t${dst:subreg_odd}, ${src:subreg_odd}\n"
180 "\tlr\t${dst:subreg_even}, ${src:subreg_even}",
184 def MOVSX64rr32 : Pseudo<(outs GR64:$dst), (ins GR32:$src),
185 "lgfr\t{$dst, $src}",
186 [(set GR64:$dst, (sext GR32:$src))]>;
187 def MOVZX64rr32 : Pseudo<(outs GR64:$dst), (ins GR32:$src),
188 "llgfr\t{$dst, $src}",
189 [(set GR64:$dst, (zext GR32:$src))]>;
191 // FIXME: Provide proper encoding!
192 let isReMaterializable = 1, isAsCheapAsAMove = 1 in {
193 def MOV32ri16 : Pseudo<(outs GR32:$dst), (ins s16imm:$src),
195 [(set GR32:$dst, immSExt16:$src)]>;
196 def MOV64ri16 : Pseudo<(outs GR64:$dst), (ins s16imm64:$src),
197 "lghi\t{$dst, $src}",
198 [(set GR64:$dst, immSExt16:$src)]>;
200 def MOV64rill16 : Pseudo<(outs GR64:$dst), (ins i64imm:$src),
201 "llill\t{$dst, $src}",
202 [(set GR64:$dst, i64ll16:$src)]>;
203 def MOV64rilh16 : Pseudo<(outs GR64:$dst), (ins i64imm:$src),
204 "llilh\t{$dst, $src}",
205 [(set GR64:$dst, i64lh16:$src)]>;
206 def MOV64rihl16 : Pseudo<(outs GR64:$dst), (ins i64imm:$src),
207 "llihl\t{$dst, $src}",
208 [(set GR64:$dst, i64hl16:$src)]>;
209 def MOV64rihh16 : Pseudo<(outs GR64:$dst), (ins i64imm:$src),
210 "llihh\t{$dst, $src}",
211 [(set GR64:$dst, i64hh16:$src)]>;
213 def MOV64ri32 : Pseudo<(outs GR64:$dst), (ins s32imm64:$src),
214 "lgfi\t{$dst, $src}",
215 [(set GR64:$dst, immSExt32:$src)]>;
216 def MOV64rilo32 : Pseudo<(outs GR64:$dst), (ins i64imm:$src),
217 "llilf\t{$dst, $src}",
218 [(set GR64:$dst, i64lo32:$src)]>;
219 def MOV64rihi32 : Pseudo<(outs GR64:$dst), (ins i64imm:$src),
220 "llihf\t{$dst, $src}",
221 [(set GR64:$dst, i64hi32:$src)]>;
224 let canFoldAsLoad = 1, isReMaterializable = 1, mayHaveSideEffects = 1 in {
225 def MOV32rm : Pseudo<(outs GR32:$dst), (ins rriaddr12:$src),
227 [(set GR32:$dst, (load rriaddr12:$src))]>;
228 def MOV32rmy : Pseudo<(outs GR32:$dst), (ins rriaddr:$src),
230 [(set GR32:$dst, (load rriaddr:$src))]>;
231 def MOV64rm : Pseudo<(outs GR64:$dst), (ins rriaddr:$src),
233 [(set GR64:$dst, (load rriaddr:$src))]>;
237 def MOV32mr : Pseudo<(outs), (ins rriaddr12:$dst, GR32:$src),
239 [(store GR32:$src, rriaddr12:$dst)]>;
240 def MOV32mry : Pseudo<(outs), (ins rriaddr:$dst, GR32:$src),
242 [(store GR32:$src, rriaddr:$dst)]>;
243 def MOV64mr : Pseudo<(outs), (ins rriaddr:$dst, GR64:$src),
245 [(store GR64:$src, rriaddr:$dst)]>;
247 def MOV8mi : Pseudo<(outs), (ins riaddr12:$dst, i32i8imm:$src),
249 [(truncstorei8 (i32 i32immSExt8:$src), riaddr12:$dst)]>;
250 def MOV8miy : Pseudo<(outs), (ins riaddr:$dst, i32i8imm:$src),
251 "mviy\t{$dst, $src}",
252 [(truncstorei8 (i32 i32immSExt8:$src), riaddr:$dst)]>;
254 def MOV16mi : Pseudo<(outs), (ins riaddr12:$dst, s16imm:$src),
255 "mvhhi\t{$dst, $src}",
256 [(truncstorei16 (i32 i32immSExt16:$src), riaddr12:$dst)]>,
258 def MOV32mi16 : Pseudo<(outs), (ins riaddr12:$dst, s32imm:$src),
259 "mvhi\t{$dst, $src}",
260 [(store (i32 immSExt16:$src), riaddr12:$dst)]>,
262 def MOV64mi16 : Pseudo<(outs), (ins riaddr12:$dst, s32imm64:$src),
263 "mvghi\t{$dst, $src}",
264 [(store (i64 immSExt16:$src), riaddr12:$dst)]>,
268 def MOVSX32rr8 : Pseudo<(outs GR32:$dst), (ins GR32:$src),
270 [(set GR32:$dst, (sext_inreg GR32:$src, i8))]>;
271 def MOVSX64rr8 : Pseudo<(outs GR64:$dst), (ins GR64:$src),
272 "lgbr\t{$dst, $src}",
273 [(set GR64:$dst, (sext_inreg GR64:$src, i8))]>;
274 def MOVSX32rr16 : Pseudo<(outs GR32:$dst), (ins GR32:$src),
276 [(set GR32:$dst, (sext_inreg GR32:$src, i16))]>;
277 def MOVSX64rr16 : Pseudo<(outs GR64:$dst), (ins GR64:$src),
278 "lghr\t{$dst, $src}",
279 [(set GR64:$dst, (sext_inreg GR64:$src, i16))]>;
282 def MOVSX32rm8 : Pseudo<(outs GR32:$dst), (ins rriaddr:$src),
284 [(set GR32:$dst, (sextloadi32i8 rriaddr:$src))]>;
285 def MOVSX32rm16 : Pseudo<(outs GR32:$dst), (ins rriaddr12:$src),
287 [(set GR32:$dst, (sextloadi32i16 rriaddr12:$src))]>;
288 def MOVSX32rm16y : Pseudo<(outs GR32:$dst), (ins rriaddr:$src),
290 [(set GR32:$dst, (sextloadi32i16 rriaddr:$src))]>;
291 def MOVSX64rm8 : Pseudo<(outs GR64:$dst), (ins rriaddr:$src),
293 [(set GR64:$dst, (sextloadi64i8 rriaddr:$src))]>;
294 def MOVSX64rm16 : Pseudo<(outs GR64:$dst), (ins rriaddr:$src),
296 [(set GR64:$dst, (sextloadi64i16 rriaddr:$src))]>;
297 def MOVSX64rm32 : Pseudo<(outs GR64:$dst), (ins rriaddr:$src),
299 [(set GR64:$dst, (sextloadi64i32 rriaddr:$src))]>;
301 def MOVZX32rm8 : Pseudo<(outs GR32:$dst), (ins rriaddr:$src),
303 [(set GR32:$dst, (zextloadi32i8 rriaddr:$src))]>;
304 def MOVZX32rm16 : Pseudo<(outs GR32:$dst), (ins rriaddr:$src),
306 [(set GR32:$dst, (zextloadi32i16 rriaddr:$src))]>;
307 def MOVZX64rm8 : Pseudo<(outs GR64:$dst), (ins rriaddr:$src),
308 "llgc\t{$dst, $src}",
309 [(set GR64:$dst, (zextloadi64i8 rriaddr:$src))]>;
310 def MOVZX64rm16 : Pseudo<(outs GR64:$dst), (ins rriaddr:$src),
311 "llgh\t{$dst, $src}",
312 [(set GR64:$dst, (zextloadi64i16 rriaddr:$src))]>;
313 def MOVZX64rm32 : Pseudo<(outs GR64:$dst), (ins rriaddr:$src),
314 "llgf\t{$dst, $src}",
315 [(set GR64:$dst, (zextloadi64i32 rriaddr:$src))]>;
318 def MOV32m8r : Pseudo<(outs), (ins rriaddr12:$dst, GR32:$src),
320 [(truncstorei8 GR32:$src, rriaddr12:$dst)]>;
322 def MOV32m8ry : Pseudo<(outs), (ins rriaddr:$dst, GR32:$src),
323 "stcy\t{$src, $dst}",
324 [(truncstorei8 GR32:$src, rriaddr:$dst)]>;
326 def MOV32m16r : Pseudo<(outs), (ins rriaddr12:$dst, GR32:$src),
328 [(truncstorei16 GR32:$src, rriaddr12:$dst)]>;
330 def MOV32m16ry : Pseudo<(outs), (ins rriaddr:$dst, GR32:$src),
331 "sthy\t{$src, $dst}",
332 [(truncstorei16 GR32:$src, rriaddr:$dst)]>;
334 def MOV64m8r : Pseudo<(outs), (ins rriaddr12:$dst, GR64:$src),
336 [(truncstorei8 GR64:$src, rriaddr12:$dst)]>;
338 def MOV64m8ry : Pseudo<(outs), (ins rriaddr:$dst, GR64:$src),
339 "stcy\t{$src, $dst}",
340 [(truncstorei8 GR64:$src, rriaddr:$dst)]>;
342 def MOV64m16r : Pseudo<(outs), (ins rriaddr12:$dst, GR64:$src),
344 [(truncstorei16 GR64:$src, rriaddr12:$dst)]>;
346 def MOV64m16ry : Pseudo<(outs), (ins rriaddr:$dst, GR64:$src),
347 "sthy\t{$src, $dst}",
348 [(truncstorei16 GR64:$src, rriaddr:$dst)]>;
350 def MOV64m32r : Pseudo<(outs), (ins rriaddr12:$dst, GR64:$src),
352 [(truncstorei32 GR64:$src, rriaddr12:$dst)]>;
354 def MOV64m32ry : Pseudo<(outs), (ins rriaddr:$dst, GR64:$src),
356 [(truncstorei32 GR64:$src, rriaddr:$dst)]>;
358 // multiple regs moves
359 // FIXME: should we use multiple arg nodes?
360 def MOV32mrm : Pseudo<(outs), (ins riaddr:$dst, GR32:$from, GR32:$to),
361 "stmy\t{$from, $to, $dst}",
363 def MOV64mrm : Pseudo<(outs), (ins riaddr:$dst, GR64:$from, GR64:$to),
364 "stmg\t{$from, $to, $dst}",
366 def MOV32rmm : Pseudo<(outs GR32:$from, GR32:$to), (ins riaddr:$dst),
367 "lmy\t{$from, $to, $dst}",
369 def MOV64rmm : Pseudo<(outs GR64:$from, GR64:$to), (ins riaddr:$dst),
370 "lmg\t{$from, $to, $dst}",
374 //===----------------------------------------------------------------------===//
375 // Arithmetic Instructions
377 let Defs = [PSW] in {
378 def NEG32rr : Pseudo<(outs GR32:$dst), (ins GR32:$src),
380 [(set GR32:$dst, (ineg GR32:$src)),
382 def NEG64rr : Pseudo<(outs GR64:$dst), (ins GR64:$src),
383 "lcgr\t{$dst, $src}",
384 [(set GR64:$dst, (ineg GR64:$src)),
386 def NEG64rr32 : Pseudo<(outs GR64:$dst), (ins GR32:$src),
387 "lcgfr\t{$dst, $src}",
388 [(set GR64:$dst, (ineg (sext GR32:$src))),
392 let isTwoAddress = 1 in {
394 let Defs = [PSW] in {
396 let isCommutable = 1 in { // X = ADD Y, Z == X = ADD Z, Y
397 // FIXME: Provide proper encoding!
398 def ADD32rr : Pseudo<(outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
400 [(set GR32:$dst, (add GR32:$src1, GR32:$src2)),
402 def ADD64rr : Pseudo<(outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
403 "agr\t{$dst, $src2}",
404 [(set GR64:$dst, (add GR64:$src1, GR64:$src2)),
408 // FIXME: Provide proper encoding!
409 def ADD32ri16 : Pseudo<(outs GR32:$dst), (ins GR32:$src1, s16imm:$src2),
410 "ahi\t{$dst, $src2}",
411 [(set GR32:$dst, (add GR32:$src1, immSExt16:$src2)),
413 def ADD32ri : Pseudo<(outs GR32:$dst), (ins GR32:$src1, s32imm:$src2),
414 "afi\t{$dst, $src2}",
415 [(set GR32:$dst, (add GR32:$src1, imm:$src2)),
417 def ADD64ri16 : Pseudo<(outs GR64:$dst), (ins GR64:$src1, s16imm64:$src2),
418 "aghi\t{$dst, $src2}",
419 [(set GR64:$dst, (add GR64:$src1, immSExt16:$src2)),
421 def ADD64ri32 : Pseudo<(outs GR64:$dst), (ins GR64:$src1, s32imm64:$src2),
422 "agfi\t{$dst, $src2}",
423 [(set GR64:$dst, (add GR64:$src1, immSExt32:$src2)),
426 let isCommutable = 1 in { // X = AND Y, Z == X = AND Z, Y
427 // FIXME: Provide proper encoding!
428 def AND32rr : Pseudo<(outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
430 [(set GR32:$dst, (and GR32:$src1, GR32:$src2))]>;
431 def AND64rr : Pseudo<(outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
432 "ngr\t{$dst, $src2}",
433 [(set GR64:$dst, (and GR64:$src1, GR64:$src2))]>;
436 // FIXME: Provide proper encoding!
437 // FIXME: Compute masked bits properly!
438 def AND32rill16 : Pseudo<(outs GR32:$dst), (ins GR32:$src1, i32imm:$src2),
439 "nill\t{$dst, $src2}",
440 [(set GR32:$dst, (and GR32:$src1, i32ll16c:$src2))]>;
441 def AND64rill16 : Pseudo<(outs GR64:$dst), (ins GR64:$src1, i64imm:$src2),
442 "nill\t{$dst, $src2}",
443 [(set GR64:$dst, (and GR64:$src1, i64ll16c:$src2))]>;
445 def AND32rilh16 : Pseudo<(outs GR32:$dst), (ins GR32:$src1, i32imm:$src2),
446 "nilh\t{$dst, $src2}",
447 [(set GR32:$dst, (and GR32:$src1, i32lh16c:$src2))]>;
448 def AND64rilh16 : Pseudo<(outs GR64:$dst), (ins GR64:$src1, i64imm:$src2),
449 "nilh\t{$dst, $src2}",
450 [(set GR64:$dst, (and GR64:$src1, i64lh16c:$src2))]>;
452 def AND64rihl16 : Pseudo<(outs GR64:$dst), (ins GR64:$src1, i64imm:$src2),
453 "nihl\t{$dst, $src2}",
454 [(set GR64:$dst, (and GR64:$src1, i64hl16c:$src2))]>;
455 def AND64rihh16 : Pseudo<(outs GR64:$dst), (ins GR64:$src1, i64imm:$src2),
456 "nihh\t{$dst, $src2}",
457 [(set GR64:$dst, (and GR64:$src1, i64hh16c:$src2))]>;
459 def AND32ri : Pseudo<(outs GR32:$dst), (ins GR32:$src1, i32imm:$src2),
460 "nilf\t{$dst, $src2}",
461 [(set GR32:$dst, (and GR32:$src1, imm:$src2))]>;
462 def AND64rilo32 : Pseudo<(outs GR64:$dst), (ins GR64:$src1, i64imm:$src2),
463 "nilf\t{$dst, $src2}",
464 [(set GR64:$dst, (and GR64:$src1, i64lo32c:$src2))]>;
465 def AND64rihi32 : Pseudo<(outs GR64:$dst), (ins GR64:$src1, i64imm:$src2),
466 "nihf\t{$dst, $src2}",
467 [(set GR64:$dst, (and GR64:$src1, i64hi32c:$src2))]>;
469 let isCommutable = 1 in { // X = OR Y, Z == X = OR Z, Y
470 // FIXME: Provide proper encoding!
471 def OR32rr : Pseudo<(outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
473 [(set GR32:$dst, (or GR32:$src1, GR32:$src2))]>;
474 def OR64rr : Pseudo<(outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
475 "ogr\t{$dst, $src2}",
476 [(set GR64:$dst, (or GR64:$src1, GR64:$src2))]>;
479 def OR32ri16 : Pseudo<(outs GR32:$dst), (ins GR32:$src1, i32imm:$src2),
480 "oill\t{$dst, $src2}",
481 [(set GR32:$dst, (or GR32:$src1, i32ll16:$src2))]>;
482 def OR32ri16h : Pseudo<(outs GR32:$dst), (ins GR32:$src1, i32imm:$src2),
483 "oilh\t{$dst, $src2}",
484 [(set GR32:$dst, (or GR32:$src1, i32lh16:$src2))]>;
485 def OR32ri : Pseudo<(outs GR32:$dst), (ins GR32:$src1, i32imm:$src2),
486 "oilf\t{$dst, $src2}",
487 [(set GR32:$dst, (or GR32:$src1, imm:$src2))]>;
489 def OR64rill16 : Pseudo<(outs GR64:$dst), (ins GR64:$src1, i64imm:$src2),
490 "oill\t{$dst, $src2}",
491 [(set GR64:$dst, (or GR64:$src1, i64ll16:$src2))]>;
492 def OR64rilh16 : Pseudo<(outs GR64:$dst), (ins GR64:$src1, i64imm:$src2),
493 "oilh\t{$dst, $src2}",
494 [(set GR64:$dst, (or GR64:$src1, i64lh16:$src2))]>;
495 def OR64rihl16 : Pseudo<(outs GR64:$dst), (ins GR64:$src1, i64imm:$src2),
496 "oihl\t{$dst, $src2}",
497 [(set GR64:$dst, (or GR64:$src1, i64hl16:$src2))]>;
498 def OR64rihh16 : Pseudo<(outs GR64:$dst), (ins GR64:$src1, i64imm:$src2),
499 "oihh\t{$dst, $src2}",
500 [(set GR64:$dst, (or GR64:$src1, i64hh16:$src2))]>;
502 def OR64rilo32 : Pseudo<(outs GR64:$dst), (ins GR64:$src1, i64imm:$src2),
503 "oilf\t{$dst, $src2}",
504 [(set GR64:$dst, (or GR64:$src1, i64lo32:$src2))]>;
505 def OR64rihi32 : Pseudo<(outs GR64:$dst), (ins GR64:$src1, i64imm:$src2),
506 "oihf\t{$dst, $src2}",
507 [(set GR64:$dst, (or GR64:$src1, i64hi32:$src2))]>;
509 // FIXME: Provide proper encoding!
510 def SUB32rr : Pseudo<(outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
512 [(set GR32:$dst, (sub GR32:$src1, GR32:$src2))]>;
513 def SUB64rr : Pseudo<(outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
514 "sgr\t{$dst, $src2}",
515 [(set GR64:$dst, (sub GR64:$src1, GR64:$src2))]>;
518 let isCommutable = 1 in { // X = XOR Y, Z == X = XOR Z, Y
519 // FIXME: Provide proper encoding!
520 def XOR32rr : Pseudo<(outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
522 [(set GR32:$dst, (xor GR32:$src1, GR32:$src2))]>;
523 def XOR64rr : Pseudo<(outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
524 "xgr\t{$dst, $src2}",
525 [(set GR64:$dst, (xor GR64:$src1, GR64:$src2))]>;
528 def XOR32ri : Pseudo<(outs GR32:$dst), (ins GR32:$src1, i32imm:$src2),
529 "xilf\t{$dst, $src2}",
530 [(set GR32:$dst, (xor GR32:$src1, imm:$src2))]>;
534 let isCommutable = 1 in { // X = MUL Y, Z == X = MUL Z, Y
535 def MUL32rr : Pseudo<(outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
536 "msr\t{$dst, $src2}",
537 [(set GR32:$dst, (mul GR32:$src1, GR32:$src2))]>;
538 def MUL64rr : Pseudo<(outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
539 "msgr\t{$dst, $src2}",
540 [(set GR64:$dst, (mul GR64:$src1, GR64:$src2))]>;
542 def MUL64rrP : Pseudo<(outs GR64P:$dst), (ins GR64P:$src1, GR32:$src2),
545 def UMUL64rrP : Pseudo<(outs GR64P:$dst), (ins GR64P:$src1, GR32:$src2),
546 "mlr\t{$dst, $src2}",
548 def UMUL128rrP : Pseudo<(outs GR128:$dst), (ins GR128:$src1, GR64:$src2),
549 "mlgr\t{$dst, $src2}",
554 def MUL32ri16 : Pseudo<(outs GR32:$dst), (ins GR32:$src1, s16imm:$src2),
555 "mhi\t{$dst, $src2}",
556 [(set GR32:$dst, (mul GR32:$src1, i32immSExt16:$src2))]>;
557 def MUL64ri16 : Pseudo<(outs GR64:$dst), (ins GR64:$src1, s16imm64:$src2),
558 "mghi\t{$dst, $src2}",
559 [(set GR64:$dst, (mul GR64:$src1, immSExt16:$src2))]>;
561 def MUL32ri : Pseudo<(outs GR32:$dst), (ins GR32:$src1, s32imm:$src2),
562 "msfi\t{$dst, $src2}",
563 [(set GR32:$dst, (mul GR32:$src1, imm:$src2))]>,
565 def MUL64ri32 : Pseudo<(outs GR64:$dst), (ins GR64:$src1, s32imm64:$src2),
566 "msgfi\t{$dst, $src2}",
567 [(set GR64:$dst, (mul GR64:$src1, i64immSExt32:$src2))]>,
570 def MUL32rm : Pseudo<(outs GR32:$dst), (ins GR32:$src1, rriaddr12:$src2),
572 [(set GR32:$dst, (mul GR32:$src1, (load rriaddr12:$src2)))]>;
573 def MUL32rmy : Pseudo<(outs GR32:$dst), (ins GR32:$src1, rriaddr:$src2),
574 "msy\t{$dst, $src2}",
575 [(set GR32:$dst, (mul GR32:$src1, (load rriaddr:$src2)))]>;
576 def MUL64rm : Pseudo<(outs GR64:$dst), (ins GR64:$src1, rriaddr:$src2),
577 "msg\t{$dst, $src2}",
578 [(set GR64:$dst, (mul GR64:$src1, (load rriaddr:$src2)))]>;
580 def MULSX64rr32 : Pseudo<(outs GR64:$dst), (ins GR64:$src1, GR32:$src2),
581 "msgfr\t{$dst, $src2}",
582 [(set GR64:$dst, (mul GR64:$src1, (sext GR32:$src2)))]>;
584 def SDIVREM64rrP : Pseudo<(outs GR64P:$dst), (ins GR64P:$src1, GR32:$src2),
588 def SDIVREM128rrP : Pseudo<(outs GR128:$dst), (ins GR128:$src1, GR64:$src2),
589 "dsgr\t{$dst, $src2}",
592 def UDIVREM64rrP : Pseudo<(outs GR64P:$dst), (ins GR64P:$src1, GR32:$src2),
593 "dlr\t{$dst, $src2}",
596 def UDIVREM128rrP : Pseudo<(outs GR128:$dst), (ins GR128:$src1, GR64:$src2),
597 "dlgr\t{$dst, $src2}",
600 } // isTwoAddress = 1
602 //===----------------------------------------------------------------------===//
605 let isTwoAddress = 1 in
606 def SRL32rri : Pseudo<(outs GR32:$dst), (ins GR32:$src, riaddr32:$amt),
608 [(set GR32:$dst, (srl GR32:$src, riaddr32:$amt))]>;
609 def SRL64rri : Pseudo<(outs GR64:$dst), (ins GR64:$src, riaddr:$amt),
610 "srlg\t{$dst, $src, $amt}",
611 [(set GR64:$dst, (srl GR64:$src, (i32 (trunc riaddr:$amt))))]>;
612 def SRLA64ri : Pseudo<(outs GR64:$dst), (ins GR64:$src, i32imm:$amt),
613 "srlg\t{$dst, $src, $amt}",
614 [(set GR64:$dst, (srl GR64:$src, (i32 imm:$amt)))]>;
616 let isTwoAddress = 1 in
617 def SHL32rri : Pseudo<(outs GR32:$dst), (ins GR32:$src, riaddr32:$amt),
619 [(set GR32:$dst, (shl GR32:$src, riaddr32:$amt))]>;
620 def SHL64rri : Pseudo<(outs GR64:$dst), (ins GR64:$src, riaddr:$amt),
621 "sllg\t{$dst, $src, $amt}",
622 [(set GR64:$dst, (shl GR64:$src, (i32 (trunc riaddr:$amt))))]>;
623 def SHL64ri : Pseudo<(outs GR64:$dst), (ins GR64:$src, i32imm:$amt),
624 "sllg\t{$dst, $src, $amt}",
625 [(set GR64:$dst, (shl GR64:$src, (i32 imm:$amt)))]>;
627 let Defs = [PSW] in {
628 let isTwoAddress = 1 in
629 def SRA32rri : Pseudo<(outs GR32:$dst), (ins GR32:$src, riaddr32:$amt),
631 [(set GR32:$dst, (sra GR32:$src, riaddr32:$amt)),
633 def SRA64rri : Pseudo<(outs GR64:$dst), (ins GR64:$src, riaddr:$amt),
634 "srag\t{$dst, $src, $amt}",
635 [(set GR64:$dst, (sra GR64:$src, (i32 (trunc riaddr:$amt)))),
637 def SRA64ri : Pseudo<(outs GR64:$dst), (ins GR64:$src, i32imm:$amt),
638 "srag\t{$dst, $src, $amt}",
639 [(set GR64:$dst, (sra GR64:$src, (i32 imm:$amt))),
643 let isTwoAddress = 1 in
644 def ROTL32rri : Pseudo<(outs GR32:$dst), (ins GR32:$src, riaddr32:$amt),
646 [(set GR32:$dst, (rotl GR32:$src, riaddr32:$amt))]>;
647 def ROTL64rri : Pseudo<(outs GR64:$dst), (ins GR64:$src, riaddr:$amt),
648 "rllg\t{$dst, $src, $amt}",
649 [(set GR64:$dst, (rotl GR64:$src, (i32 (trunc riaddr:$amt))))]>;
650 def ROTL64ri : Pseudo<(outs GR64:$dst), (ins GR64:$src, i32imm:$amt),
651 "rllg\t{$dst, $src, $amt}",
652 [(set GR64:$dst, (rotl GR64:$src, (i32 imm:$amt)))]>;
654 //===----------------------------------------------------------------------===//
655 // Test instructions (like AND but do not produce any result)
657 // Integer comparisons
658 let Defs = [PSW] in {
659 def CMP32rr : Pseudo<(outs), (ins GR32:$src1, GR32:$src2),
661 [(SystemZcmp GR32:$src1, GR32:$src2), (implicit PSW)]>;
662 def CMP64rr : Pseudo<(outs), (ins GR64:$src1, GR64:$src2),
664 [(SystemZcmp GR64:$src1, GR64:$src2), (implicit PSW)]>;
666 def CMP32ri : Pseudo<(outs), (ins GR32:$src1, s32imm:$src2),
668 [(SystemZcmp GR32:$src1, imm:$src2), (implicit PSW)]>;
669 def CMP64ri32 : Pseudo<(outs), (ins GR64:$src1, s32imm64:$src2),
670 "cgfi\t$src1, $src2",
671 [(SystemZcmp GR64:$src1, i64immSExt32:$src2),
674 def CMP32rm : Pseudo<(outs), (ins GR32:$src1, rriaddr12:$src2),
676 [(SystemZcmp GR32:$src1, (load rriaddr12:$src2)),
678 def CMP32rmy : Pseudo<(outs), (ins GR32:$src1, rriaddr:$src2),
680 [(SystemZcmp GR32:$src1, (load rriaddr:$src2)),
682 def CMP64rm : Pseudo<(outs), (ins GR64:$src1, rriaddr:$src2),
684 [(SystemZcmp GR64:$src1, (load rriaddr:$src2)),
687 def UCMP32rr : Pseudo<(outs), (ins GR32:$src1, GR32:$src2),
689 [(SystemZucmp GR32:$src1, GR32:$src2), (implicit PSW)]>;
690 def UCMP64rr : Pseudo<(outs), (ins GR64:$src1, GR64:$src2),
691 "clgr\t$src1, $src2",
692 [(SystemZucmp GR64:$src1, GR64:$src2), (implicit PSW)]>;
694 def UCMP32ri : Pseudo<(outs), (ins GR32:$src1, i32imm:$src2),
695 "clfi\t$src1, $src2",
696 [(SystemZucmp GR32:$src1, imm:$src2), (implicit PSW)]>;
697 def UCMP64ri32 : Pseudo<(outs), (ins GR64:$src1, i64i32imm:$src2),
698 "clgfi\t$src1, $src2",
699 [(SystemZucmp GR64:$src1, i64immZExt32:$src2),
702 def UCMP32rm : Pseudo<(outs), (ins GR32:$src1, rriaddr12:$src2),
704 [(SystemZucmp GR32:$src1, (load rriaddr12:$src2)),
706 def UCMP32rmy : Pseudo<(outs), (ins GR32:$src1, rriaddr:$src2),
708 [(SystemZucmp GR32:$src1, (load rriaddr:$src2)),
710 def UCMP64rm : Pseudo<(outs), (ins GR64:$src1, rriaddr:$src2),
712 [(SystemZucmp GR64:$src1, (load rriaddr:$src2)),
715 def CMPSX64rr32 : Pseudo<(outs), (ins GR64:$src1, GR32:$src2),
716 "cgfr\t$src1, $src2",
717 [(SystemZucmp GR64:$src1, (sext GR32:$src2)),
719 def UCMPZX64rr32 : Pseudo<(outs), (ins GR64:$src1, GR32:$src2),
720 "clgfr\t$src1, $src2",
721 [(SystemZucmp GR64:$src1, (zext GR32:$src2)),
724 def CMPSX64rm32 : Pseudo<(outs), (ins GR64:$src1, rriaddr:$src2),
726 [(SystemZucmp GR64:$src1, (sextloadi64i32 rriaddr:$src2)),
728 def UCMPZX64rm32 : Pseudo<(outs), (ins GR64:$src1, rriaddr:$src2),
729 "clgf\t$src1, $src2",
730 [(SystemZucmp GR64:$src1, (zextloadi64i32 rriaddr:$src2)),
733 // FIXME: Add other crazy ucmp forms
737 //===----------------------------------------------------------------------===//
738 // Non-Instruction Patterns.
739 //===----------------------------------------------------------------------===//
742 def : Pat<(SystemZpcrelwrapper tjumptable:$src), (LA64rm tjumptable:$src)>;
745 def : Pat<(i64 (anyext GR32:$src)),
746 (INSERT_SUBREG (i64 (IMPLICIT_DEF)), GR32:$src, subreg_32bit)>;
749 def : Pat<(SystemZcall (i64 tglobaladdr:$dst)), (CALLi tglobaladdr:$dst)>;
750 def : Pat<(SystemZcall (i64 texternalsym:$dst)), (CALLi texternalsym:$dst)>;
752 //===----------------------------------------------------------------------===//
754 //===----------------------------------------------------------------------===//
756 // FIXME: use add/sub tricks with 32678/-32768
758 // Arbitrary immediate support. Implement in terms of LLIHF/OILF.
759 def : Pat<(i64 imm:$imm),
760 (OR64rilo32 (MOV64rihi32 (HI32 imm:$imm)), (LO32 imm:$imm))>;
763 def : Pat<(i32 (trunc GR64:$src)),
764 (EXTRACT_SUBREG GR64:$src, subreg_32bit)>;
766 // sext_inreg patterns
767 def : Pat<(sext_inreg GR64:$src, i32),
768 (MOVSX64rr32 (EXTRACT_SUBREG GR64:$src, subreg_32bit))>;
771 def : Pat<(extloadi32i8 rriaddr:$src), (MOVZX32rm8 rriaddr:$src)>;
772 def : Pat<(extloadi32i16 rriaddr:$src), (MOVZX32rm16 rriaddr:$src)>;
773 def : Pat<(extloadi64i8 rriaddr:$src), (MOVZX64rm8 rriaddr:$src)>;
774 def : Pat<(extloadi64i16 rriaddr:$src), (MOVZX64rm16 rriaddr:$src)>;
775 def : Pat<(extloadi64i32 rriaddr:$src), (MOVZX64rm32 rriaddr:$src)>;
778 def : Pat<(mulhs GR32:$src1, GR32:$src2),
779 (EXTRACT_SUBREG (MUL64rrP (INSERT_SUBREG (i64 (IMPLICIT_DEF)),
780 GR32:$src1, subreg_odd),
784 def : Pat<(mulhu GR32:$src1, GR32:$src2),
785 (EXTRACT_SUBREG (UMUL64rrP (INSERT_SUBREG (i64 (IMPLICIT_DEF)),
786 GR32:$src1, subreg_odd),
789 def : Pat<(mulhu GR64:$src1, GR64:$src2),
790 (EXTRACT_SUBREG (UMUL128rrP (INSERT_SUBREG (i128 (IMPLICIT_DEF)),
791 GR64:$src1, subreg_odd),
796 // FIXME: Add memory versions
797 def : Pat<(sdiv GR32:$src1, GR32:$src2),
798 (EXTRACT_SUBREG (SDIVREM64rrP (INSERT_SUBREG (i64 (IMPLICIT_DEF)),
799 GR32:$src1, subreg_odd),
802 def : Pat<(sdiv GR64:$src1, GR64:$src2),
803 (EXTRACT_SUBREG (SDIVREM128rrP (INSERT_SUBREG (i128 (IMPLICIT_DEF)),
804 GR64:$src1, subreg_odd),
807 def : Pat<(udiv GR32:$src1, GR32:$src2),
808 (EXTRACT_SUBREG (UDIVREM64rrP (INSERT_SUBREG (i64 (IMPLICIT_DEF)),
809 GR32:$src1, subreg_odd),
812 def : Pat<(udiv GR64:$src1, GR64:$src2),
813 (EXTRACT_SUBREG (UDIVREM128rrP (INSERT_SUBREG (i128 (IMPLICIT_DEF)),
814 GR64:$src1, subreg_odd),
819 // FIXME: Add memory versions
820 def : Pat<(srem GR32:$src1, GR32:$src2),
821 (EXTRACT_SUBREG (SDIVREM64rrP (INSERT_SUBREG (i64 (IMPLICIT_DEF)),
822 GR32:$src1, subreg_odd),
825 def : Pat<(srem GR64:$src1, GR64:$src2),
826 (EXTRACT_SUBREG (SDIVREM128rrP (INSERT_SUBREG (i128 (IMPLICIT_DEF)),
827 GR64:$src1, subreg_odd),
830 def : Pat<(urem GR32:$src1, GR32:$src2),
831 (EXTRACT_SUBREG (UDIVREM64rrP (INSERT_SUBREG (i64 (IMPLICIT_DEF)),
832 GR32:$src1, subreg_odd),
835 def : Pat<(urem GR64:$src1, GR64:$src2),
836 (EXTRACT_SUBREG (UDIVREM128rrP (INSERT_SUBREG (i128 (IMPLICIT_DEF)),
837 GR64:$src1, subreg_odd),
841 def : Pat<(i32 imm:$src),
842 (EXTRACT_SUBREG (MOV64ri32 (i64 imm:$src)), subreg_32bit)>;