1 //===-- SystemZInstrInfo.td - General SystemZ instructions ----*- tblgen-*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 //===----------------------------------------------------------------------===//
12 //===----------------------------------------------------------------------===//
14 def ADJCALLSTACKDOWN : Pseudo<(outs), (ins i64imm:$amt),
15 [(callseq_start timm:$amt)]>;
16 def ADJCALLSTACKUP : Pseudo<(outs), (ins i64imm:$amt1, i64imm:$amt2),
17 [(callseq_end timm:$amt1, timm:$amt2)]>;
19 let neverHasSideEffects = 1 in {
20 // Takes as input the value of the stack pointer after a dynamic allocation
21 // has been made. Sets the output to the address of the dynamically-
22 // allocated area itself, skipping the outgoing arguments.
24 // This expands to an LA or LAY instruction. We restrict the offset
25 // to the range of LA and keep the LAY range in reserve for when
26 // the size of the outgoing arguments is added.
27 def ADJDYNALLOC : Pseudo<(outs GR64:$dst), (ins dynalloc12only:$src),
28 [(set GR64:$dst, dynalloc12only:$src)]>;
31 //===----------------------------------------------------------------------===//
32 // Control flow instructions
33 //===----------------------------------------------------------------------===//
35 // A return instruction. R1 is the condition-code mask (all 1s)
36 // and R2 is the target address, which is always stored in %r14.
37 let isReturn = 1, isTerminator = 1, isBarrier = 1, hasCtrlDep = 1,
38 R1 = 15, R2 = 14, isCodeGenOnly = 1 in {
39 def RET : InstRR<0x07, (outs), (ins), "br\t%r14", [(z_retflag)]>;
42 // Unconditional branches. R1 is the condition-code mask (all 1s).
43 let isBranch = 1, isTerminator = 1, isBarrier = 1, R1 = 15 in {
44 let isIndirectBranch = 1 in
45 def BR : InstRR<0x07, (outs), (ins ADDR64:$R2),
46 "br\t$R2", [(brind ADDR64:$R2)]>;
48 // An assembler extended mnemonic for BRC.
49 def J : InstRI<0xA74, (outs), (ins brtarget16:$I2), "j\t$I2",
52 // An assembler extended mnemonic for BRCL. (The extension is "G"
53 // rather than "L" because "JL" is "Jump if Less".)
54 def JG : InstRIL<0xC04, (outs), (ins brtarget32:$I2), "jg\t$I2", []>;
57 // Conditional branches. It's easier for LLVM to handle these branches
58 // in their raw BRC/BRCL form, with the 4-bit condition-code mask being
59 // the first operand. It seems friendlier to use mnemonic forms like
60 // JE and JLH when writing out the assembly though.
62 // Using a custom inserter for BRC gives us a chance to convert the BRC
63 // and a preceding compare into a single compare-and-branch instruction.
64 // The inserter makes no change in cases where a separate branch really
66 multiclass CondBranches<Operand ccmask, string short, string long> {
67 let isBranch = 1, isTerminator = 1, Uses = [CC] in {
68 def "" : InstRI<0xA74, (outs), (ins ccmask:$R1, brtarget16:$I2), short, []>;
69 def L : InstRIL<0xC04, (outs), (ins ccmask:$R1, brtarget32:$I2), long, []>;
72 let isCodeGenOnly = 1, usesCustomInserter = 1 in
73 defm BRC : CondBranches<cond4, "j$R1\t$I2", "jg$R1\t$I2">;
74 defm AsmBRC : CondBranches<uimm8zx4, "brc\t$R1, $I2", "brcl\t$R1, $I2">;
76 def : Pat<(z_br_ccmask cond4:$cond, bb:$dst), (BRC cond4:$cond, bb:$dst)>;
78 // Fused compare-and-branch instructions. As for normal branches,
79 // we handle these instructions internally in their raw CRJ-like form,
80 // but use assembly macros like CRJE when writing them out.
82 // These instructions do not use or clobber the condition codes.
83 // We nevertheless pretend that they clobber CC, so that we can lower
84 // them to separate comparisons and BRCLs if the branch ends up being
86 multiclass CompareBranches<Operand ccmask, string pos1, string pos2> {
87 let isBranch = 1, isTerminator = 1, Defs = [CC] in {
88 def RJ : InstRIEb<0xEC76, (outs), (ins GR32:$R1, GR32:$R2, ccmask:$M3,
90 "crj"##pos1##"\t$R1, $R2, "##pos2##"$RI4", []>;
91 def GRJ : InstRIEb<0xEC64, (outs), (ins GR64:$R1, GR64:$R2, ccmask:$M3,
93 "cgrj"##pos1##"\t$R1, $R2, "##pos2##"$RI4", []>;
94 def IJ : InstRIEc<0xEC7E, (outs), (ins GR32:$R1, imm32sx8:$I2, ccmask:$M3,
96 "cij"##pos1##"\t$R1, $I2, "##pos2##"$RI4", []>;
97 def GIJ : InstRIEc<0xEC7C, (outs), (ins GR64:$R1, imm64sx8:$I2, ccmask:$M3,
99 "cgij"##pos1##"\t$R1, $I2, "##pos2##"$RI4", []>;
102 let isCodeGenOnly = 1 in
103 defm C : CompareBranches<cond4, "$M3", "">;
104 defm AsmC : CompareBranches<uimm8zx4, "", "$M3, ">;
106 // Define AsmParser mnemonics for each general condition-code mask
107 // (integer or floating-point)
108 multiclass CondExtendedMnemonic<bits<4> ccmask, string name> {
110 def "" : InstRI<0xA74, (outs), (ins brtarget16:$I2),
111 "j"##name##"\t$I2", []>;
112 def L : InstRIL<0xC04, (outs), (ins brtarget32:$I2),
113 "jg"##name##"\t$I2", []>;
116 defm AsmJO : CondExtendedMnemonic<1, "o">;
117 defm AsmJH : CondExtendedMnemonic<2, "h">;
118 defm AsmJNLE : CondExtendedMnemonic<3, "nle">;
119 defm AsmJL : CondExtendedMnemonic<4, "l">;
120 defm AsmJNHE : CondExtendedMnemonic<5, "nhe">;
121 defm AsmJLH : CondExtendedMnemonic<6, "lh">;
122 defm AsmJNE : CondExtendedMnemonic<7, "ne">;
123 defm AsmJE : CondExtendedMnemonic<8, "e">;
124 defm AsmJNLH : CondExtendedMnemonic<9, "nlh">;
125 defm AsmJHE : CondExtendedMnemonic<10, "he">;
126 defm AsmJNL : CondExtendedMnemonic<11, "nl">;
127 defm AsmJLE : CondExtendedMnemonic<12, "le">;
128 defm AsmJNH : CondExtendedMnemonic<13, "nh">;
129 defm AsmJNO : CondExtendedMnemonic<14, "no">;
131 // Define AsmParser mnemonics for each integer condition-code mask.
132 // This is like the list above, except that condition 3 is not possible
133 // and that the low bit of the mask is therefore always 0. This means
134 // that each condition has two names. Conditions "o" and "no" are not used.
136 // We don't make one of the two names an alias of the other because
137 // we need the custom parsing routines to select the correct register class.
138 multiclass IntCondExtendedMnemonicA<bits<4> ccmask, string name> {
140 def CR : InstRIEb<0xEC76, (outs), (ins GR32:$R1, GR32:$R2,
142 "crj"##name##"\t$R1, $R2, $RI4", []>;
143 def CGR : InstRIEb<0xEC64, (outs), (ins GR64:$R1, GR64:$R2,
145 "cgrj"##name##"\t$R1, $R2, $RI4", []>;
146 def CI : InstRIEc<0xEC7E, (outs), (ins GR32:$R1, imm32sx8:$I2,
148 "cij"##name##"\t$R1, $I2, $RI4", []>;
149 def CGI : InstRIEc<0xEC7C, (outs), (ins GR64:$R1, imm64sx8:$I2,
151 "cgij"##name##"\t$R1, $I2, $RI4", []>;
154 multiclass IntCondExtendedMnemonic<bits<4> ccmask, string name1, string name2>
155 : IntCondExtendedMnemonicA<ccmask, name1> {
156 let isAsmParserOnly = 1 in
157 defm Alt : IntCondExtendedMnemonicA<ccmask, name2>;
159 defm AsmJH : IntCondExtendedMnemonic<2, "h", "nle">;
160 defm AsmJL : IntCondExtendedMnemonic<4, "l", "nhe">;
161 defm AsmJLH : IntCondExtendedMnemonic<6, "lh", "ne">;
162 defm AsmJE : IntCondExtendedMnemonic<8, "e", "nlh">;
163 defm AsmJHE : IntCondExtendedMnemonic<10, "he", "nl">;
164 defm AsmJLE : IntCondExtendedMnemonic<12, "le", "nh">;
166 //===----------------------------------------------------------------------===//
167 // Select instructions
168 //===----------------------------------------------------------------------===//
170 def Select32 : SelectWrapper<GR32>;
171 def Select64 : SelectWrapper<GR64>;
173 defm CondStore8_32 : CondStores<GR32, nonvolatile_truncstorei8,
174 nonvolatile_anyextloadi8, bdxaddr20only>;
175 defm CondStore16_32 : CondStores<GR32, nonvolatile_truncstorei16,
176 nonvolatile_anyextloadi16, bdxaddr20only>;
177 defm CondStore32_32 : CondStores<GR32, nonvolatile_store,
178 nonvolatile_load, bdxaddr20only>;
180 defm CondStore8 : CondStores<GR64, nonvolatile_truncstorei8,
181 nonvolatile_anyextloadi8, bdxaddr20only>;
182 defm CondStore16 : CondStores<GR64, nonvolatile_truncstorei16,
183 nonvolatile_anyextloadi16, bdxaddr20only>;
184 defm CondStore32 : CondStores<GR64, nonvolatile_truncstorei32,
185 nonvolatile_anyextloadi32, bdxaddr20only>;
186 defm CondStore64 : CondStores<GR64, nonvolatile_store,
187 nonvolatile_load, bdxaddr20only>;
189 //===----------------------------------------------------------------------===//
191 //===----------------------------------------------------------------------===//
193 // The definitions here are for the call-clobbered registers.
194 let isCall = 1, Defs = [R0D, R1D, R2D, R3D, R4D, R5D, R14D,
195 F0D, F1D, F2D, F3D, F4D, F5D, F6D, F7D],
196 R1 = 14, isCodeGenOnly = 1 in {
197 def BRAS : InstRI<0xA75, (outs), (ins pcrel16call:$I2, variable_ops),
198 "bras\t%r14, $I2", []>;
199 def BRASL : InstRIL<0xC05, (outs), (ins pcrel32call:$I2, variable_ops),
200 "brasl\t%r14, $I2", [(z_call pcrel32call:$I2)]>;
201 def BASR : InstRR<0x0D, (outs), (ins ADDR64:$R2, variable_ops),
202 "basr\t%r14, $R2", [(z_call ADDR64:$R2)]>;
205 // Define the general form of the call instructions for the asm parser.
206 // These instructions don't hard-code %r14 as the return address register.
207 def AsmBRAS : InstRI<0xA75, (outs), (ins GR64:$R1, brtarget16:$I2),
208 "bras\t$R1, $I2", []>;
209 def AsmBRASL : InstRIL<0xC05, (outs), (ins GR64:$R1, brtarget32:$I2),
210 "brasl\t$R1, $I2", []>;
211 def AsmBASR : InstRR<0x0D, (outs), (ins GR64:$R1, ADDR64:$R2),
212 "basr\t$R1, $R2", []>;
214 //===----------------------------------------------------------------------===//
216 //===----------------------------------------------------------------------===//
219 let neverHasSideEffects = 1 in {
220 def LR : UnaryRR <"l", 0x18, null_frag, GR32, GR32>;
221 def LGR : UnaryRRE<"lg", 0xB904, null_frag, GR64, GR64>;
225 let neverHasSideEffects = 1, isAsCheapAsAMove = 1, isMoveImm = 1,
226 isReMaterializable = 1 in {
227 // 16-bit sign-extended immediates.
228 def LHI : UnaryRI<"lhi", 0xA78, bitconvert, GR32, imm32sx16>;
229 def LGHI : UnaryRI<"lghi", 0xA79, bitconvert, GR64, imm64sx16>;
231 // Other 16-bit immediates.
232 def LLILL : UnaryRI<"llill", 0xA5F, bitconvert, GR64, imm64ll16>;
233 def LLILH : UnaryRI<"llilh", 0xA5E, bitconvert, GR64, imm64lh16>;
234 def LLIHL : UnaryRI<"llihl", 0xA5D, bitconvert, GR64, imm64hl16>;
235 def LLIHH : UnaryRI<"llihh", 0xA5C, bitconvert, GR64, imm64hh16>;
237 // 32-bit immediates.
238 def LGFI : UnaryRIL<"lgfi", 0xC01, bitconvert, GR64, imm64sx32>;
239 def LLILF : UnaryRIL<"llilf", 0xC0F, bitconvert, GR64, imm64lf32>;
240 def LLIHF : UnaryRIL<"llihf", 0xC0E, bitconvert, GR64, imm64hf32>;
244 let canFoldAsLoad = 1, SimpleBDXLoad = 1 in {
245 defm L : UnaryRXPair<"l", 0x58, 0xE358, load, GR32, 4>;
246 def LG : UnaryRXY<"lg", 0xE304, load, GR64, 8>;
248 // These instructions are split after register allocation, so we don't
249 // want a custom inserter.
250 let Has20BitOffset = 1, HasIndex = 1, Is128Bit = 1 in {
251 def L128 : Pseudo<(outs GR128:$dst), (ins bdxaddr20only128:$src),
252 [(set GR128:$dst, (load bdxaddr20only128:$src))]>;
255 let canFoldAsLoad = 1 in {
256 def LRL : UnaryRILPC<"lrl", 0xC4D, aligned_load, GR32>;
257 def LGRL : UnaryRILPC<"lgrl", 0xC48, aligned_load, GR64>;
261 let SimpleBDXStore = 1 in {
262 let isCodeGenOnly = 1 in
263 defm ST32 : StoreRXPair<"st", 0x50, 0xE350, store, GR32, 4>;
264 def STG : StoreRXY<"stg", 0xE324, store, GR64, 8>;
266 // These instructions are split after register allocation, so we don't
267 // want a custom inserter.
268 let Has20BitOffset = 1, HasIndex = 1, Is128Bit = 1 in {
269 def ST128 : Pseudo<(outs), (ins GR128:$src, bdxaddr20only128:$dst),
270 [(store GR128:$src, bdxaddr20only128:$dst)]>;
273 let isCodeGenOnly = 1 in
274 def STRL32 : StoreRILPC<"strl", 0xC4F, aligned_store, GR32>;
275 def STGRL : StoreRILPC<"stgrl", 0xC4B, aligned_store, GR64>;
277 // 8-bit immediate stores to 8-bit fields.
278 defm MVI : StoreSIPair<"mvi", 0x92, 0xEB52, truncstorei8, imm32zx8trunc>;
280 // 16-bit immediate stores to 16-, 32- or 64-bit fields.
281 def MVHHI : StoreSIL<"mvhhi", 0xE544, truncstorei16, imm32sx16trunc>;
282 def MVHI : StoreSIL<"mvhi", 0xE54C, store, imm32sx16>;
283 def MVGHI : StoreSIL<"mvghi", 0xE548, store, imm64sx16>;
285 // Memory-to-memory moves.
286 let mayLoad = 1, mayStore = 1 in
287 def MVC : InstSS<0xD2, (outs), (ins bdladdr12onlylen8:$BDL1,
289 "mvc\t$BDL1, $BD2", []>;
291 //===----------------------------------------------------------------------===//
293 //===----------------------------------------------------------------------===//
295 // 32-bit extensions from registers.
296 let neverHasSideEffects = 1 in {
297 def LBR : UnaryRRE<"lb", 0xB926, sext8, GR32, GR32>;
298 def LHR : UnaryRRE<"lh", 0xB927, sext16, GR32, GR32>;
301 // 64-bit extensions from registers.
302 let neverHasSideEffects = 1 in {
303 def LGBR : UnaryRRE<"lgb", 0xB906, sext8, GR64, GR64>;
304 def LGHR : UnaryRRE<"lgh", 0xB907, sext16, GR64, GR64>;
305 def LGFR : UnaryRRE<"lgf", 0xB914, sext32, GR64, GR32>;
308 // Match 32-to-64-bit sign extensions in which the source is already
309 // in a 64-bit register.
310 def : Pat<(sext_inreg GR64:$src, i32),
311 (LGFR (EXTRACT_SUBREG GR64:$src, subreg_32bit))>;
313 // 32-bit extensions from memory.
314 def LB : UnaryRXY<"lb", 0xE376, sextloadi8, GR32, 1>;
315 defm LH : UnaryRXPair<"lh", 0x48, 0xE378, sextloadi16, GR32, 2>;
316 def LHRL : UnaryRILPC<"lhrl", 0xC45, aligned_sextloadi16, GR32>;
318 // 64-bit extensions from memory.
319 def LGB : UnaryRXY<"lgb", 0xE377, sextloadi8, GR64, 1>;
320 def LGH : UnaryRXY<"lgh", 0xE315, sextloadi16, GR64, 2>;
321 def LGF : UnaryRXY<"lgf", 0xE314, sextloadi32, GR64, 4>;
322 def LGHRL : UnaryRILPC<"lghrl", 0xC44, aligned_sextloadi16, GR64>;
323 def LGFRL : UnaryRILPC<"lgfrl", 0xC4C, aligned_sextloadi32, GR64>;
325 // If the sign of a load-extend operation doesn't matter, use the signed ones.
326 // There's not really much to choose between the sign and zero extensions,
327 // but LH is more compact than LLH for small offsets.
328 def : Pat<(i32 (extloadi8 bdxaddr20only:$src)), (LB bdxaddr20only:$src)>;
329 def : Pat<(i32 (extloadi16 bdxaddr12pair:$src)), (LH bdxaddr12pair:$src)>;
330 def : Pat<(i32 (extloadi16 bdxaddr20pair:$src)), (LHY bdxaddr20pair:$src)>;
332 def : Pat<(i64 (extloadi8 bdxaddr20only:$src)), (LGB bdxaddr20only:$src)>;
333 def : Pat<(i64 (extloadi16 bdxaddr20only:$src)), (LGH bdxaddr20only:$src)>;
334 def : Pat<(i64 (extloadi32 bdxaddr20only:$src)), (LGF bdxaddr20only:$src)>;
336 //===----------------------------------------------------------------------===//
338 //===----------------------------------------------------------------------===//
340 // 32-bit extensions from registers.
341 let neverHasSideEffects = 1 in {
342 def LLCR : UnaryRRE<"llc", 0xB994, zext8, GR32, GR32>;
343 def LLHR : UnaryRRE<"llh", 0xB995, zext16, GR32, GR32>;
346 // 64-bit extensions from registers.
347 let neverHasSideEffects = 1 in {
348 def LLGCR : UnaryRRE<"llgc", 0xB984, zext8, GR64, GR64>;
349 def LLGHR : UnaryRRE<"llgh", 0xB985, zext16, GR64, GR64>;
350 def LLGFR : UnaryRRE<"llgf", 0xB916, zext32, GR64, GR32>;
353 // Match 32-to-64-bit zero extensions in which the source is already
354 // in a 64-bit register.
355 def : Pat<(and GR64:$src, 0xffffffff),
356 (LLGFR (EXTRACT_SUBREG GR64:$src, subreg_32bit))>;
358 // 32-bit extensions from memory.
359 def LLC : UnaryRXY<"llc", 0xE394, zextloadi8, GR32, 1>;
360 def LLH : UnaryRXY<"llh", 0xE395, zextloadi16, GR32, 2>;
361 def LLHRL : UnaryRILPC<"llhrl", 0xC42, aligned_zextloadi16, GR32>;
363 // 64-bit extensions from memory.
364 def LLGC : UnaryRXY<"llgc", 0xE390, zextloadi8, GR64, 1>;
365 def LLGH : UnaryRXY<"llgh", 0xE391, zextloadi16, GR64, 2>;
366 def LLGF : UnaryRXY<"llgf", 0xE316, zextloadi32, GR64, 4>;
367 def LLGHRL : UnaryRILPC<"llghrl", 0xC46, aligned_zextloadi16, GR64>;
368 def LLGFRL : UnaryRILPC<"llgfrl", 0xC4E, aligned_zextloadi32, GR64>;
370 //===----------------------------------------------------------------------===//
372 //===----------------------------------------------------------------------===//
374 // Truncations of 64-bit registers to 32-bit registers.
375 def : Pat<(i32 (trunc GR64:$src)),
376 (EXTRACT_SUBREG GR64:$src, subreg_32bit)>;
378 // Truncations of 32-bit registers to memory.
379 let isCodeGenOnly = 1 in {
380 defm STC32 : StoreRXPair<"stc", 0x42, 0xE372, truncstorei8, GR32, 1>;
381 defm STH32 : StoreRXPair<"sth", 0x40, 0xE370, truncstorei16, GR32, 2>;
382 def STHRL32 : StoreRILPC<"sthrl", 0xC47, aligned_truncstorei16, GR32>;
385 // Truncations of 64-bit registers to memory.
386 defm STC : StoreRXPair<"stc", 0x42, 0xE372, truncstorei8, GR64, 1>;
387 defm STH : StoreRXPair<"sth", 0x40, 0xE370, truncstorei16, GR64, 2>;
388 def STHRL : StoreRILPC<"sthrl", 0xC47, aligned_truncstorei16, GR64>;
389 defm ST : StoreRXPair<"st", 0x50, 0xE350, truncstorei32, GR64, 4>;
390 def STRL : StoreRILPC<"strl", 0xC4F, aligned_truncstorei32, GR64>;
392 //===----------------------------------------------------------------------===//
393 // Multi-register moves
394 //===----------------------------------------------------------------------===//
396 // Multi-register loads.
397 def LMG : LoadMultipleRSY<"lmg", 0xEB04, GR64>;
399 // Multi-register stores.
400 def STMG : StoreMultipleRSY<"stmg", 0xEB24, GR64>;
402 //===----------------------------------------------------------------------===//
404 //===----------------------------------------------------------------------===//
406 // Byte-swapping register moves.
407 let neverHasSideEffects = 1 in {
408 def LRVR : UnaryRRE<"lrv", 0xB91F, bswap, GR32, GR32>;
409 def LRVGR : UnaryRRE<"lrvg", 0xB90F, bswap, GR64, GR64>;
412 // Byte-swapping loads. Unlike normal loads, these instructions are
413 // allowed to access storage more than once.
414 def LRV : UnaryRXY<"lrv", 0xE31E, loadu<bswap, nonvolatile_load>, GR32, 4>;
415 def LRVG : UnaryRXY<"lrvg", 0xE30F, loadu<bswap, nonvolatile_load>, GR64, 8>;
417 // Likewise byte-swapping stores.
418 def STRV : StoreRXY<"strv", 0xE33E, storeu<bswap, nonvolatile_store>, GR32, 4>;
419 def STRVG : StoreRXY<"strvg", 0xE32F, storeu<bswap, nonvolatile_store>,
422 //===----------------------------------------------------------------------===//
423 // Load address instructions
424 //===----------------------------------------------------------------------===//
426 // Load BDX-style addresses.
427 let neverHasSideEffects = 1, isAsCheapAsAMove = 1, isReMaterializable = 1,
429 let DispSize = "12" in
430 def LA : InstRX<0x41, (outs GR64:$R1), (ins laaddr12pair:$XBD2),
432 [(set GR64:$R1, laaddr12pair:$XBD2)]>;
433 let DispSize = "20" in
434 def LAY : InstRXY<0xE371, (outs GR64:$R1), (ins laaddr20pair:$XBD2),
436 [(set GR64:$R1, laaddr20pair:$XBD2)]>;
439 // Load a PC-relative address. There's no version of this instruction
440 // with a 16-bit offset, so there's no relaxation.
441 let neverHasSideEffects = 1, isAsCheapAsAMove = 1, isMoveImm = 1,
442 isReMaterializable = 1 in {
443 def LARL : InstRIL<0xC00, (outs GR64:$R1), (ins pcrel32:$I2),
445 [(set GR64:$R1, pcrel32:$I2)]>;
448 //===----------------------------------------------------------------------===//
450 //===----------------------------------------------------------------------===//
453 def LCR : UnaryRR <"lc", 0x13, ineg, GR32, GR32>;
454 def LCGR : UnaryRRE<"lcg", 0xB903, ineg, GR64, GR64>;
455 def LCGFR : UnaryRRE<"lcgf", 0xB913, null_frag, GR64, GR32>;
457 defm : SXU<ineg, LCGFR>;
459 //===----------------------------------------------------------------------===//
461 //===----------------------------------------------------------------------===//
463 let isCodeGenOnly = 1 in
464 defm IC32 : BinaryRXPair<"ic", 0x43, 0xE373, inserti8, GR32, zextloadi8, 1>;
465 defm IC : BinaryRXPair<"ic", 0x43, 0xE373, inserti8, GR64, zextloadi8, 1>;
467 defm : InsertMem<"inserti8", IC32, GR32, zextloadi8, bdxaddr12pair>;
468 defm : InsertMem<"inserti8", IC32Y, GR32, zextloadi8, bdxaddr20pair>;
470 defm : InsertMem<"inserti8", IC, GR64, zextloadi8, bdxaddr12pair>;
471 defm : InsertMem<"inserti8", ICY, GR64, zextloadi8, bdxaddr20pair>;
473 // Insertions of a 16-bit immediate, leaving other bits unaffected.
474 // We don't have or_as_insert equivalents of these operations because
475 // OI is available instead.
476 let isCodeGenOnly = 1 in {
477 def IILL32 : BinaryRI<"iill", 0xA53, insertll, GR32, imm32ll16>;
478 def IILH32 : BinaryRI<"iilh", 0xA52, insertlh, GR32, imm32lh16>;
480 def IILL : BinaryRI<"iill", 0xA53, insertll, GR64, imm64ll16>;
481 def IILH : BinaryRI<"iilh", 0xA52, insertlh, GR64, imm64lh16>;
482 def IIHL : BinaryRI<"iihl", 0xA51, inserthl, GR64, imm64hl16>;
483 def IIHH : BinaryRI<"iihh", 0xA50, inserthh, GR64, imm64hh16>;
485 // ...likewise for 32-bit immediates. For GR32s this is a general
486 // full-width move. (We use IILF rather than something like LLILF
487 // for 32-bit moves because IILF leaves the upper 32 bits of the
489 let isCodeGenOnly = 1, isAsCheapAsAMove = 1, isMoveImm = 1,
490 isReMaterializable = 1 in {
491 def IILF32 : UnaryRIL<"iilf", 0xC09, bitconvert, GR32, uimm32>;
493 def IILF : BinaryRIL<"iilf", 0xC09, insertlf, GR64, imm64lf32>;
494 def IIHF : BinaryRIL<"iihf", 0xC08, inserthf, GR64, imm64hf32>;
496 // An alternative model of inserthf, with the first operand being
497 // a zero-extended value.
498 def : Pat<(or (zext32 GR32:$src), imm64hf32:$imm),
499 (IIHF (INSERT_SUBREG (i64 (IMPLICIT_DEF)), GR32:$src, subreg_32bit),
502 //===----------------------------------------------------------------------===//
504 //===----------------------------------------------------------------------===//
508 // Addition of a register.
509 let isCommutable = 1 in {
510 def AR : BinaryRR <"a", 0x1A, add, GR32, GR32>;
511 def AGR : BinaryRRE<"ag", 0xB908, add, GR64, GR64>;
513 def AGFR : BinaryRRE<"agf", 0xB918, null_frag, GR64, GR32>;
515 // Addition of signed 16-bit immediates.
516 def AHI : BinaryRI<"ahi", 0xA7A, add, GR32, imm32sx16>;
517 def AGHI : BinaryRI<"aghi", 0xA7B, add, GR64, imm64sx16>;
519 // Addition of signed 32-bit immediates.
520 def AFI : BinaryRIL<"afi", 0xC29, add, GR32, simm32>;
521 def AGFI : BinaryRIL<"agfi", 0xC28, add, GR64, imm64sx32>;
523 // Addition of memory.
524 defm AH : BinaryRXPair<"ah", 0x4A, 0xE37A, add, GR32, sextloadi16, 2>;
525 defm A : BinaryRXPair<"a", 0x5A, 0xE35A, add, GR32, load, 4>;
526 def AGF : BinaryRXY<"agf", 0xE318, add, GR64, sextloadi32, 4>;
527 def AG : BinaryRXY<"ag", 0xE308, add, GR64, load, 8>;
529 // Addition to memory.
530 def ASI : BinarySIY<"asi", 0xEB6A, add, imm32sx8>;
531 def AGSI : BinarySIY<"agsi", 0xEB7A, add, imm64sx8>;
533 defm : SXB<add, GR64, AGFR>;
535 // Addition producing a carry.
537 // Addition of a register.
538 let isCommutable = 1 in {
539 def ALR : BinaryRR <"al", 0x1E, addc, GR32, GR32>;
540 def ALGR : BinaryRRE<"alg", 0xB90A, addc, GR64, GR64>;
542 def ALGFR : BinaryRRE<"algf", 0xB91A, null_frag, GR64, GR32>;
544 // Addition of unsigned 32-bit immediates.
545 def ALFI : BinaryRIL<"alfi", 0xC2B, addc, GR32, uimm32>;
546 def ALGFI : BinaryRIL<"algfi", 0xC2A, addc, GR64, imm64zx32>;
548 // Addition of memory.
549 defm AL : BinaryRXPair<"al", 0x5E, 0xE35E, addc, GR32, load, 4>;
550 def ALGF : BinaryRXY<"algf", 0xE31A, addc, GR64, zextloadi32, 4>;
551 def ALG : BinaryRXY<"alg", 0xE30A, addc, GR64, load, 8>;
553 defm : ZXB<addc, GR64, ALGFR>;
555 // Addition producing and using a carry.
556 let Defs = [CC], Uses = [CC] in {
557 // Addition of a register.
558 def ALCR : BinaryRRE<"alc", 0xB998, adde, GR32, GR32>;
559 def ALCGR : BinaryRRE<"alcg", 0xB988, adde, GR64, GR64>;
561 // Addition of memory.
562 def ALC : BinaryRXY<"alc", 0xE398, adde, GR32, load, 4>;
563 def ALCG : BinaryRXY<"alcg", 0xE388, adde, GR64, load, 8>;
566 //===----------------------------------------------------------------------===//
568 //===----------------------------------------------------------------------===//
570 // Plain substraction. Although immediate forms exist, we use the
571 // add-immediate instruction instead.
573 // Subtraction of a register.
574 def SR : BinaryRR <"s", 0x1B, sub, GR32, GR32>;
575 def SGFR : BinaryRRE<"sgf", 0xB919, null_frag, GR64, GR32>;
576 def SGR : BinaryRRE<"sg", 0xB909, sub, GR64, GR64>;
578 // Subtraction of memory.
579 defm SH : BinaryRXPair<"sh", 0x4B, 0xE37B, sub, GR32, sextloadi16, 2>;
580 defm S : BinaryRXPair<"s", 0x5B, 0xE35B, sub, GR32, load, 4>;
581 def SGF : BinaryRXY<"sgf", 0xE319, sub, GR64, sextloadi32, 4>;
582 def SG : BinaryRXY<"sg", 0xE309, sub, GR64, load, 8>;
584 defm : SXB<sub, GR64, SGFR>;
586 // Subtraction producing a carry.
588 // Subtraction of a register.
589 def SLR : BinaryRR <"sl", 0x1F, subc, GR32, GR32>;
590 def SLGFR : BinaryRRE<"slgf", 0xB91B, null_frag, GR64, GR32>;
591 def SLGR : BinaryRRE<"slg", 0xB90B, subc, GR64, GR64>;
593 // Subtraction of unsigned 32-bit immediates. These don't match
594 // subc because we prefer addc for constants.
595 def SLFI : BinaryRIL<"slfi", 0xC25, null_frag, GR32, uimm32>;
596 def SLGFI : BinaryRIL<"slgfi", 0xC24, null_frag, GR64, imm64zx32>;
598 // Subtraction of memory.
599 defm SL : BinaryRXPair<"sl", 0x5F, 0xE35F, subc, GR32, load, 4>;
600 def SLGF : BinaryRXY<"slgf", 0xE31B, subc, GR64, zextloadi32, 4>;
601 def SLG : BinaryRXY<"slg", 0xE30B, subc, GR64, load, 8>;
603 defm : ZXB<subc, GR64, SLGFR>;
605 // Subtraction producing and using a carry.
606 let Defs = [CC], Uses = [CC] in {
607 // Subtraction of a register.
608 def SLBR : BinaryRRE<"slb", 0xB999, sube, GR32, GR32>;
609 def SLGBR : BinaryRRE<"slbg", 0xB989, sube, GR64, GR64>;
611 // Subtraction of memory.
612 def SLB : BinaryRXY<"slb", 0xE399, sube, GR32, load, 4>;
613 def SLBG : BinaryRXY<"slbg", 0xE389, sube, GR64, load, 8>;
616 //===----------------------------------------------------------------------===//
618 //===----------------------------------------------------------------------===//
621 // ANDs of a register.
622 let isCommutable = 1 in {
623 def NR : BinaryRR <"n", 0x14, and, GR32, GR32>;
624 def NGR : BinaryRRE<"ng", 0xB980, and, GR64, GR64>;
627 // ANDs of a 16-bit immediate, leaving other bits unaffected.
628 let isCodeGenOnly = 1 in {
629 def NILL32 : BinaryRI<"nill", 0xA57, and, GR32, imm32ll16c>;
630 def NILH32 : BinaryRI<"nilh", 0xA56, and, GR32, imm32lh16c>;
632 def NILL : BinaryRI<"nill", 0xA57, and, GR64, imm64ll16c>;
633 def NILH : BinaryRI<"nilh", 0xA56, and, GR64, imm64lh16c>;
634 def NIHL : BinaryRI<"nihl", 0xA55, and, GR64, imm64hl16c>;
635 def NIHH : BinaryRI<"nihh", 0xA54, and, GR64, imm64hh16c>;
637 // ANDs of a 32-bit immediate, leaving other bits unaffected.
638 let isCodeGenOnly = 1 in
639 def NILF32 : BinaryRIL<"nilf", 0xC0B, and, GR32, uimm32>;
640 def NILF : BinaryRIL<"nilf", 0xC0B, and, GR64, imm64lf32c>;
641 def NIHF : BinaryRIL<"nihf", 0xC0A, and, GR64, imm64hf32c>;
644 defm N : BinaryRXPair<"n", 0x54, 0xE354, and, GR32, load, 4>;
645 def NG : BinaryRXY<"ng", 0xE380, and, GR64, load, 8>;
648 defm NI : BinarySIPair<"ni", 0x94, 0xEB54, null_frag, uimm8>;
650 defm : RMWIByte<and, bdaddr12pair, NI>;
651 defm : RMWIByte<and, bdaddr20pair, NIY>;
653 //===----------------------------------------------------------------------===//
655 //===----------------------------------------------------------------------===//
658 // ORs of a register.
659 let isCommutable = 1 in {
660 def OR : BinaryRR <"o", 0x16, or, GR32, GR32>;
661 def OGR : BinaryRRE<"og", 0xB981, or, GR64, GR64>;
664 // ORs of a 16-bit immediate, leaving other bits unaffected.
665 let isCodeGenOnly = 1 in {
666 def OILL32 : BinaryRI<"oill", 0xA5B, or, GR32, imm32ll16>;
667 def OILH32 : BinaryRI<"oilh", 0xA5A, or, GR32, imm32lh16>;
669 def OILL : BinaryRI<"oill", 0xA5B, or, GR64, imm64ll16>;
670 def OILH : BinaryRI<"oilh", 0xA5A, or, GR64, imm64lh16>;
671 def OIHL : BinaryRI<"oihl", 0xA59, or, GR64, imm64hl16>;
672 def OIHH : BinaryRI<"oihh", 0xA58, or, GR64, imm64hh16>;
674 // ORs of a 32-bit immediate, leaving other bits unaffected.
675 let isCodeGenOnly = 1 in
676 def OILF32 : BinaryRIL<"oilf", 0xC0D, or, GR32, uimm32>;
677 def OILF : BinaryRIL<"oilf", 0xC0D, or, GR64, imm64lf32>;
678 def OIHF : BinaryRIL<"oihf", 0xC0C, or, GR64, imm64hf32>;
681 defm O : BinaryRXPair<"o", 0x56, 0xE356, or, GR32, load, 4>;
682 def OG : BinaryRXY<"og", 0xE381, or, GR64, load, 8>;
685 defm OI : BinarySIPair<"oi", 0x96, 0xEB56, null_frag, uimm8>;
687 defm : RMWIByte<or, bdaddr12pair, OI>;
688 defm : RMWIByte<or, bdaddr20pair, OIY>;
690 //===----------------------------------------------------------------------===//
692 //===----------------------------------------------------------------------===//
695 // XORs of a register.
696 let isCommutable = 1 in {
697 def XR : BinaryRR <"x", 0x17, xor, GR32, GR32>;
698 def XGR : BinaryRRE<"xg", 0xB982, xor, GR64, GR64>;
701 // XORs of a 32-bit immediate, leaving other bits unaffected.
702 let isCodeGenOnly = 1 in
703 def XILF32 : BinaryRIL<"xilf", 0xC07, xor, GR32, uimm32>;
704 def XILF : BinaryRIL<"xilf", 0xC07, xor, GR64, imm64lf32>;
705 def XIHF : BinaryRIL<"xihf", 0xC06, xor, GR64, imm64hf32>;
708 defm X : BinaryRXPair<"x",0x57, 0xE357, xor, GR32, load, 4>;
709 def XG : BinaryRXY<"xg", 0xE382, xor, GR64, load, 8>;
712 defm XI : BinarySIPair<"xi", 0x97, 0xEB57, null_frag, uimm8>;
714 defm : RMWIByte<xor, bdaddr12pair, XI>;
715 defm : RMWIByte<xor, bdaddr20pair, XIY>;
717 //===----------------------------------------------------------------------===//
719 //===----------------------------------------------------------------------===//
721 // Multiplication of a register.
722 let isCommutable = 1 in {
723 def MSR : BinaryRRE<"ms", 0xB252, mul, GR32, GR32>;
724 def MSGR : BinaryRRE<"msg", 0xB90C, mul, GR64, GR64>;
726 def MSGFR : BinaryRRE<"msgf", 0xB91C, null_frag, GR64, GR32>;
727 defm : SXB<mul, GR64, MSGFR>;
729 // Multiplication of a signed 16-bit immediate.
730 def MHI : BinaryRI<"mhi", 0xA7C, mul, GR32, imm32sx16>;
731 def MGHI : BinaryRI<"mghi", 0xA7D, mul, GR64, imm64sx16>;
733 // Multiplication of a signed 32-bit immediate.
734 def MSFI : BinaryRIL<"msfi", 0xC21, mul, GR32, simm32>;
735 def MSGFI : BinaryRIL<"msgfi", 0xC20, mul, GR64, imm64sx32>;
737 // Multiplication of memory.
738 defm MH : BinaryRXPair<"mh", 0x4C, 0xE37C, mul, GR32, sextloadi16, 2>;
739 defm MS : BinaryRXPair<"ms", 0x71, 0xE351, mul, GR32, load, 4>;
740 def MSGF : BinaryRXY<"msgf", 0xE31C, mul, GR64, sextloadi32, 4>;
741 def MSG : BinaryRXY<"msg", 0xE30C, mul, GR64, load, 8>;
743 // Multiplication of a register, producing two results.
744 def MLGR : BinaryRRE<"mlg", 0xB986, z_umul_lohi64, GR128, GR64>;
746 // Multiplication of memory, producing two results.
747 def MLG : BinaryRXY<"mlg", 0xE386, z_umul_lohi64, GR128, load, 8>;
749 //===----------------------------------------------------------------------===//
750 // Division and remainder
751 //===----------------------------------------------------------------------===//
753 // Division and remainder, from registers.
754 def DSGFR : BinaryRRE<"dsgf", 0xB91D, z_sdivrem32, GR128, GR32>;
755 def DSGR : BinaryRRE<"dsg", 0xB90D, z_sdivrem64, GR128, GR64>;
756 def DLR : BinaryRRE<"dl", 0xB997, z_udivrem32, GR128, GR32>;
757 def DLGR : BinaryRRE<"dlg", 0xB987, z_udivrem64, GR128, GR64>;
759 // Division and remainder, from memory.
760 def DSGF : BinaryRXY<"dsgf", 0xE31D, z_sdivrem32, GR128, load, 4>;
761 def DSG : BinaryRXY<"dsg", 0xE30D, z_sdivrem64, GR128, load, 8>;
762 def DL : BinaryRXY<"dl", 0xE397, z_udivrem32, GR128, load, 4>;
763 def DLG : BinaryRXY<"dlg", 0xE387, z_udivrem64, GR128, load, 8>;
765 //===----------------------------------------------------------------------===//
767 //===----------------------------------------------------------------------===//
770 let neverHasSideEffects = 1 in {
771 def SLL : ShiftRS <"sll", 0x89, shl, GR32, shift12only>;
772 def SLLG : ShiftRSY<"sllg", 0xEB0D, shl, GR64, shift20only>;
775 // Logical shift right.
776 let neverHasSideEffects = 1 in {
777 def SRL : ShiftRS <"srl", 0x88, srl, GR32, shift12only>;
778 def SRLG : ShiftRSY<"srlg", 0xEB0C, srl, GR64, shift20only>;
781 // Arithmetic shift right.
783 def SRA : ShiftRS <"sra", 0x8A, sra, GR32, shift12only>;
784 def SRAG : ShiftRSY<"srag", 0xEB0A, sra, GR64, shift20only>;
788 let neverHasSideEffects = 1 in {
789 def RLL : ShiftRSY<"rll", 0xEB1D, rotl, GR32, shift20only>;
790 def RLLG : ShiftRSY<"rllg", 0xEB1C, rotl, GR64, shift20only>;
793 // Rotate second operand left and inserted selected bits into first operand.
794 // These can act like 32-bit operands provided that the constant start and
795 // end bits (operands 2 and 3) are in the range [32, 64)
797 let isCodeGenOnly = 1 in
798 def RISBG32 : RotateSelectRIEf<"risbg", 0xEC55, GR32, GR32>;
799 def RISBG : RotateSelectRIEf<"risbg", 0xEC55, GR64, GR64>;
802 //===----------------------------------------------------------------------===//
804 //===----------------------------------------------------------------------===//
806 // Signed comparisons.
808 // Comparison with a register.
809 def CR : CompareRR <"c", 0x19, z_cmp, GR32, GR32>;
810 def CGFR : CompareRRE<"cgf", 0xB930, null_frag, GR64, GR32>;
811 def CGR : CompareRRE<"cg", 0xB920, z_cmp, GR64, GR64>;
813 // Comparison with a signed 16-bit immediate.
814 def CHI : CompareRI<"chi", 0xA7E, z_cmp, GR32, imm32sx16>;
815 def CGHI : CompareRI<"cghi", 0xA7F, z_cmp, GR64, imm64sx16>;
817 // Comparison with a signed 32-bit immediate.
818 def CFI : CompareRIL<"cfi", 0xC2D, z_cmp, GR32, simm32>;
819 def CGFI : CompareRIL<"cgfi", 0xC2C, z_cmp, GR64, imm64sx32>;
821 // Comparison with memory.
822 defm CH : CompareRXPair<"ch", 0x49, 0xE379, z_cmp, GR32, sextloadi16, 2>;
823 defm C : CompareRXPair<"c", 0x59, 0xE359, z_cmp, GR32, load, 4>;
824 def CGH : CompareRXY<"cgh", 0xE334, z_cmp, GR64, sextloadi16, 2>;
825 def CGF : CompareRXY<"cgf", 0xE330, z_cmp, GR64, sextloadi32, 4>;
826 def CG : CompareRXY<"cg", 0xE320, z_cmp, GR64, load, 8>;
827 def CHRL : CompareRILPC<"chrl", 0xC65, z_cmp, GR32, aligned_sextloadi16>;
828 def CRL : CompareRILPC<"crl", 0xC6D, z_cmp, GR32, aligned_load>;
829 def CGHRL : CompareRILPC<"cghrl", 0xC64, z_cmp, GR64, aligned_sextloadi16>;
830 def CGFRL : CompareRILPC<"cgfrl", 0xC6C, z_cmp, GR64, aligned_sextloadi32>;
831 def CGRL : CompareRILPC<"cgrl", 0xC68, z_cmp, GR64, aligned_load>;
833 // Comparison between memory and a signed 16-bit immediate.
834 def CHHSI : CompareSIL<"chhsi", 0xE554, z_cmp, sextloadi16, imm32sx16>;
835 def CHSI : CompareSIL<"chsi", 0xE55C, z_cmp, load, imm32sx16>;
836 def CGHSI : CompareSIL<"cghsi", 0xE558, z_cmp, load, imm64sx16>;
838 defm : SXB<z_cmp, GR64, CGFR>;
840 // Unsigned comparisons.
842 // Comparison with a register.
843 def CLR : CompareRR <"cl", 0x15, z_ucmp, GR32, GR32>;
844 def CLGFR : CompareRRE<"clgf", 0xB931, null_frag, GR64, GR32>;
845 def CLGR : CompareRRE<"clg", 0xB921, z_ucmp, GR64, GR64>;
847 // Comparison with a signed 32-bit immediate.
848 def CLFI : CompareRIL<"clfi", 0xC2F, z_ucmp, GR32, uimm32>;
849 def CLGFI : CompareRIL<"clgfi", 0xC2E, z_ucmp, GR64, imm64zx32>;
851 // Comparison with memory.
852 defm CL : CompareRXPair<"cl", 0x55, 0xE355, z_ucmp, GR32, load, 4>;
853 def CLGF : CompareRXY<"clgf", 0xE331, z_ucmp, GR64, zextloadi32, 4>;
854 def CLG : CompareRXY<"clg", 0xE321, z_ucmp, GR64, load, 8>;
855 def CLHRL : CompareRILPC<"clhrl", 0xC67, z_ucmp, GR32,
856 aligned_zextloadi16>;
857 def CLRL : CompareRILPC<"clrl", 0xC6F, z_ucmp, GR32,
859 def CLGHRL : CompareRILPC<"clghrl", 0xC66, z_ucmp, GR64,
860 aligned_zextloadi16>;
861 def CLGFRL : CompareRILPC<"clgfrl", 0xC6E, z_ucmp, GR64,
862 aligned_zextloadi32>;
863 def CLGRL : CompareRILPC<"clgrl", 0xC6A, z_ucmp, GR64,
866 // Comparison between memory and an unsigned 8-bit immediate.
867 defm CLI : CompareSIPair<"cli", 0x95, 0xEB55, z_ucmp, zextloadi8, imm32zx8>;
869 // Comparison between memory and an unsigned 16-bit immediate.
870 def CLHHSI : CompareSIL<"clhhsi", 0xE555, z_ucmp, zextloadi16, imm32zx16>;
871 def CLFHSI : CompareSIL<"clfhsi", 0xE55D, z_ucmp, load, imm32zx16>;
872 def CLGHSI : CompareSIL<"clghsi", 0xE559, z_ucmp, load, imm64zx16>;
874 defm : ZXB<z_ucmp, GR64, CLGFR>;
876 //===----------------------------------------------------------------------===//
878 //===----------------------------------------------------------------------===//
880 def ATOMIC_SWAPW : AtomicLoadWBinaryReg<z_atomic_swapw>;
881 def ATOMIC_SWAP_32 : AtomicLoadBinaryReg32<atomic_swap_32>;
882 def ATOMIC_SWAP_64 : AtomicLoadBinaryReg64<atomic_swap_64>;
884 def ATOMIC_LOADW_AR : AtomicLoadWBinaryReg<z_atomic_loadw_add>;
885 def ATOMIC_LOADW_AFI : AtomicLoadWBinaryImm<z_atomic_loadw_add, simm32>;
886 def ATOMIC_LOAD_AR : AtomicLoadBinaryReg32<atomic_load_add_32>;
887 def ATOMIC_LOAD_AHI : AtomicLoadBinaryImm32<atomic_load_add_32, imm32sx16>;
888 def ATOMIC_LOAD_AFI : AtomicLoadBinaryImm32<atomic_load_add_32, simm32>;
889 def ATOMIC_LOAD_AGR : AtomicLoadBinaryReg64<atomic_load_add_64>;
890 def ATOMIC_LOAD_AGHI : AtomicLoadBinaryImm64<atomic_load_add_64, imm64sx16>;
891 def ATOMIC_LOAD_AGFI : AtomicLoadBinaryImm64<atomic_load_add_64, imm64sx32>;
893 def ATOMIC_LOADW_SR : AtomicLoadWBinaryReg<z_atomic_loadw_sub>;
894 def ATOMIC_LOAD_SR : AtomicLoadBinaryReg32<atomic_load_sub_32>;
895 def ATOMIC_LOAD_SGR : AtomicLoadBinaryReg64<atomic_load_sub_64>;
897 def ATOMIC_LOADW_NR : AtomicLoadWBinaryReg<z_atomic_loadw_and>;
898 def ATOMIC_LOADW_NILH : AtomicLoadWBinaryImm<z_atomic_loadw_and, imm32lh16c>;
899 def ATOMIC_LOAD_NR : AtomicLoadBinaryReg32<atomic_load_and_32>;
900 def ATOMIC_LOAD_NILL32 : AtomicLoadBinaryImm32<atomic_load_and_32, imm32ll16c>;
901 def ATOMIC_LOAD_NILH32 : AtomicLoadBinaryImm32<atomic_load_and_32, imm32lh16c>;
902 def ATOMIC_LOAD_NILF32 : AtomicLoadBinaryImm32<atomic_load_and_32, uimm32>;
903 def ATOMIC_LOAD_NGR : AtomicLoadBinaryReg64<atomic_load_and_64>;
904 def ATOMIC_LOAD_NILL : AtomicLoadBinaryImm64<atomic_load_and_64, imm64ll16c>;
905 def ATOMIC_LOAD_NILH : AtomicLoadBinaryImm64<atomic_load_and_64, imm64lh16c>;
906 def ATOMIC_LOAD_NIHL : AtomicLoadBinaryImm64<atomic_load_and_64, imm64hl16c>;
907 def ATOMIC_LOAD_NIHH : AtomicLoadBinaryImm64<atomic_load_and_64, imm64hh16c>;
908 def ATOMIC_LOAD_NILF : AtomicLoadBinaryImm64<atomic_load_and_64, imm64lf32c>;
909 def ATOMIC_LOAD_NIHF : AtomicLoadBinaryImm64<atomic_load_and_64, imm64hf32c>;
911 def ATOMIC_LOADW_OR : AtomicLoadWBinaryReg<z_atomic_loadw_or>;
912 def ATOMIC_LOADW_OILH : AtomicLoadWBinaryImm<z_atomic_loadw_or, imm32lh16>;
913 def ATOMIC_LOAD_OR : AtomicLoadBinaryReg32<atomic_load_or_32>;
914 def ATOMIC_LOAD_OILL32 : AtomicLoadBinaryImm32<atomic_load_or_32, imm32ll16>;
915 def ATOMIC_LOAD_OILH32 : AtomicLoadBinaryImm32<atomic_load_or_32, imm32lh16>;
916 def ATOMIC_LOAD_OILF32 : AtomicLoadBinaryImm32<atomic_load_or_32, uimm32>;
917 def ATOMIC_LOAD_OGR : AtomicLoadBinaryReg64<atomic_load_or_64>;
918 def ATOMIC_LOAD_OILL : AtomicLoadBinaryImm64<atomic_load_or_64, imm64ll16>;
919 def ATOMIC_LOAD_OILH : AtomicLoadBinaryImm64<atomic_load_or_64, imm64lh16>;
920 def ATOMIC_LOAD_OIHL : AtomicLoadBinaryImm64<atomic_load_or_64, imm64hl16>;
921 def ATOMIC_LOAD_OIHH : AtomicLoadBinaryImm64<atomic_load_or_64, imm64hh16>;
922 def ATOMIC_LOAD_OILF : AtomicLoadBinaryImm64<atomic_load_or_64, imm64lf32>;
923 def ATOMIC_LOAD_OIHF : AtomicLoadBinaryImm64<atomic_load_or_64, imm64hf32>;
925 def ATOMIC_LOADW_XR : AtomicLoadWBinaryReg<z_atomic_loadw_xor>;
926 def ATOMIC_LOADW_XILF : AtomicLoadWBinaryImm<z_atomic_loadw_xor, uimm32>;
927 def ATOMIC_LOAD_XR : AtomicLoadBinaryReg32<atomic_load_xor_32>;
928 def ATOMIC_LOAD_XILF32 : AtomicLoadBinaryImm32<atomic_load_xor_32, uimm32>;
929 def ATOMIC_LOAD_XGR : AtomicLoadBinaryReg64<atomic_load_xor_64>;
930 def ATOMIC_LOAD_XILF : AtomicLoadBinaryImm64<atomic_load_xor_64, imm64lf32>;
931 def ATOMIC_LOAD_XIHF : AtomicLoadBinaryImm64<atomic_load_xor_64, imm64hf32>;
933 def ATOMIC_LOADW_NRi : AtomicLoadWBinaryReg<z_atomic_loadw_nand>;
934 def ATOMIC_LOADW_NILHi : AtomicLoadWBinaryImm<z_atomic_loadw_nand,
936 def ATOMIC_LOAD_NRi : AtomicLoadBinaryReg32<atomic_load_nand_32>;
937 def ATOMIC_LOAD_NILL32i : AtomicLoadBinaryImm32<atomic_load_nand_32,
939 def ATOMIC_LOAD_NILH32i : AtomicLoadBinaryImm32<atomic_load_nand_32,
941 def ATOMIC_LOAD_NILF32i : AtomicLoadBinaryImm32<atomic_load_nand_32, uimm32>;
942 def ATOMIC_LOAD_NGRi : AtomicLoadBinaryReg64<atomic_load_nand_64>;
943 def ATOMIC_LOAD_NILLi : AtomicLoadBinaryImm64<atomic_load_nand_64,
945 def ATOMIC_LOAD_NILHi : AtomicLoadBinaryImm64<atomic_load_nand_64,
947 def ATOMIC_LOAD_NIHLi : AtomicLoadBinaryImm64<atomic_load_nand_64,
949 def ATOMIC_LOAD_NIHHi : AtomicLoadBinaryImm64<atomic_load_nand_64,
951 def ATOMIC_LOAD_NILFi : AtomicLoadBinaryImm64<atomic_load_nand_64,
953 def ATOMIC_LOAD_NIHFi : AtomicLoadBinaryImm64<atomic_load_nand_64,
956 def ATOMIC_LOADW_MIN : AtomicLoadWBinaryReg<z_atomic_loadw_min>;
957 def ATOMIC_LOAD_MIN_32 : AtomicLoadBinaryReg32<atomic_load_min_32>;
958 def ATOMIC_LOAD_MIN_64 : AtomicLoadBinaryReg64<atomic_load_min_64>;
960 def ATOMIC_LOADW_MAX : AtomicLoadWBinaryReg<z_atomic_loadw_max>;
961 def ATOMIC_LOAD_MAX_32 : AtomicLoadBinaryReg32<atomic_load_max_32>;
962 def ATOMIC_LOAD_MAX_64 : AtomicLoadBinaryReg64<atomic_load_max_64>;
964 def ATOMIC_LOADW_UMIN : AtomicLoadWBinaryReg<z_atomic_loadw_umin>;
965 def ATOMIC_LOAD_UMIN_32 : AtomicLoadBinaryReg32<atomic_load_umin_32>;
966 def ATOMIC_LOAD_UMIN_64 : AtomicLoadBinaryReg64<atomic_load_umin_64>;
968 def ATOMIC_LOADW_UMAX : AtomicLoadWBinaryReg<z_atomic_loadw_umax>;
969 def ATOMIC_LOAD_UMAX_32 : AtomicLoadBinaryReg32<atomic_load_umax_32>;
970 def ATOMIC_LOAD_UMAX_64 : AtomicLoadBinaryReg64<atomic_load_umax_64>;
973 : Pseudo<(outs GR32:$dst), (ins bdaddr20only:$addr, GR32:$cmp, GR32:$swap,
974 ADDR32:$bitshift, ADDR32:$negbitshift,
977 (z_atomic_cmp_swapw bdaddr20only:$addr, GR32:$cmp, GR32:$swap,
978 ADDR32:$bitshift, ADDR32:$negbitshift,
979 uimm32:$bitsize))]> {
983 let usesCustomInserter = 1;
987 defm CS : CmpSwapRSPair<"cs", 0xBA, 0xEB14, atomic_cmp_swap_32, GR32>;
988 def CSG : CmpSwapRSY<"csg", 0xEB30, atomic_cmp_swap_64, GR64>;
991 //===----------------------------------------------------------------------===//
992 // Miscellaneous Instructions.
993 //===----------------------------------------------------------------------===//
995 // Read a 32-bit access register into a GR32. As with all GR32 operations,
996 // the upper 32 bits of the enclosing GR64 remain unchanged, which is useful
997 // when a 64-bit address is stored in a pair of access registers.
998 def EAR : InstRRE<0xB24F, (outs GR32:$R1), (ins access_reg:$R2),
1000 [(set GR32:$R1, (z_extract_access access_reg:$R2))]>;
1002 // Find leftmost one, AKA count leading zeros. The instruction actually
1003 // returns a pair of GR64s, the first giving the number of leading zeros
1004 // and the second giving a copy of the source with the leftmost one bit
1005 // cleared. We only use the first result here.
1006 let Defs = [CC] in {
1007 def FLOGR : UnaryRRE<"flog", 0xB983, null_frag, GR128, GR64>;
1009 def : Pat<(ctlz GR64:$src),
1010 (EXTRACT_SUBREG (FLOGR GR64:$src), subreg_high)>;
1012 // Use subregs to populate the "don't care" bits in a 32-bit to 64-bit anyext.
1013 def : Pat<(i64 (anyext GR32:$src)),
1014 (INSERT_SUBREG (i64 (IMPLICIT_DEF)), GR32:$src, subreg_32bit)>;
1016 // There are no 32-bit equivalents of LLILL and LLILH, so use a full
1017 // 64-bit move followed by a subreg. This preserves the invariant that
1018 // all GR32 operations only modify the low 32 bits.
1019 def : Pat<(i32 imm32ll16:$src),
1020 (EXTRACT_SUBREG (LLILL (LL16 imm:$src)), subreg_32bit)>;
1021 def : Pat<(i32 imm32lh16:$src),
1022 (EXTRACT_SUBREG (LLILH (LH16 imm:$src)), subreg_32bit)>;
1024 // Extend GR32s and GR64s to GR128s.
1025 let usesCustomInserter = 1 in {
1026 def AEXT128_64 : Pseudo<(outs GR128:$dst), (ins GR64:$src), []>;
1027 def ZEXT128_32 : Pseudo<(outs GR128:$dst), (ins GR32:$src), []>;
1028 def ZEXT128_64 : Pseudo<(outs GR128:$dst), (ins GR64:$src), []>;
1031 //===----------------------------------------------------------------------===//
1033 //===----------------------------------------------------------------------===//
1035 // Use AL* for GR64 additions of unsigned 32-bit values.
1036 defm : ZXB<add, GR64, ALGFR>;
1037 def : Pat<(add GR64:$src1, imm64zx32:$src2),
1038 (ALGFI GR64:$src1, imm64zx32:$src2)>;
1039 def : Pat<(add GR64:$src1, (zextloadi32 bdxaddr20only:$addr)),
1040 (ALGF GR64:$src1, bdxaddr20only:$addr)>;
1042 // Use SL* for GR64 subtractions of unsigned 32-bit values.
1043 defm : ZXB<sub, GR64, SLGFR>;
1044 def : Pat<(add GR64:$src1, imm64zx32n:$src2),
1045 (SLGFI GR64:$src1, imm64zx32n:$src2)>;
1046 def : Pat<(sub GR64:$src1, (zextloadi32 bdxaddr20only:$addr)),
1047 (SLGF GR64:$src1, bdxaddr20only:$addr)>;