lib/Target/SystemZ/SystemZInstrInfo.td

   1 //===- SystemZInstrInfo.td - SystemZ Instruction defs ---------*- tblgen-*-===//
   2 //
   3 //                     The LLVM Compiler Infrastructure
   4 //
   5 // This file is distributed under the University of Illinois Open Source
   6 // License. See LICENSE.TXT for details.
   7 //
   8 //===----------------------------------------------------------------------===//
   9 //
  10 // This file describes the SystemZ instructions in TableGen format.
  11 //
  12 //===----------------------------------------------------------------------===//
  13
  14 //===----------------------------------------------------------------------===//
  15 // SystemZ Instruction Predicate Definitions.
  16 def IsZ10 : Predicate<"Subtarget.isZ10()">;
  17
  18 include "SystemZInstrFormats.td"
  19
  20 //===----------------------------------------------------------------------===//
  21 // Type Constraints.
  22 //===----------------------------------------------------------------------===//
  23 class SDTCisI8<int OpNum> : SDTCisVT<OpNum, i8>;
  24 class SDTCisI16<int OpNum> : SDTCisVT<OpNum, i16>;
  25 class SDTCisI32<int OpNum> : SDTCisVT<OpNum, i32>;
  26 class SDTCisI64<int OpNum> : SDTCisVT<OpNum, i64>;
  27
  28 //===----------------------------------------------------------------------===//
  29 // Type Profiles.
  30 //===----------------------------------------------------------------------===//
  31 def SDT_SystemZCall         : SDTypeProfile<0, -1, [SDTCisPtrTy<0>]>;
  32 def SDT_SystemZCallSeqStart : SDCallSeqStart<[SDTCisI64<0>]>;
  33 def SDT_SystemZCallSeqEnd   : SDCallSeqEnd<[SDTCisI64<0>, SDTCisI64<1>]>;
  34 def SDT_CmpTest             : SDTypeProfile<0, 2, [SDTCisSameAs<0, 1>]>;
  35 def SDT_BrCond              : SDTypeProfile<0, 2,
  36                                            [SDTCisVT<0, OtherVT>,
  37                                             SDTCisI8<1>]>;
  38 def SDT_SelectCC            : SDTypeProfile<1, 3,
  39                                            [SDTCisSameAs<0, 1>, SDTCisSameAs<1, 2>,
  40                                             SDTCisI8<3>]>;
  41 def SDT_Address             : SDTypeProfile<1, 1,
  42                                             [SDTCisSameAs<0, 1>, SDTCisPtrTy<0>]>;
  43
  44 //===----------------------------------------------------------------------===//
  45 // SystemZ Specific Node Definitions.
  46 //===----------------------------------------------------------------------===//
  47 def SystemZretflag : SDNode<"SystemZISD::RET_FLAG", SDTNone,
  48                      [SDNPHasChain, SDNPOptInFlag]>;
  49 def SystemZcall    : SDNode<"SystemZISD::CALL", SDT_SystemZCall,
  50                      [SDNPHasChain, SDNPOutFlag, SDNPOptInFlag]>;
  51 def SystemZcallseq_start :
  52                  SDNode<"ISD::CALLSEQ_START", SDT_SystemZCallSeqStart,
  53                         [SDNPHasChain, SDNPOutFlag]>;
  54 def SystemZcallseq_end :
  55                  SDNode<"ISD::CALLSEQ_END",   SDT_SystemZCallSeqEnd,
  56                         [SDNPHasChain, SDNPOptInFlag, SDNPOutFlag]>;
  57 def SystemZcmp     : SDNode<"SystemZISD::CMP", SDT_CmpTest, [SDNPOutFlag]>;
  58 def SystemZucmp    : SDNode<"SystemZISD::UCMP", SDT_CmpTest, [SDNPOutFlag]>;
  59 def SystemZbrcond  : SDNode<"SystemZISD::BRCOND", SDT_BrCond,
  60                             [SDNPHasChain, SDNPInFlag]>;
  61 def SystemZselect  : SDNode<"SystemZISD::SELECT", SDT_SelectCC, [SDNPInFlag]>;
  62 def SystemZpcrelwrapper : SDNode<"SystemZISD::PCRelativeWrapper", SDT_Address, []>;
  63
  64
  65 include "SystemZOperands.td"
  66
  67 //===----------------------------------------------------------------------===//
  68 // Instruction list..
  69
  70 def ADJCALLSTACKDOWN : Pseudo<(outs), (ins i64imm:$amt),
  71                               "#ADJCALLSTACKDOWN",
  72                               [(SystemZcallseq_start timm:$amt)]>;
  73 def ADJCALLSTACKUP   : Pseudo<(outs), (ins i64imm:$amt1, i64imm:$amt2),
  74                               "#ADJCALLSTACKUP",
  75                               [(SystemZcallseq_end timm:$amt1, timm:$amt2)]>;
  76
  77 let usesCustomDAGSchedInserter = 1 in {
  78   def Select32 : Pseudo<(outs GR32:$dst), (ins GR32:$src1, GR32:$src2, i8imm:$cc),
  79                         "# Select32 PSEUDO",
  80                         [(set GR32:$dst,
  81                               (SystemZselect GR32:$src1, GR32:$src2, imm:$cc))]>;
  82   def Select64 : Pseudo<(outs GR64:$dst), (ins GR64:$src1, GR64:$src2, i8imm:$cc),
  83                         "# Select64 PSEUDO",
  84                         [(set GR64:$dst,
  85                               (SystemZselect GR64:$src1, GR64:$src2, imm:$cc))]>;
  86 }
  87
  88
  89 //===----------------------------------------------------------------------===//
  90 //  Control Flow Instructions...
  91 //
  92
  93 // FIXME: Provide proper encoding!
  94 let isReturn = 1, isTerminator = 1, isBarrier = 1, hasCtrlDep = 1 in {
  95   def RET : Pseudo<(outs), (ins), "br\t%r14", [(SystemZretflag)]>;
  96 }
  97
  98 let isBranch = 1, isTerminator = 1 in {
  99   let isBarrier = 1 in {
 100     def JMP  : Pseudo<(outs), (ins brtarget:$dst), "j\t{$dst}", [(br bb:$dst)]>;
 101
 102     let isIndirectBranch = 1 in
 103       def JMPr   : Pseudo<(outs), (ins GR64:$dst), "br\t{$dst}", [(brind GR64:$dst)]>;
 104   }
 105
 106   let Uses = [PSW] in {
 107     def JO  : Pseudo<(outs), (ins brtarget:$dst),
 108                      "jo\t$dst",
 109                      [(SystemZbrcond bb:$dst, SYSTEMZ_COND_O)]>;
 110     def JH  : Pseudo<(outs), (ins brtarget:$dst),
 111                      "jh\t$dst",
 112                      [(SystemZbrcond bb:$dst, SYSTEMZ_COND_H)]>;
 113     def JNLE: Pseudo<(outs), (ins brtarget:$dst),
 114                      "jnle\t$dst",
 115                      [(SystemZbrcond bb:$dst, SYSTEMZ_COND_NLE)]>;
 116     def JL  : Pseudo<(outs), (ins brtarget:$dst),
 117                      "jl\t$dst",
 118                      [(SystemZbrcond bb:$dst, SYSTEMZ_COND_L)]>;
 119     def JNHE: Pseudo<(outs), (ins brtarget:$dst),
 120                      "jnhe\t$dst",
 121                      [(SystemZbrcond bb:$dst, SYSTEMZ_COND_NHE)]>;
 122     def JLH : Pseudo<(outs), (ins brtarget:$dst),
 123                      "jlh\t$dst",
 124                      [(SystemZbrcond bb:$dst, SYSTEMZ_COND_LH)]>;
 125     def JNE : Pseudo<(outs), (ins brtarget:$dst),
 126                      "jne\t$dst",
 127                      [(SystemZbrcond bb:$dst, SYSTEMZ_COND_NE)]>;
 128     def JE  : Pseudo<(outs), (ins brtarget:$dst),
 129                      "je\t$dst",
 130                      [(SystemZbrcond bb:$dst, SYSTEMZ_COND_E)]>;
 131     def JNLH: Pseudo<(outs), (ins brtarget:$dst),
 132                      "jnlh\t$dst",
 133                      [(SystemZbrcond bb:$dst, SYSTEMZ_COND_NLH)]>;
 134     def JHE : Pseudo<(outs), (ins brtarget:$dst),
 135                      "jhe\t$dst",
 136                      [(SystemZbrcond bb:$dst, SYSTEMZ_COND_HE)]>;
 137     def JNL : Pseudo<(outs), (ins brtarget:$dst),
 138                      "jnl\t$dst",
 139                      [(SystemZbrcond bb:$dst, SYSTEMZ_COND_NL)]>;
 140     def JLE : Pseudo<(outs), (ins brtarget:$dst),
 141                      "jle\t$dst",
 142                      [(SystemZbrcond bb:$dst, SYSTEMZ_COND_LE)]>;
 143     def JNH : Pseudo<(outs), (ins brtarget:$dst),
 144                      "jnh\t$dst",
 145                      [(SystemZbrcond bb:$dst, SYSTEMZ_COND_NH)]>;
 146     def JNO : Pseudo<(outs), (ins brtarget:$dst),
 147                      "jno\t$dst",
 148                      [(SystemZbrcond bb:$dst, SYSTEMZ_COND_NO)]>;
 149   } // Uses = [PSW]
 150 } // isBranch = 1
 151
 152 //===----------------------------------------------------------------------===//
 153 //  Call Instructions...
 154 //
 155
 156 let isCall = 1 in
 157   // All calls clobber the non-callee saved registers. Uses for argument
 158   // registers are added manually.
 159   let Defs = [R0D, R1D, R2D, R3D, R4D, R5D, R14D,
 160               F0L, F1L, F2L, F3L, F4L, F5L, F6L, F7L] in {
 161     def CALLi     : Pseudo<(outs), (ins imm_pcrel:$dst, variable_ops),
 162                            "brasl\t%r14, $dst", [(SystemZcall imm:$dst)]>;
 163     def CALLr     : Pseudo<(outs), (ins ADDR64:$dst, variable_ops),
 164                            "basr\t%r14, $dst", [(SystemZcall ADDR64:$dst)]>;
 165   }
 166
 167 //===----------------------------------------------------------------------===//
 168 //  Miscellaneous Instructions.
 169 //
 170
 171 let isReMaterializable = 1 in
 172 // FIXME: Provide imm12 variant
 173 // FIXME: Address should be halfword aligned...
 174 def LA64r  : Pseudo<(outs GR64:$dst), (ins laaddr:$src),
 175                     "lay\t{$dst, $src}",
 176                     [(set GR64:$dst, laaddr:$src)]>;
 177 def LA64rm : Pseudo<(outs GR64:$dst), (ins i64imm:$src),
 178                     "larl\t{$dst, $src}",
 179                     [(set GR64:$dst,
 180                           (SystemZpcrelwrapper tglobaladdr:$src))]>;
 181
 182 let neverHasSideEffects = 1 in
 183 def NOP : Pseudo<(outs), (ins), "# no-op", []>;
 184
 185 //===----------------------------------------------------------------------===//
 186 // Move Instructions
 187
 188 // FIXME: Provide proper encoding!
 189 let neverHasSideEffects = 1 in {
 190 def MOV32rr : Pseudo<(outs GR32:$dst), (ins GR32:$src),
 191                      "lr\t{$dst, $src}",
 192                      []>;
 193 def MOV64rr : Pseudo<(outs GR64:$dst), (ins GR64:$src),
 194                      "lgr\t{$dst, $src}",
 195                      []>;
 196 def MOV128rr : Pseudo<(outs GR128:$dst), (ins GR128:$src),
 197                      "# MOV128 PSEUDO!\n"
 198                      "\tlgr\t${dst:subreg_odd}, ${src:subreg_odd}\n"
 199                      "\tlgr\t${dst:subreg_even}, ${src:subreg_even}",
 200                      []>;
 201 def MOV64rrP : Pseudo<(outs GR64P:$dst), (ins GR64P:$src),
 202                      "# MOV64P PSEUDO!\n"
 203                      "\tlr\t${dst:subreg_odd}, ${src:subreg_odd}\n"
 204                      "\tlr\t${dst:subreg_even}, ${src:subreg_even}",
 205                      []>;
 206 }
 207
 208 def MOVSX64rr32 : Pseudo<(outs GR64:$dst), (ins GR32:$src),
 209                          "lgfr\t{$dst, $src}",
 210                          [(set GR64:$dst, (sext GR32:$src))]>;
 211 def MOVZX64rr32 : Pseudo<(outs GR64:$dst), (ins GR32:$src),
 212                          "llgfr\t{$dst, $src}",
 213                          [(set GR64:$dst, (zext GR32:$src))]>;
 214
 215 // FIXME: Provide proper encoding!
 216 let isReMaterializable = 1, isAsCheapAsAMove = 1 in {
 217 def MOV32ri16 : Pseudo<(outs GR32:$dst), (ins s16imm:$src),
 218                        "lhi\t{$dst, $src}",
 219                        [(set GR32:$dst, immSExt16:$src)]>;
 220 def MOV64ri16 : Pseudo<(outs GR64:$dst), (ins s16imm64:$src),
 221                        "lghi\t{$dst, $src}",
 222                        [(set GR64:$dst, immSExt16:$src)]>;
 223
 224 def MOV64rill16 : Pseudo<(outs GR64:$dst), (ins i64imm:$src),
 225                          "llill\t{$dst, $src}",
 226                          [(set GR64:$dst, i64ll16:$src)]>;
 227 def MOV64rilh16 : Pseudo<(outs GR64:$dst), (ins i64imm:$src),
 228                          "llilh\t{$dst, $src}",
 229                          [(set GR64:$dst, i64lh16:$src)]>;
 230 def MOV64rihl16 : Pseudo<(outs GR64:$dst), (ins i64imm:$src),
 231                          "llihl\t{$dst, $src}",
 232                          [(set GR64:$dst, i64hl16:$src)]>;
 233 def MOV64rihh16 : Pseudo<(outs GR64:$dst), (ins i64imm:$src),
 234                          "llihh\t{$dst, $src}",
 235                          [(set GR64:$dst, i64hh16:$src)]>;
 236
 237 def MOV64ri32 : Pseudo<(outs GR64:$dst), (ins s32imm64:$src),
 238                        "lgfi\t{$dst, $src}",
 239                        [(set GR64:$dst, immSExt32:$src)]>;
 240 def MOV64rilo32 : Pseudo<(outs GR64:$dst), (ins i64imm:$src),
 241                          "llilf\t{$dst, $src}",
 242                          [(set GR64:$dst, i64lo32:$src)]>;
 243 def MOV64rihi32 : Pseudo<(outs GR64:$dst), (ins i64imm:$src),
 244                          "llihf\t{$dst, $src}",
 245                          [(set GR64:$dst, i64hi32:$src)]>;
 246 }
 247
 248 let canFoldAsLoad = 1, isReMaterializable = 1, mayHaveSideEffects = 1 in {
 249 def MOV32rm  : Pseudo<(outs GR32:$dst), (ins rriaddr12:$src),
 250                       "l\t{$dst, $src}",
 251                       [(set GR32:$dst, (load rriaddr12:$src))]>;
 252 def MOV32rmy : Pseudo<(outs GR32:$dst), (ins rriaddr:$src),
 253                       "ly\t{$dst, $src}",
 254                       [(set GR32:$dst, (load rriaddr:$src))]>;
 255 def MOV64rm  : Pseudo<(outs GR64:$dst), (ins rriaddr:$src),
 256                       "lg\t{$dst, $src}",
 257                       [(set GR64:$dst, (load rriaddr:$src))]>;
 258
 259 }
 260
 261 def MOV32mr  : Pseudo<(outs), (ins rriaddr12:$dst, GR32:$src),
 262                       "st\t{$src, $dst}",
 263                       [(store GR32:$src, rriaddr12:$dst)]>;
 264 def MOV32mry : Pseudo<(outs), (ins rriaddr:$dst, GR32:$src),
 265                       "sty\t{$src, $dst}",
 266                       [(store GR32:$src, rriaddr:$dst)]>;
 267 def MOV64mr  : Pseudo<(outs), (ins rriaddr:$dst, GR64:$src),
 268                       "stg\t{$src, $dst}",
 269                       [(store GR64:$src, rriaddr:$dst)]>;
 270
 271 def MOV8mi    : Pseudo<(outs), (ins riaddr12:$dst, i32i8imm:$src),
 272                        "mvi\t{$dst, $src}",
 273                        [(truncstorei8 (i32 i32immSExt8:$src), riaddr12:$dst)]>;
 274 def MOV8miy   : Pseudo<(outs), (ins riaddr:$dst, i32i8imm:$src),
 275                        "mviy\t{$dst, $src}",
 276                        [(truncstorei8 (i32 i32immSExt8:$src), riaddr:$dst)]>;
 277
 278 def MOV16mi   : Pseudo<(outs), (ins riaddr12:$dst, s16imm:$src),
 279                        "mvhhi\t{$dst, $src}",
 280                        [(truncstorei16 (i32 i32immSExt16:$src), riaddr12:$dst)]>,
 281                        Requires<[IsZ10]>;
 282 def MOV32mi16 : Pseudo<(outs), (ins riaddr12:$dst, s32imm:$src),
 283                        "mvhi\t{$dst, $src}",
 284                        [(store (i32 immSExt16:$src), riaddr12:$dst)]>,
 285                        Requires<[IsZ10]>;
 286 def MOV64mi16 : Pseudo<(outs), (ins riaddr12:$dst, s32imm64:$src),
 287                        "mvghi\t{$dst, $src}",
 288                        [(store (i64 immSExt16:$src), riaddr12:$dst)]>,
 289                        Requires<[IsZ10]>;
 290
 291 // sexts
 292 def MOVSX32rr8  : Pseudo<(outs GR32:$dst), (ins GR32:$src),
 293                          "lbr\t{$dst, $src}",
 294                          [(set GR32:$dst, (sext_inreg GR32:$src, i8))]>;
 295 def MOVSX64rr8  : Pseudo<(outs GR64:$dst), (ins GR64:$src),
 296                          "lgbr\t{$dst, $src}",
 297                          [(set GR64:$dst, (sext_inreg GR64:$src, i8))]>;
 298 def MOVSX32rr16 : Pseudo<(outs GR32:$dst), (ins GR32:$src),
 299                          "lhr\t{$dst, $src}",
 300                          [(set GR32:$dst, (sext_inreg GR32:$src, i16))]>;
 301 def MOVSX64rr16 : Pseudo<(outs GR64:$dst), (ins GR64:$src),
 302                          "lghr\t{$dst, $src}",
 303                          [(set GR64:$dst, (sext_inreg GR64:$src, i16))]>;
 304
 305 // extloads
 306 def MOVSX32rm8   : Pseudo<(outs GR32:$dst), (ins rriaddr:$src),
 307                           "lb\t{$dst, $src}",
 308                           [(set GR32:$dst, (sextloadi32i8 rriaddr:$src))]>;
 309 def MOVSX32rm16  : Pseudo<(outs GR32:$dst), (ins rriaddr12:$src),
 310                           "lh\t{$dst, $src}",
 311                           [(set GR32:$dst, (sextloadi32i16 rriaddr12:$src))]>;
 312 def MOVSX32rm16y : Pseudo<(outs GR32:$dst), (ins rriaddr:$src),
 313                          "lhy\t{$dst, $src}",
 314                          [(set GR32:$dst, (sextloadi32i16 rriaddr:$src))]>;
 315 def MOVSX64rm8   : Pseudo<(outs GR64:$dst), (ins rriaddr:$src),
 316                           "lgb\t{$dst, $src}",
 317                           [(set GR64:$dst, (sextloadi64i8 rriaddr:$src))]>;
 318 def MOVSX64rm16  : Pseudo<(outs GR64:$dst), (ins rriaddr:$src),
 319                           "lgh\t{$dst, $src}",
 320                           [(set GR64:$dst, (sextloadi64i16 rriaddr:$src))]>;
 321 def MOVSX64rm32  : Pseudo<(outs GR64:$dst), (ins rriaddr:$src),
 322                           "lgf\t{$dst, $src}",
 323                           [(set GR64:$dst, (sextloadi64i32 rriaddr:$src))]>;
 324
 325 def MOVZX32rm8  : Pseudo<(outs GR32:$dst), (ins rriaddr:$src),
 326                          "llc\t{$dst, $src}",
 327                          [(set GR32:$dst, (zextloadi32i8 rriaddr:$src))]>;
 328 def MOVZX32rm16 : Pseudo<(outs GR32:$dst), (ins rriaddr:$src),
 329                          "llh\t{$dst, $src}",
 330                          [(set GR32:$dst, (zextloadi32i16 rriaddr:$src))]>;
 331 def MOVZX64rm8  : Pseudo<(outs GR64:$dst), (ins rriaddr:$src),
 332                          "llgc\t{$dst, $src}",
 333                          [(set GR64:$dst, (zextloadi64i8 rriaddr:$src))]>;
 334 def MOVZX64rm16 : Pseudo<(outs GR64:$dst), (ins rriaddr:$src),
 335                          "llgh\t{$dst, $src}",
 336                          [(set GR64:$dst, (zextloadi64i16 rriaddr:$src))]>;
 337 def MOVZX64rm32 : Pseudo<(outs GR64:$dst), (ins rriaddr:$src),
 338                          "llgf\t{$dst, $src}",
 339                          [(set GR64:$dst, (zextloadi64i32 rriaddr:$src))]>;
 340
 341 // truncstores
 342 def MOV32m8r   : Pseudo<(outs), (ins rriaddr12:$dst, GR32:$src),
 343                         "stc\t{$src, $dst}",
 344                         [(truncstorei8 GR32:$src, rriaddr12:$dst)]>;
 345
 346 def MOV32m8ry  : Pseudo<(outs), (ins rriaddr:$dst, GR32:$src),
 347                         "stcy\t{$src, $dst}",
 348                         [(truncstorei8 GR32:$src, rriaddr:$dst)]>;
 349
 350 def MOV32m16r  : Pseudo<(outs), (ins rriaddr12:$dst, GR32:$src),
 351                         "sth\t{$src, $dst}",
 352                         [(truncstorei16 GR32:$src, rriaddr12:$dst)]>;
 353
 354 def MOV32m16ry : Pseudo<(outs), (ins rriaddr:$dst, GR32:$src),
 355                         "sthy\t{$src, $dst}",
 356                         [(truncstorei16 GR32:$src, rriaddr:$dst)]>;
 357
 358 def MOV64m8r   : Pseudo<(outs), (ins rriaddr12:$dst, GR64:$src),
 359                         "stc\t{$src, $dst}",
 360                         [(truncstorei8 GR64:$src, rriaddr12:$dst)]>;
 361
 362 def MOV64m8ry  : Pseudo<(outs), (ins rriaddr:$dst, GR64:$src),
 363                         "stcy\t{$src, $dst}",
 364                         [(truncstorei8 GR64:$src, rriaddr:$dst)]>;
 365
 366 def MOV64m16r  : Pseudo<(outs), (ins rriaddr12:$dst, GR64:$src),
 367                         "sth\t{$src, $dst}",
 368                         [(truncstorei16 GR64:$src, rriaddr12:$dst)]>;
 369
 370 def MOV64m16ry : Pseudo<(outs), (ins rriaddr:$dst, GR64:$src),
 371                         "sthy\t{$src, $dst}",
 372                         [(truncstorei16 GR64:$src, rriaddr:$dst)]>;
 373
 374 def MOV64m32r  : Pseudo<(outs), (ins rriaddr12:$dst, GR64:$src),
 375                         "st\t{$src, $dst}",
 376                         [(truncstorei32 GR64:$src, rriaddr12:$dst)]>;
 377
 378 def MOV64m32ry : Pseudo<(outs), (ins rriaddr:$dst, GR64:$src),
 379                         "sty\t{$src, $dst}",
 380                         [(truncstorei32 GR64:$src, rriaddr:$dst)]>;
 381
 382 // multiple regs moves
 383 // FIXME: should we use multiple arg nodes?
 384 def MOV32mrm  : Pseudo<(outs), (ins riaddr:$dst, GR32:$from, GR32:$to),
 385                        "stmy\t{$from, $to, $dst}",
 386                        []>;
 387 def MOV64mrm  : Pseudo<(outs), (ins riaddr:$dst, GR64:$from, GR64:$to),
 388                        "stmg\t{$from, $to, $dst}",
 389                        []>;
 390 def MOV32rmm  : Pseudo<(outs GR32:$from, GR32:$to), (ins riaddr:$dst),
 391                        "lmy\t{$from, $to, $dst}",
 392                        []>;
 393 def MOV64rmm  : Pseudo<(outs GR64:$from, GR64:$to), (ins riaddr:$dst),
 394                        "lmg\t{$from, $to, $dst}",
 395                        []>;
 396
 397 let isReMaterializable = 1, isAsCheapAsAMove = 1, isTwoAddress = 1 in {
 398 def MOV64Pr0_even : Pseudo<(outs GR64P:$dst), (ins GR64P:$src),
 399                            "lhi\t${dst:subreg_even}, 0",
 400                            []>;
 401 def MOV128r0_even : Pseudo<(outs GR128:$dst), (ins GR128:$src),
 402                            "lghi\t${dst:subreg_even}, 0",
 403                            []>;
 404 }
 405
 406 //===----------------------------------------------------------------------===//
 407 // Arithmetic Instructions
 408
 409 let Defs = [PSW] in {
 410 def NEG32rr : Pseudo<(outs GR32:$dst), (ins GR32:$src),
 411                      "lcr\t{$dst, $src}",
 412                      [(set GR32:$dst, (ineg GR32:$src)),
 413                       (implicit PSW)]>;
 414 def NEG64rr : Pseudo<(outs GR64:$dst), (ins GR64:$src),
 415                      "lcgr\t{$dst, $src}",
 416                      [(set GR64:$dst, (ineg GR64:$src)),
 417                       (implicit PSW)]>;
 418 def NEG64rr32 : Pseudo<(outs GR64:$dst), (ins GR32:$src),
 419                        "lcgfr\t{$dst, $src}",
 420                        [(set GR64:$dst, (ineg (sext GR32:$src))),
 421                         (implicit PSW)]>;
 422 }
 423
 424 let isTwoAddress = 1 in {
 425
 426 let Defs = [PSW] in {
 427
 428 let isCommutable = 1 in { // X = ADD Y, Z  == X = ADD Z, Y
 429 // FIXME: Provide proper encoding!
 430 def ADD32rr : Pseudo<(outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
 431                      "ar\t{$dst, $src2}",
 432                      [(set GR32:$dst, (add GR32:$src1, GR32:$src2)),
 433                       (implicit PSW)]>;
 434 def ADD64rr : Pseudo<(outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
 435                      "agr\t{$dst, $src2}",
 436                      [(set GR64:$dst, (add GR64:$src1, GR64:$src2)),
 437                       (implicit PSW)]>;
 438 }
 439
 440 // FIXME: Provide proper encoding!
 441 def ADD32ri16 : Pseudo<(outs GR32:$dst), (ins GR32:$src1, s16imm:$src2),
 442                        "ahi\t{$dst, $src2}",
 443                        [(set GR32:$dst, (add GR32:$src1, immSExt16:$src2)),
 444                         (implicit PSW)]>;
 445 def ADD32ri   : Pseudo<(outs GR32:$dst), (ins GR32:$src1, s32imm:$src2),
 446                        "afi\t{$dst, $src2}",
 447                        [(set GR32:$dst, (add GR32:$src1, imm:$src2)),
 448                         (implicit PSW)]>;
 449 def ADD64ri16 : Pseudo<(outs GR64:$dst), (ins GR64:$src1, s16imm64:$src2),
 450                        "aghi\t{$dst, $src2}",
 451                        [(set GR64:$dst, (add GR64:$src1, immSExt16:$src2)),
 452                         (implicit PSW)]>;
 453 def ADD64ri32 : Pseudo<(outs GR64:$dst), (ins GR64:$src1, s32imm64:$src2),
 454                        "agfi\t{$dst, $src2}",
 455                        [(set GR64:$dst, (add GR64:$src1, immSExt32:$src2)),
 456                         (implicit PSW)]>;
 457
 458 let isCommutable = 1 in { // X = AND Y, Z  == X = AND Z, Y
 459 // FIXME: Provide proper encoding!
 460 def AND32rr : Pseudo<(outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
 461                      "nr\t{$dst, $src2}",
 462                      [(set GR32:$dst, (and GR32:$src1, GR32:$src2))]>;
 463 def AND64rr : Pseudo<(outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
 464                      "ngr\t{$dst, $src2}",
 465                      [(set GR64:$dst, (and GR64:$src1, GR64:$src2))]>;
 466 }
 467
 468 // FIXME: Provide proper encoding!
 469 // FIXME: Compute masked bits properly!
 470 def AND32rill16 : Pseudo<(outs GR32:$dst), (ins GR32:$src1, i32imm:$src2),
 471                          "nill\t{$dst, $src2}",
 472                         [(set GR32:$dst, (and GR32:$src1, i32ll16c:$src2))]>;
 473 def AND64rill16 : Pseudo<(outs GR64:$dst), (ins GR64:$src1, i64imm:$src2),
 474                          "nill\t{$dst, $src2}",
 475                          [(set GR64:$dst, (and GR64:$src1, i64ll16c:$src2))]>;
 476
 477 def AND32rilh16 : Pseudo<(outs GR32:$dst), (ins GR32:$src1, i32imm:$src2),
 478                          "nilh\t{$dst, $src2}",
 479                          [(set GR32:$dst, (and GR32:$src1, i32lh16c:$src2))]>;
 480 def AND64rilh16 : Pseudo<(outs GR64:$dst), (ins GR64:$src1, i64imm:$src2),
 481                          "nilh\t{$dst, $src2}",
 482                          [(set GR64:$dst, (and GR64:$src1, i64lh16c:$src2))]>;
 483
 484 def AND64rihl16 : Pseudo<(outs GR64:$dst), (ins GR64:$src1, i64imm:$src2),
 485                          "nihl\t{$dst, $src2}",
 486                          [(set GR64:$dst, (and GR64:$src1, i64hl16c:$src2))]>;
 487 def AND64rihh16 : Pseudo<(outs GR64:$dst), (ins GR64:$src1, i64imm:$src2),
 488                          "nihh\t{$dst, $src2}",
 489                          [(set GR64:$dst, (and GR64:$src1, i64hh16c:$src2))]>;
 490
 491 def AND32ri     : Pseudo<(outs GR32:$dst), (ins GR32:$src1, i32imm:$src2),
 492                          "nilf\t{$dst, $src2}",
 493                          [(set GR32:$dst, (and GR32:$src1, imm:$src2))]>;
 494 def AND64rilo32 : Pseudo<(outs GR64:$dst), (ins GR64:$src1, i64imm:$src2),
 495                          "nilf\t{$dst, $src2}",
 496                          [(set GR64:$dst, (and GR64:$src1, i64lo32c:$src2))]>;
 497 def AND64rihi32 : Pseudo<(outs GR64:$dst), (ins GR64:$src1, i64imm:$src2),
 498                          "nihf\t{$dst, $src2}",
 499                          [(set GR64:$dst, (and GR64:$src1, i64hi32c:$src2))]>;
 500
 501 let isCommutable = 1 in { // X = OR Y, Z  == X = OR Z, Y
 502 // FIXME: Provide proper encoding!
 503 def OR32rr : Pseudo<(outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
 504                     "or\t{$dst, $src2}",
 505                     [(set GR32:$dst, (or GR32:$src1, GR32:$src2))]>;
 506 def OR64rr : Pseudo<(outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
 507                     "ogr\t{$dst, $src2}",
 508                     [(set GR64:$dst, (or GR64:$src1, GR64:$src2))]>;
 509 }
 510
 511 def OR32ri16  : Pseudo<(outs GR32:$dst), (ins GR32:$src1, i32imm:$src2),
 512                       "oill\t{$dst, $src2}",
 513                       [(set GR32:$dst, (or GR32:$src1, i32ll16:$src2))]>;
 514 def OR32ri16h : Pseudo<(outs GR32:$dst), (ins GR32:$src1, i32imm:$src2),
 515                       "oilh\t{$dst, $src2}",
 516                       [(set GR32:$dst, (or GR32:$src1, i32lh16:$src2))]>;
 517 def OR32ri : Pseudo<(outs GR32:$dst), (ins GR32:$src1, i32imm:$src2),
 518                     "oilf\t{$dst, $src2}",
 519                     [(set GR32:$dst, (or GR32:$src1, imm:$src2))]>;
 520
 521 def OR64rill16 : Pseudo<(outs GR64:$dst), (ins GR64:$src1, i64imm:$src2),
 522                         "oill\t{$dst, $src2}",
 523                         [(set GR64:$dst, (or GR64:$src1, i64ll16:$src2))]>;
 524 def OR64rilh16 : Pseudo<(outs GR64:$dst), (ins GR64:$src1, i64imm:$src2),
 525                         "oilh\t{$dst, $src2}",
 526                         [(set GR64:$dst, (or GR64:$src1, i64lh16:$src2))]>;
 527 def OR64rihl16 : Pseudo<(outs GR64:$dst), (ins GR64:$src1, i64imm:$src2),
 528                         "oihl\t{$dst, $src2}",
 529                         [(set GR64:$dst, (or GR64:$src1, i64hl16:$src2))]>;
 530 def OR64rihh16 : Pseudo<(outs GR64:$dst), (ins GR64:$src1, i64imm:$src2),
 531                         "oihh\t{$dst, $src2}",
 532                         [(set GR64:$dst, (or GR64:$src1, i64hh16:$src2))]>;
 533
 534 def OR64rilo32 : Pseudo<(outs GR64:$dst), (ins GR64:$src1, i64imm:$src2),
 535                         "oilf\t{$dst, $src2}",
 536                         [(set GR64:$dst, (or GR64:$src1, i64lo32:$src2))]>;
 537 def OR64rihi32 : Pseudo<(outs GR64:$dst), (ins GR64:$src1, i64imm:$src2),
 538                         "oihf\t{$dst, $src2}",
 539                         [(set GR64:$dst, (or GR64:$src1, i64hi32:$src2))]>;
 540
 541 // FIXME: Provide proper encoding!
 542 def SUB32rr : Pseudo<(outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
 543                      "sr\t{$dst, $src2}",
 544                      [(set GR32:$dst, (sub GR32:$src1, GR32:$src2))]>;
 545 def SUB64rr : Pseudo<(outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
 546                      "sgr\t{$dst, $src2}",
 547                      [(set GR64:$dst, (sub GR64:$src1, GR64:$src2))]>;
 548
 549
 550 let isCommutable = 1 in { // X = XOR Y, Z  == X = XOR Z, Y
 551 // FIXME: Provide proper encoding!
 552 def XOR32rr : Pseudo<(outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
 553                      "xr\t{$dst, $src2}",
 554                      [(set GR32:$dst, (xor GR32:$src1, GR32:$src2))]>;
 555 def XOR64rr : Pseudo<(outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
 556                      "xgr\t{$dst, $src2}",
 557                      [(set GR64:$dst, (xor GR64:$src1, GR64:$src2))]>;
 558 }
 559
 560 def XOR32ri : Pseudo<(outs GR32:$dst), (ins GR32:$src1, i32imm:$src2),
 561                      "xilf\t{$dst, $src2}",
 562                      [(set GR32:$dst, (xor GR32:$src1, imm:$src2))]>;
 563
 564 } // Defs = [PSW]
 565
 566 let isCommutable = 1 in { // X = MUL Y, Z == X = MUL Z, Y
 567 def MUL32rr : Pseudo<(outs GR32:$dst), (ins GR32:$src1, GR32:$src2),
 568                      "msr\t{$dst, $src2}",
 569                      [(set GR32:$dst, (mul GR32:$src1, GR32:$src2))]>;
 570 def MUL64rr : Pseudo<(outs GR64:$dst), (ins GR64:$src1, GR64:$src2),
 571                      "msgr\t{$dst, $src2}",
 572                      [(set GR64:$dst, (mul GR64:$src1, GR64:$src2))]>;
 573 }
 574
 575 def MUL64rrP   : Pseudo<(outs GR64P:$dst), (ins GR64P:$src1, GR32:$src2),
 576                         "mr\t{$dst, $src2}",
 577                         []>;
 578 def UMUL64rrP  : Pseudo<(outs GR64P:$dst), (ins GR64P:$src1, GR32:$src2),
 579                          "mlr\t{$dst, $src2}",
 580                          []>;
 581 def UMUL128rrP : Pseudo<(outs GR128:$dst), (ins GR128:$src1, GR64:$src2),
 582                         "mlgr\t{$dst, $src2}",
 583                         []>;
 584
 585 def MUL32ri16   : Pseudo<(outs GR32:$dst), (ins GR32:$src1, s16imm:$src2),
 586                          "mhi\t{$dst, $src2}",
 587                          [(set GR32:$dst, (mul GR32:$src1, i32immSExt16:$src2))]>;
 588 def MUL64ri16   : Pseudo<(outs GR64:$dst), (ins GR64:$src1, s16imm64:$src2),
 589                          "mghi\t{$dst, $src2}",
 590                          [(set GR64:$dst, (mul GR64:$src1, immSExt16:$src2))]>;
 591
 592 def MUL32ri     : Pseudo<(outs GR32:$dst), (ins GR32:$src1, s32imm:$src2),
 593                          "msfi\t{$dst, $src2}",
 594                          [(set GR32:$dst, (mul GR32:$src1, imm:$src2))]>,
 595                          Requires<[IsZ10]>;
 596 def MUL64ri32   : Pseudo<(outs GR64:$dst), (ins GR64:$src1, s32imm64:$src2),
 597                          "msgfi\t{$dst, $src2}",
 598                          [(set GR64:$dst, (mul GR64:$src1, i64immSExt32:$src2))]>,
 599                          Requires<[IsZ10]>;
 600
 601 def MUL32rm : Pseudo<(outs GR32:$dst), (ins GR32:$src1, rriaddr12:$src2),
 602                      "ms\t{$dst, $src2}",
 603                      [(set GR32:$dst, (mul GR32:$src1, (load rriaddr12:$src2)))]>;
 604 def MUL32rmy : Pseudo<(outs GR32:$dst), (ins GR32:$src1, rriaddr:$src2),
 605                       "msy\t{$dst, $src2}",
 606                       [(set GR32:$dst, (mul GR32:$src1, (load rriaddr:$src2)))]>;
 607 def MUL64rm  : Pseudo<(outs GR64:$dst), (ins GR64:$src1, rriaddr:$src2),
 608                       "msg\t{$dst, $src2}",
 609                       [(set GR64:$dst, (mul GR64:$src1, (load rriaddr:$src2)))]>;
 610
 611 def MULSX64rr32 : Pseudo<(outs GR64:$dst), (ins GR64:$src1, GR32:$src2),
 612                          "msgfr\t{$dst, $src2}",
 613                          [(set GR64:$dst, (mul GR64:$src1, (sext GR32:$src2)))]>;
 614
 615 def SDIVREM32r : Pseudo<(outs GR128:$dst), (ins GR128:$src1, GR32:$src2),
 616                         "dsgfr\t{$dst, $src2}",
 617                         []>;
 618 def SDIVREM64r : Pseudo<(outs GR128:$dst), (ins GR128:$src1, GR64:$src2),
 619                         "dsgr\t{$dst, $src2}",
 620                         []>;
 621
 622 def UDIVREM32r : Pseudo<(outs GR64P:$dst), (ins GR64P:$src1, GR32:$src2),
 623                         "dlr\t{$dst, $src2}",
 624                         []>;
 625 def UDIVREM64r : Pseudo<(outs GR128:$dst), (ins GR128:$src1, GR64:$src2),
 626                         "dlgr\t{$dst, $src2}",
 627                         []>;
 628 let mayLoad = 1 in {
 629 def SDIVREM32m : Pseudo<(outs GR128:$dst), (ins GR128:$src1, rriaddr:$src2),
 630                         "dsgf\t{$dst, $src2}",
 631                         []>;
 632 def SDIVREM64m : Pseudo<(outs GR128:$dst), (ins GR128:$src1, rriaddr:$src2),
 633                         "dsg\t{$dst, $src2}",
 634                         []>;
 635
 636 def UDIVREM32m : Pseudo<(outs GR64P:$dst), (ins GR64P:$src1, rriaddr:$src2),
 637                         "dl\t{$dst, $src2}",
 638                         []>;
 639 def UDIVREM64m : Pseudo<(outs GR128:$dst), (ins GR128:$src1, rriaddr:$src2),
 640                         "dlg\t{$dst, $src2}",
 641                         []>;
 642 } // mayLoad
 643 } // isTwoAddress = 1
 644
 645 //===----------------------------------------------------------------------===//
 646 // Shifts
 647
 648 let isTwoAddress = 1 in
 649 def SRL32rri : Pseudo<(outs GR32:$dst), (ins GR32:$src, riaddr32:$amt),
 650                       "srl\t{$src, $amt}",
 651                       [(set GR32:$dst, (srl GR32:$src, riaddr32:$amt))]>;
 652 def SRL64rri : Pseudo<(outs GR64:$dst), (ins GR64:$src, riaddr:$amt),
 653                       "srlg\t{$dst, $src, $amt}",
 654                       [(set GR64:$dst, (srl GR64:$src, riaddr:$amt))]>;
 655
 656 let isTwoAddress = 1 in
 657 def SHL32rri : Pseudo<(outs GR32:$dst), (ins GR32:$src, riaddr32:$amt),
 658                       "sll\t{$src, $amt}",
 659                       [(set GR32:$dst, (shl GR32:$src, riaddr32:$amt))]>;
 660 def SHL64rri : Pseudo<(outs GR64:$dst), (ins GR64:$src, riaddr:$amt),
 661                       "sllg\t{$dst, $src, $amt}",
 662                       [(set GR64:$dst, (shl GR64:$src, riaddr:$amt))]>;
 663
 664 let Defs = [PSW] in {
 665 let isTwoAddress = 1 in
 666 def SRA32rri : Pseudo<(outs GR32:$dst), (ins GR32:$src, riaddr32:$amt),
 667                       "sra\t{$src, $amt}",
 668                       [(set GR32:$dst, (sra GR32:$src, riaddr32:$amt)),
 669                        (implicit PSW)]>;
 670
 671 def SRA64rri : Pseudo<(outs GR64:$dst), (ins GR64:$src, riaddr:$amt),
 672                       "srag\t{$dst, $src, $amt}",
 673                       [(set GR64:$dst, (sra GR64:$src, riaddr:$amt)),
 674                        (implicit PSW)]>;
 675 } // Defs = [PSW]
 676
 677 def ROTL32rri : Pseudo<(outs GR32:$dst), (ins GR32:$src, riaddr32:$amt),
 678                        "rll\t{$dst, $src, $amt}",
 679                        [(set GR32:$dst, (rotl GR32:$src, riaddr32:$amt))]>;
 680 def ROTL64rri : Pseudo<(outs GR64:$dst), (ins GR64:$src, riaddr:$amt),
 681                        "rllg\t{$dst, $src, $amt}",
 682                        [(set GR64:$dst, (rotl GR64:$src, riaddr:$amt))]>;
 683
 684 //===----------------------------------------------------------------------===//
 685 // Test instructions (like AND but do not produce any result)
 686
 687 // Integer comparisons
 688 let Defs = [PSW] in {
 689 def CMP32rr : Pseudo<(outs), (ins GR32:$src1, GR32:$src2),
 690                      "cr\t$src1, $src2",
 691                      [(SystemZcmp GR32:$src1, GR32:$src2), (implicit PSW)]>;
 692 def CMP64rr : Pseudo<(outs), (ins GR64:$src1, GR64:$src2),
 693                      "cgr\t$src1, $src2",
 694                      [(SystemZcmp GR64:$src1, GR64:$src2), (implicit PSW)]>;
 695
 696 def CMP32ri   : Pseudo<(outs), (ins GR32:$src1, s32imm:$src2),
 697                        "cfi\t$src1, $src2",
 698                        [(SystemZcmp GR32:$src1, imm:$src2), (implicit PSW)]>;
 699 def CMP64ri32 : Pseudo<(outs), (ins GR64:$src1, s32imm64:$src2),
 700                        "cgfi\t$src1, $src2",
 701                        [(SystemZcmp GR64:$src1, i64immSExt32:$src2),
 702                         (implicit PSW)]>;
 703
 704 def CMP32rm : Pseudo<(outs), (ins GR32:$src1, rriaddr12:$src2),
 705                      "c\t$src1, $src2",
 706                      [(SystemZcmp GR32:$src1, (load rriaddr12:$src2)),
 707                       (implicit PSW)]>;
 708 def CMP32rmy : Pseudo<(outs), (ins GR32:$src1, rriaddr:$src2),
 709                       "cy\t$src1, $src2",
 710                       [(SystemZcmp GR32:$src1, (load rriaddr:$src2)),
 711                        (implicit PSW)]>;
 712 def CMP64rm  : Pseudo<(outs), (ins GR64:$src1, rriaddr:$src2),
 713                       "cg\t$src1, $src2",
 714                       [(SystemZcmp GR64:$src1, (load rriaddr:$src2)),
 715                        (implicit PSW)]>;
 716
 717 def UCMP32rr : Pseudo<(outs), (ins GR32:$src1, GR32:$src2),
 718                       "clr\t$src1, $src2",
 719                       [(SystemZucmp GR32:$src1, GR32:$src2), (implicit PSW)]>;
 720 def UCMP64rr : Pseudo<(outs), (ins GR64:$src1, GR64:$src2),
 721                       "clgr\t$src1, $src2",
 722                       [(SystemZucmp GR64:$src1, GR64:$src2), (implicit PSW)]>;
 723
 724 def UCMP32ri   : Pseudo<(outs), (ins GR32:$src1, i32imm:$src2),
 725                         "clfi\t$src1, $src2",
 726                         [(SystemZucmp GR32:$src1, imm:$src2), (implicit PSW)]>;
 727 def UCMP64ri32 : Pseudo<(outs), (ins GR64:$src1, i64i32imm:$src2),
 728                         "clgfi\t$src1, $src2",
 729                         [(SystemZucmp GR64:$src1, i64immZExt32:$src2),
 730                          (implicit PSW)]>;
 731
 732 def UCMP32rm  : Pseudo<(outs), (ins GR32:$src1, rriaddr12:$src2),
 733                        "cl\t$src1, $src2",
 734                        [(SystemZucmp GR32:$src1, (load rriaddr12:$src2)),
 735                         (implicit PSW)]>;
 736 def UCMP32rmy : Pseudo<(outs), (ins GR32:$src1, rriaddr:$src2),
 737                        "cly\t$src1, $src2",
 738                        [(SystemZucmp GR32:$src1, (load rriaddr:$src2)),
 739                         (implicit PSW)]>;
 740 def UCMP64rm  : Pseudo<(outs), (ins GR64:$src1, rriaddr:$src2),
 741                        "clg\t$src1, $src2",
 742                        [(SystemZucmp GR64:$src1, (load rriaddr:$src2)),
 743                         (implicit PSW)]>;
 744
 745 def CMPSX64rr32  : Pseudo<(outs), (ins GR64:$src1, GR32:$src2),
 746                           "cgfr\t$src1, $src2",
 747                           [(SystemZucmp GR64:$src1, (sext GR32:$src2)),
 748                            (implicit PSW)]>;
 749 def UCMPZX64rr32 : Pseudo<(outs), (ins GR64:$src1, GR32:$src2),
 750                           "clgfr\t$src1, $src2",
 751                           [(SystemZucmp GR64:$src1, (zext GR32:$src2)),
 752                            (implicit PSW)]>;
 753
 754 def CMPSX64rm32   : Pseudo<(outs), (ins GR64:$src1, rriaddr:$src2),
 755                            "cgf\t$src1, $src2",
 756                            [(SystemZucmp GR64:$src1, (sextloadi64i32 rriaddr:$src2)),
 757                             (implicit PSW)]>;
 758 def UCMPZX64rm32  : Pseudo<(outs), (ins GR64:$src1, rriaddr:$src2),
 759                            "clgf\t$src1, $src2",
 760                            [(SystemZucmp GR64:$src1, (zextloadi64i32 rriaddr:$src2)),
 761                             (implicit PSW)]>;
 762
 763 // FIXME: Add other crazy ucmp forms
 764
 765 } // Defs = [PSW]
 766
 767 //===----------------------------------------------------------------------===//
 768 // Non-Instruction Patterns.
 769 //===----------------------------------------------------------------------===//
 770
 771 // ConstPools, JumpTables
 772 def : Pat<(SystemZpcrelwrapper tjumptable:$src), (LA64rm tjumptable:$src)>;
 773 def : Pat<(SystemZpcrelwrapper tconstpool:$src), (LA64rm tconstpool:$src)>;
 774
 775 // anyext
 776 def : Pat<(i64 (anyext GR32:$src)), (MOVZX64rr32 GR32:$src)>;
 777
 778 // calls
 779 def : Pat<(SystemZcall (i64 tglobaladdr:$dst)), (CALLi tglobaladdr:$dst)>;
 780 def : Pat<(SystemZcall (i64 texternalsym:$dst)), (CALLi texternalsym:$dst)>;
 781
 782 //===----------------------------------------------------------------------===//
 783 // Peepholes.
 784 //===----------------------------------------------------------------------===//
 785
 786 // FIXME: use add/sub tricks with 32678/-32768
 787
 788 // Arbitrary immediate support.  Implement in terms of LLIHF/OILF.
 789 def : Pat<(i64 imm:$imm),
 790           (OR64rilo32 (MOV64rihi32 (HI32 imm:$imm)), (LO32 imm:$imm))>;
 791
 792 // trunc patterns
 793 def : Pat<(i32 (trunc GR64:$src)),
 794           (EXTRACT_SUBREG GR64:$src, subreg_32bit)>;
 795
 796 // sext_inreg patterns
 797 def : Pat<(sext_inreg GR64:$src, i32),
 798           (MOVSX64rr32 (EXTRACT_SUBREG GR64:$src, subreg_32bit))>;
 799
 800 // extload patterns
 801 def : Pat<(extloadi32i8  rriaddr:$src), (MOVZX32rm8  rriaddr:$src)>;
 802 def : Pat<(extloadi32i16 rriaddr:$src), (MOVZX32rm16 rriaddr:$src)>;
 803 def : Pat<(extloadi64i8  rriaddr:$src), (MOVZX64rm8  rriaddr:$src)>;
 804 def : Pat<(extloadi64i16 rriaddr:$src), (MOVZX64rm16 rriaddr:$src)>;
 805 def : Pat<(extloadi64i32 rriaddr:$src), (MOVZX64rm32 rriaddr:$src)>;
 806
 807 // muls
 808 def : Pat<(mulhs GR32:$src1, GR32:$src2),
 809           (EXTRACT_SUBREG (MUL64rrP (INSERT_SUBREG (i64 (IMPLICIT_DEF)),
 810                                                    GR32:$src1, subreg_odd32),
 811                                     GR32:$src2),
 812                           subreg_even32)>;
 813
 814 def : Pat<(mulhu GR32:$src1, GR32:$src2),
 815           (EXTRACT_SUBREG (UMUL64rrP (INSERT_SUBREG (i64 (IMPLICIT_DEF)),
 816                                                     GR32:$src1, subreg_odd32),
 817                                      GR32:$src2),
 818                           subreg_even32)>;
 819 def : Pat<(mulhu GR64:$src1, GR64:$src2),
 820           (EXTRACT_SUBREG (UMUL128rrP (INSERT_SUBREG (i128 (IMPLICIT_DEF)),
 821                                                      GR64:$src1, subreg_odd),
 822                                       GR64:$src2),
 823                           subreg_even)>;
 824
 825 def : Pat<(i32 imm:$src),
 826           (EXTRACT_SUBREG (MOV64ri32 (i64 imm:$src)), subreg_32bit)>;