1 //===-- SystemZInstrInfo.h - SystemZ instruction information ----*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the SystemZ implementation of the TargetInstrInfo class.
12 //===----------------------------------------------------------------------===//
14 #ifndef LLVM_TARGET_SYSTEMZINSTRINFO_H
15 #define LLVM_TARGET_SYSTEMZINSTRINFO_H
18 #include "SystemZRegisterInfo.h"
19 #include "llvm/Target/TargetInstrInfo.h"
21 #define GET_INSTRINFO_HEADER
22 #include "SystemZGenInstrInfo.inc"
26 class SystemZTargetMachine;
30 // See comments in SystemZInstrFormats.td.
31 SimpleBDXLoad = (1 << 0),
32 SimpleBDXStore = (1 << 1),
33 Has20BitOffset = (1 << 2),
36 AccessSizeMask = (31 << 5),
39 static inline unsigned getAccessSize(unsigned int Flags) {
40 return (Flags & AccessSizeMask) >> AccessSizeShift;
43 // SystemZ MachineOperand target flags.
45 // Masks out the bits for the access model.
46 MO_SYMBOL_MODIFIER = (1 << 0),
51 // Classifies a branch.
53 // An instruction that branches on the current value of CC.
56 // An instruction that peforms a 32-bit signed comparison and branches
60 // An instruction that peforms a 64-bit signed comparison and branches
64 // Information about a branch instruction.
66 // The type of the branch.
69 // CCMASK_<N> is set if CC might be equal to N.
72 // CCMASK_<N> is set if the branch should be taken when CC == N.
75 // The target of the branch.
76 const MachineOperand *Target;
78 Branch(BranchType type, unsigned ccValid, unsigned ccMask,
79 const MachineOperand *target)
80 : Type(type), CCValid(ccValid), CCMask(ccMask), Target(target) {}
84 class SystemZInstrInfo : public SystemZGenInstrInfo {
85 const SystemZRegisterInfo RI;
86 SystemZTargetMachine &TM;
88 void splitMove(MachineBasicBlock::iterator MI, unsigned NewOpcode) const;
89 void splitAdjDynAlloc(MachineBasicBlock::iterator MI) const;
92 explicit SystemZInstrInfo(SystemZTargetMachine &TM);
94 // Override TargetInstrInfo.
95 virtual unsigned isLoadFromStackSlot(const MachineInstr *MI,
96 int &FrameIndex) const LLVM_OVERRIDE;
97 virtual unsigned isStoreToStackSlot(const MachineInstr *MI,
98 int &FrameIndex) const LLVM_OVERRIDE;
99 virtual bool isStackSlotCopy(const MachineInstr *MI, int &DestFrameIndex,
100 int &SrcFrameIndex) const LLVM_OVERRIDE;
101 virtual bool AnalyzeBranch(MachineBasicBlock &MBB,
102 MachineBasicBlock *&TBB,
103 MachineBasicBlock *&FBB,
104 SmallVectorImpl<MachineOperand> &Cond,
105 bool AllowModify) const LLVM_OVERRIDE;
106 virtual unsigned RemoveBranch(MachineBasicBlock &MBB) const LLVM_OVERRIDE;
107 virtual unsigned InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
108 MachineBasicBlock *FBB,
109 const SmallVectorImpl<MachineOperand> &Cond,
110 DebugLoc DL) const LLVM_OVERRIDE;
111 virtual bool isPredicable(MachineInstr *MI) const LLVM_OVERRIDE;
112 virtual bool isProfitableToIfCvt(MachineBasicBlock &MBB, unsigned NumCycles,
113 unsigned ExtraPredCycles,
114 const BranchProbability &Probability) const
116 virtual bool isProfitableToIfCvt(MachineBasicBlock &TMBB,
118 unsigned ExtraPredCyclesT,
119 MachineBasicBlock &FMBB,
121 unsigned ExtraPredCyclesF,
122 const BranchProbability &Probability) const
125 PredicateInstruction(MachineInstr *MI,
126 const SmallVectorImpl<MachineOperand> &Pred) const
128 virtual void copyPhysReg(MachineBasicBlock &MBB,
129 MachineBasicBlock::iterator MBBI, DebugLoc DL,
130 unsigned DestReg, unsigned SrcReg,
131 bool KillSrc) const LLVM_OVERRIDE;
133 storeRegToStackSlot(MachineBasicBlock &MBB,
134 MachineBasicBlock::iterator MBBI,
135 unsigned SrcReg, bool isKill, int FrameIndex,
136 const TargetRegisterClass *RC,
137 const TargetRegisterInfo *TRI) const LLVM_OVERRIDE;
139 loadRegFromStackSlot(MachineBasicBlock &MBB,
140 MachineBasicBlock::iterator MBBI,
141 unsigned DestReg, int FrameIdx,
142 const TargetRegisterClass *RC,
143 const TargetRegisterInfo *TRI) const LLVM_OVERRIDE;
144 virtual MachineInstr *
145 convertToThreeAddress(MachineFunction::iterator &MFI,
146 MachineBasicBlock::iterator &MBBI,
147 LiveVariables *LV) const;
148 virtual MachineInstr *
149 foldMemoryOperandImpl(MachineFunction &MF, MachineInstr *MI,
150 const SmallVectorImpl<unsigned> &Ops,
151 int FrameIndex) const;
152 virtual MachineInstr *
153 foldMemoryOperandImpl(MachineFunction &MF, MachineInstr* MI,
154 const SmallVectorImpl<unsigned> &Ops,
155 MachineInstr* LoadMI) const;
157 expandPostRAPseudo(MachineBasicBlock::iterator MBBI) const LLVM_OVERRIDE;
159 ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const
162 // Return the SystemZRegisterInfo, which this class owns.
163 const SystemZRegisterInfo &getRegisterInfo() const { return RI; }
165 // Return the size in bytes of MI.
166 uint64_t getInstSizeInBytes(const MachineInstr *MI) const;
168 // Return true if MI is a conditional or unconditional branch.
169 // When returning true, set Cond to the mask of condition-code
170 // values on which the instruction will branch, and set Target
171 // to the operand that contains the branch target. This target
172 // can be a register or a basic block.
173 SystemZII::Branch getBranchInfo(const MachineInstr *MI) const;
175 // Get the load and store opcodes for a given register class.
176 void getLoadStoreOpcodes(const TargetRegisterClass *RC,
177 unsigned &LoadOpcode, unsigned &StoreOpcode) const;
179 // Opcode is the opcode of an instruction that has an address operand,
180 // and the caller wants to perform that instruction's operation on an
181 // address that has displacement Offset. Return the opcode of a suitable
182 // instruction (which might be Opcode itself) or 0 if no such instruction
184 unsigned getOpcodeForOffset(unsigned Opcode, int64_t Offset) const;
186 // Return true if ROTATE AND ... SELECTED BITS can be used to select bits
187 // Mask of the R2 operand, given that only the low BitSize bits of Mask are
188 // significant. Set Start and End to the I3 and I4 operands if so.
189 bool isRxSBGMask(uint64_t Mask, unsigned BitSize,
190 unsigned &Start, unsigned &End) const;
192 // If Opcode is a COMPARE opcode for which an associated COMPARE AND
193 // BRANCH exists, return the opcode for the latter, otherwise return 0.
194 // MI, if nonnull, is the compare instruction.
195 unsigned getCompareAndBranch(unsigned Opcode,
196 const MachineInstr *MI = 0) const;
198 // Emit code before MBBI in MI to move immediate value Value into
199 // physical register Reg.
200 void loadImmediate(MachineBasicBlock &MBB,
201 MachineBasicBlock::iterator MBBI,
202 unsigned Reg, uint64_t Value) const;
204 } // end namespace llvm