1 //===-- SystemZInstrInfo.cpp - SystemZ instruction information ------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the SystemZ implementation of the TargetInstrInfo class.
12 //===----------------------------------------------------------------------===//
14 #include "SystemZInstrInfo.h"
15 #include "SystemZTargetMachine.h"
16 #include "SystemZInstrBuilder.h"
17 #include "llvm/CodeGen/LiveVariables.h"
18 #include "llvm/CodeGen/MachineRegisterInfo.h"
20 #define GET_INSTRINFO_CTOR
21 #define GET_INSTRMAP_INFO
22 #include "SystemZGenInstrInfo.inc"
26 // Return a mask with Count low bits set.
27 static uint64_t allOnes(unsigned int Count) {
28 return Count == 0 ? 0 : (uint64_t(1) << (Count - 1) << 1) - 1;
31 SystemZInstrInfo::SystemZInstrInfo(SystemZTargetMachine &tm)
32 : SystemZGenInstrInfo(SystemZ::ADJCALLSTACKDOWN, SystemZ::ADJCALLSTACKUP),
36 // MI is a 128-bit load or store. Split it into two 64-bit loads or stores,
37 // each having the opcode given by NewOpcode.
38 void SystemZInstrInfo::splitMove(MachineBasicBlock::iterator MI,
39 unsigned NewOpcode) const {
40 MachineBasicBlock *MBB = MI->getParent();
41 MachineFunction &MF = *MBB->getParent();
43 // Get two load or store instructions. Use the original instruction for one
44 // of them (arbitarily the second here) and create a clone for the other.
45 MachineInstr *EarlierMI = MF.CloneMachineInstr(MI);
46 MBB->insert(MI, EarlierMI);
48 // Set up the two 64-bit registers.
49 MachineOperand &HighRegOp = EarlierMI->getOperand(0);
50 MachineOperand &LowRegOp = MI->getOperand(0);
51 HighRegOp.setReg(RI.getSubReg(HighRegOp.getReg(), SystemZ::subreg_high));
52 LowRegOp.setReg(RI.getSubReg(LowRegOp.getReg(), SystemZ::subreg_low));
54 // The address in the first (high) instruction is already correct.
55 // Adjust the offset in the second (low) instruction.
56 MachineOperand &HighOffsetOp = EarlierMI->getOperand(2);
57 MachineOperand &LowOffsetOp = MI->getOperand(2);
58 LowOffsetOp.setImm(LowOffsetOp.getImm() + 8);
61 unsigned HighOpcode = getOpcodeForOffset(NewOpcode, HighOffsetOp.getImm());
62 unsigned LowOpcode = getOpcodeForOffset(NewOpcode, LowOffsetOp.getImm());
63 assert(HighOpcode && LowOpcode && "Both offsets should be in range");
65 EarlierMI->setDesc(get(HighOpcode));
66 MI->setDesc(get(LowOpcode));
69 // Split ADJDYNALLOC instruction MI.
70 void SystemZInstrInfo::splitAdjDynAlloc(MachineBasicBlock::iterator MI) const {
71 MachineBasicBlock *MBB = MI->getParent();
72 MachineFunction &MF = *MBB->getParent();
73 MachineFrameInfo *MFFrame = MF.getFrameInfo();
74 MachineOperand &OffsetMO = MI->getOperand(2);
76 uint64_t Offset = (MFFrame->getMaxCallFrameSize() +
77 SystemZMC::CallFrameSize +
79 unsigned NewOpcode = getOpcodeForOffset(SystemZ::LA, Offset);
80 assert(NewOpcode && "No support for huge argument lists yet");
81 MI->setDesc(get(NewOpcode));
82 OffsetMO.setImm(Offset);
85 // If MI is a simple load or store for a frame object, return the register
86 // it loads or stores and set FrameIndex to the index of the frame object.
87 // Return 0 otherwise.
89 // Flag is SimpleBDXLoad for loads and SimpleBDXStore for stores.
90 static int isSimpleMove(const MachineInstr *MI, int &FrameIndex,
92 const MCInstrDesc &MCID = MI->getDesc();
93 if ((MCID.TSFlags & Flag) &&
94 MI->getOperand(1).isFI() &&
95 MI->getOperand(2).getImm() == 0 &&
96 MI->getOperand(3).getReg() == 0) {
97 FrameIndex = MI->getOperand(1).getIndex();
98 return MI->getOperand(0).getReg();
103 unsigned SystemZInstrInfo::isLoadFromStackSlot(const MachineInstr *MI,
104 int &FrameIndex) const {
105 return isSimpleMove(MI, FrameIndex, SystemZII::SimpleBDXLoad);
108 unsigned SystemZInstrInfo::isStoreToStackSlot(const MachineInstr *MI,
109 int &FrameIndex) const {
110 return isSimpleMove(MI, FrameIndex, SystemZII::SimpleBDXStore);
113 bool SystemZInstrInfo::isStackSlotCopy(const MachineInstr *MI,
115 int &SrcFrameIndex) const {
116 // Check for MVC 0(Length,FI1),0(FI2)
117 const MachineFrameInfo *MFI = MI->getParent()->getParent()->getFrameInfo();
118 if (MI->getOpcode() != SystemZ::MVC ||
119 !MI->getOperand(0).isFI() ||
120 MI->getOperand(1).getImm() != 0 ||
121 !MI->getOperand(3).isFI() ||
122 MI->getOperand(4).getImm() != 0)
125 // Check that Length covers the full slots.
126 int64_t Length = MI->getOperand(2).getImm();
127 unsigned FI1 = MI->getOperand(0).getIndex();
128 unsigned FI2 = MI->getOperand(3).getIndex();
129 if (MFI->getObjectSize(FI1) != Length ||
130 MFI->getObjectSize(FI2) != Length)
133 DestFrameIndex = FI1;
138 bool SystemZInstrInfo::AnalyzeBranch(MachineBasicBlock &MBB,
139 MachineBasicBlock *&TBB,
140 MachineBasicBlock *&FBB,
141 SmallVectorImpl<MachineOperand> &Cond,
142 bool AllowModify) const {
143 // Most of the code and comments here are boilerplate.
145 // Start from the bottom of the block and work up, examining the
146 // terminator instructions.
147 MachineBasicBlock::iterator I = MBB.end();
148 while (I != MBB.begin()) {
150 if (I->isDebugValue())
153 // Working from the bottom, when we see a non-terminator instruction, we're
155 if (!isUnpredicatedTerminator(I))
158 // A terminator that isn't a branch can't easily be handled by this
163 // Can't handle indirect branches.
164 SystemZII::Branch Branch(getBranchInfo(I));
165 if (!Branch.Target->isMBB())
168 // Punt on compound branches.
169 if (Branch.Type != SystemZII::BranchNormal)
172 if (Branch.CCMask == SystemZ::CCMASK_ANY) {
173 // Handle unconditional branches.
175 TBB = Branch.Target->getMBB();
179 // If the block has any instructions after a JMP, delete them.
180 while (llvm::next(I) != MBB.end())
181 llvm::next(I)->eraseFromParent();
186 // Delete the JMP if it's equivalent to a fall-through.
187 if (MBB.isLayoutSuccessor(Branch.Target->getMBB())) {
189 I->eraseFromParent();
194 // TBB is used to indicate the unconditinal destination.
195 TBB = Branch.Target->getMBB();
199 // Working from the bottom, handle the first conditional branch.
201 // FIXME: add X86-style branch swap
203 TBB = Branch.Target->getMBB();
204 Cond.push_back(MachineOperand::CreateImm(Branch.CCValid));
205 Cond.push_back(MachineOperand::CreateImm(Branch.CCMask));
209 // Handle subsequent conditional branches.
210 assert(Cond.size() == 2 && TBB && "Should have seen a conditional branch");
212 // Only handle the case where all conditional branches branch to the same
214 if (TBB != Branch.Target->getMBB())
217 // If the conditions are the same, we can leave them alone.
218 unsigned OldCCValid = Cond[0].getImm();
219 unsigned OldCCMask = Cond[1].getImm();
220 if (OldCCValid == Branch.CCValid && OldCCMask == Branch.CCMask)
223 // FIXME: Try combining conditions like X86 does. Should be easy on Z!
230 unsigned SystemZInstrInfo::RemoveBranch(MachineBasicBlock &MBB) const {
231 // Most of the code and comments here are boilerplate.
232 MachineBasicBlock::iterator I = MBB.end();
235 while (I != MBB.begin()) {
237 if (I->isDebugValue())
241 if (!getBranchInfo(I).Target->isMBB())
243 // Remove the branch.
244 I->eraseFromParent();
252 bool SystemZInstrInfo::
253 ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const {
254 assert(Cond.size() == 2 && "Invalid condition");
255 Cond[1].setImm(Cond[1].getImm() ^ Cond[0].getImm());
260 SystemZInstrInfo::InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
261 MachineBasicBlock *FBB,
262 const SmallVectorImpl<MachineOperand> &Cond,
264 // In this function we output 32-bit branches, which should always
265 // have enough range. They can be shortened and relaxed by later code
266 // in the pipeline, if desired.
268 // Shouldn't be a fall through.
269 assert(TBB && "InsertBranch must not be told to insert a fallthrough");
270 assert((Cond.size() == 2 || Cond.size() == 0) &&
271 "SystemZ branch conditions have one component!");
274 // Unconditional branch?
275 assert(!FBB && "Unconditional branch with multiple successors!");
276 BuildMI(&MBB, DL, get(SystemZ::J)).addMBB(TBB);
280 // Conditional branch.
282 unsigned CCValid = Cond[0].getImm();
283 unsigned CCMask = Cond[1].getImm();
284 BuildMI(&MBB, DL, get(SystemZ::BRC))
285 .addImm(CCValid).addImm(CCMask).addMBB(TBB);
289 // Two-way Conditional branch. Insert the second branch.
290 BuildMI(&MBB, DL, get(SystemZ::J)).addMBB(FBB);
296 // If Opcode is a move that has a conditional variant, return that variant,
297 // otherwise return 0.
298 static unsigned getConditionalMove(unsigned Opcode) {
300 case SystemZ::LR: return SystemZ::LOCR;
301 case SystemZ::LGR: return SystemZ::LOCGR;
306 bool SystemZInstrInfo::isPredicable(MachineInstr *MI) const {
307 unsigned Opcode = MI->getOpcode();
308 if (TM.getSubtargetImpl()->hasLoadStoreOnCond() &&
309 getConditionalMove(Opcode))
314 bool SystemZInstrInfo::
315 isProfitableToIfCvt(MachineBasicBlock &MBB,
316 unsigned NumCycles, unsigned ExtraPredCycles,
317 const BranchProbability &Probability) const {
318 // For now only convert single instructions.
319 return NumCycles == 1;
322 bool SystemZInstrInfo::
323 isProfitableToIfCvt(MachineBasicBlock &TMBB,
324 unsigned NumCyclesT, unsigned ExtraPredCyclesT,
325 MachineBasicBlock &FMBB,
326 unsigned NumCyclesF, unsigned ExtraPredCyclesF,
327 const BranchProbability &Probability) const {
328 // For now avoid converting mutually-exclusive cases.
332 bool SystemZInstrInfo::
333 PredicateInstruction(MachineInstr *MI,
334 const SmallVectorImpl<MachineOperand> &Pred) const {
335 assert(Pred.size() == 2 && "Invalid condition");
336 unsigned CCValid = Pred[0].getImm();
337 unsigned CCMask = Pred[1].getImm();
338 assert(CCMask > 0 && CCMask < 15 && "Invalid predicate");
339 unsigned Opcode = MI->getOpcode();
340 if (TM.getSubtargetImpl()->hasLoadStoreOnCond()) {
341 if (unsigned CondOpcode = getConditionalMove(Opcode)) {
342 MI->setDesc(get(CondOpcode));
343 MachineInstrBuilder(*MI->getParent()->getParent(), MI)
344 .addImm(CCValid).addImm(CCMask);
352 SystemZInstrInfo::copyPhysReg(MachineBasicBlock &MBB,
353 MachineBasicBlock::iterator MBBI, DebugLoc DL,
354 unsigned DestReg, unsigned SrcReg,
355 bool KillSrc) const {
356 // Split 128-bit GPR moves into two 64-bit moves. This handles ADDR128 too.
357 if (SystemZ::GR128BitRegClass.contains(DestReg, SrcReg)) {
358 copyPhysReg(MBB, MBBI, DL, RI.getSubReg(DestReg, SystemZ::subreg_high),
359 RI.getSubReg(SrcReg, SystemZ::subreg_high), KillSrc);
360 copyPhysReg(MBB, MBBI, DL, RI.getSubReg(DestReg, SystemZ::subreg_low),
361 RI.getSubReg(SrcReg, SystemZ::subreg_low), KillSrc);
365 // Everything else needs only one instruction.
367 if (SystemZ::GR32BitRegClass.contains(DestReg, SrcReg))
368 Opcode = SystemZ::LR;
369 else if (SystemZ::GR64BitRegClass.contains(DestReg, SrcReg))
370 Opcode = SystemZ::LGR;
371 else if (SystemZ::FP32BitRegClass.contains(DestReg, SrcReg))
372 Opcode = SystemZ::LER;
373 else if (SystemZ::FP64BitRegClass.contains(DestReg, SrcReg))
374 Opcode = SystemZ::LDR;
375 else if (SystemZ::FP128BitRegClass.contains(DestReg, SrcReg))
376 Opcode = SystemZ::LXR;
378 llvm_unreachable("Impossible reg-to-reg copy");
380 BuildMI(MBB, MBBI, DL, get(Opcode), DestReg)
381 .addReg(SrcReg, getKillRegState(KillSrc));
385 SystemZInstrInfo::storeRegToStackSlot(MachineBasicBlock &MBB,
386 MachineBasicBlock::iterator MBBI,
387 unsigned SrcReg, bool isKill,
389 const TargetRegisterClass *RC,
390 const TargetRegisterInfo *TRI) const {
391 DebugLoc DL = MBBI != MBB.end() ? MBBI->getDebugLoc() : DebugLoc();
393 // Callers may expect a single instruction, so keep 128-bit moves
394 // together for now and lower them after register allocation.
395 unsigned LoadOpcode, StoreOpcode;
396 getLoadStoreOpcodes(RC, LoadOpcode, StoreOpcode);
397 addFrameReference(BuildMI(MBB, MBBI, DL, get(StoreOpcode))
398 .addReg(SrcReg, getKillRegState(isKill)), FrameIdx);
402 SystemZInstrInfo::loadRegFromStackSlot(MachineBasicBlock &MBB,
403 MachineBasicBlock::iterator MBBI,
404 unsigned DestReg, int FrameIdx,
405 const TargetRegisterClass *RC,
406 const TargetRegisterInfo *TRI) const {
407 DebugLoc DL = MBBI != MBB.end() ? MBBI->getDebugLoc() : DebugLoc();
409 // Callers may expect a single instruction, so keep 128-bit moves
410 // together for now and lower them after register allocation.
411 unsigned LoadOpcode, StoreOpcode;
412 getLoadStoreOpcodes(RC, LoadOpcode, StoreOpcode);
413 addFrameReference(BuildMI(MBB, MBBI, DL, get(LoadOpcode), DestReg),
417 // Return true if MI is a simple load or store with a 12-bit displacement
418 // and no index. Flag is SimpleBDXLoad for loads and SimpleBDXStore for stores.
419 static bool isSimpleBD12Move(const MachineInstr *MI, unsigned Flag) {
420 const MCInstrDesc &MCID = MI->getDesc();
421 return ((MCID.TSFlags & Flag) &&
422 isUInt<12>(MI->getOperand(2).getImm()) &&
423 MI->getOperand(3).getReg() == 0);
428 LogicOp() : RegSize(0), ImmLSB(0), ImmSize(0) {}
429 LogicOp(unsigned regSize, unsigned immLSB, unsigned immSize)
430 : RegSize(regSize), ImmLSB(immLSB), ImmSize(immSize) {}
432 operator bool() const { return RegSize; }
434 unsigned RegSize, ImmLSB, ImmSize;
438 static LogicOp interpretAndImmediate(unsigned Opcode) {
440 case SystemZ::NILL32: return LogicOp(32, 0, 16);
441 case SystemZ::NILH32: return LogicOp(32, 16, 16);
442 case SystemZ::NILL: return LogicOp(64, 0, 16);
443 case SystemZ::NILH: return LogicOp(64, 16, 16);
444 case SystemZ::NIHL: return LogicOp(64, 32, 16);
445 case SystemZ::NIHH: return LogicOp(64, 48, 16);
446 case SystemZ::NILF32: return LogicOp(32, 0, 32);
447 case SystemZ::NILF: return LogicOp(64, 0, 32);
448 case SystemZ::NIHF: return LogicOp(64, 32, 32);
449 default: return LogicOp();
453 // Used to return from convertToThreeAddress after replacing two-address
454 // instruction OldMI with three-address instruction NewMI.
455 static MachineInstr *finishConvertToThreeAddress(MachineInstr *OldMI,
459 unsigned NumOps = OldMI->getNumOperands();
460 for (unsigned I = 1; I < NumOps; ++I) {
461 MachineOperand &Op = OldMI->getOperand(I);
462 if (Op.isReg() && Op.isKill())
463 LV->replaceKillInstruction(Op.getReg(), OldMI, NewMI);
470 SystemZInstrInfo::convertToThreeAddress(MachineFunction::iterator &MFI,
471 MachineBasicBlock::iterator &MBBI,
472 LiveVariables *LV) const {
473 MachineInstr *MI = MBBI;
474 MachineBasicBlock *MBB = MI->getParent();
476 unsigned Opcode = MI->getOpcode();
477 unsigned NumOps = MI->getNumOperands();
479 // Try to convert something like SLL into SLLK, if supported.
480 // We prefer to keep the two-operand form where possible both
481 // because it tends to be shorter and because some instructions
482 // have memory forms that can be used during spilling.
483 if (TM.getSubtargetImpl()->hasDistinctOps()) {
484 int ThreeOperandOpcode = SystemZ::getThreeOperandOpcode(Opcode);
485 if (ThreeOperandOpcode >= 0) {
486 MachineOperand &Dest = MI->getOperand(0);
487 MachineOperand &Src = MI->getOperand(1);
488 MachineInstrBuilder MIB =
489 BuildMI(*MBB, MBBI, MI->getDebugLoc(), get(ThreeOperandOpcode))
491 // Keep the kill state, but drop the tied flag.
492 MIB.addReg(Src.getReg(), getKillRegState(Src.isKill()), Src.getSubReg());
493 // Keep the remaining operands as-is.
494 for (unsigned I = 2; I < NumOps; ++I)
495 MIB.addOperand(MI->getOperand(I));
496 return finishConvertToThreeAddress(MI, MIB, LV);
500 // Try to convert an AND into an RISBG-type instruction.
501 if (LogicOp And = interpretAndImmediate(Opcode)) {
503 if (And.RegSize == 64)
504 NewOpcode = SystemZ::RISBG;
505 else if (TM.getSubtargetImpl()->hasHighWord())
506 NewOpcode = SystemZ::RISBLG32;
508 // We can't use RISBG for 32-bit operations because it clobbers the
509 // high word of the destination too.
512 uint64_t Imm = MI->getOperand(2).getImm() << And.ImmLSB;
513 // AND IMMEDIATE leaves the other bits of the register unchanged.
514 Imm |= allOnes(And.RegSize) & ~(allOnes(And.ImmSize) << And.ImmLSB);
516 if (isRxSBGMask(Imm, And.RegSize, Start, End)) {
517 if (NewOpcode == SystemZ::RISBLG32) {
521 MachineOperand &Dest = MI->getOperand(0);
522 MachineOperand &Src = MI->getOperand(1);
523 MachineInstrBuilder MIB =
524 BuildMI(*MBB, MI, MI->getDebugLoc(), get(NewOpcode))
525 .addOperand(Dest).addReg(0)
526 .addReg(Src.getReg(), getKillRegState(Src.isKill()), Src.getSubReg())
527 .addImm(Start).addImm(End + 128).addImm(0);
528 return finishConvertToThreeAddress(MI, MIB, LV);
536 SystemZInstrInfo::foldMemoryOperandImpl(MachineFunction &MF,
538 const SmallVectorImpl<unsigned> &Ops,
539 int FrameIndex) const {
540 const MachineFrameInfo *MFI = MF.getFrameInfo();
541 unsigned Size = MFI->getObjectSize(FrameIndex);
543 // Eary exit for cases we don't care about
547 unsigned OpNum = Ops[0];
548 assert(Size == MF.getRegInfo()
549 .getRegClass(MI->getOperand(OpNum).getReg())->getSize() &&
550 "Invalid size combination");
552 unsigned Opcode = MI->getOpcode();
553 if (Opcode == SystemZ::LGDR || Opcode == SystemZ::LDGR) {
554 bool Op0IsGPR = (Opcode == SystemZ::LGDR);
555 bool Op1IsGPR = (Opcode == SystemZ::LDGR);
556 // If we're spilling the destination of an LDGR or LGDR, store the
557 // source register instead.
559 unsigned StoreOpcode = Op1IsGPR ? SystemZ::STG : SystemZ::STD;
560 return BuildMI(MF, MI->getDebugLoc(), get(StoreOpcode))
561 .addOperand(MI->getOperand(1)).addFrameIndex(FrameIndex)
562 .addImm(0).addReg(0);
564 // If we're spilling the source of an LDGR or LGDR, load the
565 // destination register instead.
567 unsigned LoadOpcode = Op0IsGPR ? SystemZ::LG : SystemZ::LD;
568 unsigned Dest = MI->getOperand(0).getReg();
569 return BuildMI(MF, MI->getDebugLoc(), get(LoadOpcode), Dest)
570 .addFrameIndex(FrameIndex).addImm(0).addReg(0);
574 // Look for cases where the source of a simple store or the destination
575 // of a simple load is being spilled. Try to use MVC instead.
577 // Although MVC is in practice a fast choice in these cases, it is still
578 // logically a bytewise copy. This means that we cannot use it if the
579 // load or store is volatile. It also means that the transformation is
580 // not valid in cases where the two memories partially overlap; however,
581 // that is not a problem here, because we know that one of the memories
582 // is a full frame index.
583 if (OpNum == 0 && MI->hasOneMemOperand()) {
584 MachineMemOperand *MMO = *MI->memoperands_begin();
585 if (MMO->getSize() == Size && !MMO->isVolatile()) {
586 // Handle conversion of loads.
587 if (isSimpleBD12Move(MI, SystemZII::SimpleBDXLoad)) {
588 return BuildMI(MF, MI->getDebugLoc(), get(SystemZ::MVC))
589 .addFrameIndex(FrameIndex).addImm(0).addImm(Size)
590 .addOperand(MI->getOperand(1)).addImm(MI->getOperand(2).getImm())
593 // Handle conversion of stores.
594 if (isSimpleBD12Move(MI, SystemZII::SimpleBDXStore)) {
595 return BuildMI(MF, MI->getDebugLoc(), get(SystemZ::MVC))
596 .addOperand(MI->getOperand(1)).addImm(MI->getOperand(2).getImm())
597 .addImm(Size).addFrameIndex(FrameIndex).addImm(0)
603 // If the spilled operand is the final one, try to change <INSN>R
605 int MemOpcode = SystemZ::getMemOpcode(Opcode);
606 if (MemOpcode >= 0) {
607 unsigned NumOps = MI->getNumExplicitOperands();
608 if (OpNum == NumOps - 1) {
609 const MCInstrDesc &MemDesc = get(MemOpcode);
610 uint64_t AccessBytes = SystemZII::getAccessSize(MemDesc.TSFlags);
611 assert(AccessBytes != 0 && "Size of access should be known");
612 assert(AccessBytes <= Size && "Access outside the frame index");
613 uint64_t Offset = Size - AccessBytes;
614 MachineInstrBuilder MIB = BuildMI(MF, MI->getDebugLoc(), get(MemOpcode));
615 for (unsigned I = 0; I < OpNum; ++I)
616 MIB.addOperand(MI->getOperand(I));
617 MIB.addFrameIndex(FrameIndex).addImm(Offset);
618 if (MemDesc.TSFlags & SystemZII::HasIndex)
628 SystemZInstrInfo::foldMemoryOperandImpl(MachineFunction &MF, MachineInstr* MI,
629 const SmallVectorImpl<unsigned> &Ops,
630 MachineInstr* LoadMI) const {
635 SystemZInstrInfo::expandPostRAPseudo(MachineBasicBlock::iterator MI) const {
636 switch (MI->getOpcode()) {
638 splitMove(MI, SystemZ::LG);
642 splitMove(MI, SystemZ::STG);
646 splitMove(MI, SystemZ::LD);
650 splitMove(MI, SystemZ::STD);
653 case SystemZ::ADJDYNALLOC:
654 splitAdjDynAlloc(MI);
662 uint64_t SystemZInstrInfo::getInstSizeInBytes(const MachineInstr *MI) const {
663 if (MI->getOpcode() == TargetOpcode::INLINEASM) {
664 const MachineFunction *MF = MI->getParent()->getParent();
665 const char *AsmStr = MI->getOperand(0).getSymbolName();
666 return getInlineAsmLength(AsmStr, *MF->getTarget().getMCAsmInfo());
668 return MI->getDesc().getSize();
672 SystemZInstrInfo::getBranchInfo(const MachineInstr *MI) const {
673 switch (MI->getOpcode()) {
677 return SystemZII::Branch(SystemZII::BranchNormal, SystemZ::CCMASK_ANY,
678 SystemZ::CCMASK_ANY, &MI->getOperand(0));
682 return SystemZII::Branch(SystemZII::BranchNormal,
683 MI->getOperand(0).getImm(),
684 MI->getOperand(1).getImm(), &MI->getOperand(2));
688 return SystemZII::Branch(SystemZII::BranchC, SystemZ::CCMASK_ICMP,
689 MI->getOperand(2).getImm(), &MI->getOperand(3));
693 return SystemZII::Branch(SystemZII::BranchCG, SystemZ::CCMASK_ICMP,
694 MI->getOperand(2).getImm(), &MI->getOperand(3));
697 llvm_unreachable("Unrecognized branch opcode");
701 void SystemZInstrInfo::getLoadStoreOpcodes(const TargetRegisterClass *RC,
702 unsigned &LoadOpcode,
703 unsigned &StoreOpcode) const {
704 if (RC == &SystemZ::GR32BitRegClass || RC == &SystemZ::ADDR32BitRegClass) {
705 LoadOpcode = SystemZ::L;
706 StoreOpcode = SystemZ::ST32;
707 } else if (RC == &SystemZ::GR64BitRegClass ||
708 RC == &SystemZ::ADDR64BitRegClass) {
709 LoadOpcode = SystemZ::LG;
710 StoreOpcode = SystemZ::STG;
711 } else if (RC == &SystemZ::GR128BitRegClass ||
712 RC == &SystemZ::ADDR128BitRegClass) {
713 LoadOpcode = SystemZ::L128;
714 StoreOpcode = SystemZ::ST128;
715 } else if (RC == &SystemZ::FP32BitRegClass) {
716 LoadOpcode = SystemZ::LE;
717 StoreOpcode = SystemZ::STE;
718 } else if (RC == &SystemZ::FP64BitRegClass) {
719 LoadOpcode = SystemZ::LD;
720 StoreOpcode = SystemZ::STD;
721 } else if (RC == &SystemZ::FP128BitRegClass) {
722 LoadOpcode = SystemZ::LX;
723 StoreOpcode = SystemZ::STX;
725 llvm_unreachable("Unsupported regclass to load or store");
728 unsigned SystemZInstrInfo::getOpcodeForOffset(unsigned Opcode,
729 int64_t Offset) const {
730 const MCInstrDesc &MCID = get(Opcode);
731 int64_t Offset2 = (MCID.TSFlags & SystemZII::Is128Bit ? Offset + 8 : Offset);
732 if (isUInt<12>(Offset) && isUInt<12>(Offset2)) {
733 // Get the instruction to use for unsigned 12-bit displacements.
734 int Disp12Opcode = SystemZ::getDisp12Opcode(Opcode);
735 if (Disp12Opcode >= 0)
738 // All address-related instructions can use unsigned 12-bit
742 if (isInt<20>(Offset) && isInt<20>(Offset2)) {
743 // Get the instruction to use for signed 20-bit displacements.
744 int Disp20Opcode = SystemZ::getDisp20Opcode(Opcode);
745 if (Disp20Opcode >= 0)
748 // Check whether Opcode allows signed 20-bit displacements.
749 if (MCID.TSFlags & SystemZII::Has20BitOffset)
755 // Return true if Mask matches the regexp 0*1+0*, given that zero masks
756 // have already been filtered out. Store the first set bit in LSB and
757 // the number of set bits in Length if so.
758 static bool isStringOfOnes(uint64_t Mask, unsigned &LSB, unsigned &Length) {
759 unsigned First = findFirstSet(Mask);
760 uint64_t Top = (Mask >> First) + 1;
761 if ((Top & -Top) == Top) {
763 Length = findFirstSet(Top);
769 bool SystemZInstrInfo::isRxSBGMask(uint64_t Mask, unsigned BitSize,
770 unsigned &Start, unsigned &End) const {
771 // Reject trivial all-zero masks.
775 // Handle the 1+0+ or 0+1+0* cases. Start then specifies the index of
776 // the msb and End specifies the index of the lsb.
777 unsigned LSB, Length;
778 if (isStringOfOnes(Mask, LSB, Length)) {
779 Start = 63 - (LSB + Length - 1);
784 // Handle the wrap-around 1+0+1+ cases. Start then specifies the msb
785 // of the low 1s and End specifies the lsb of the high 1s.
786 if (isStringOfOnes(Mask ^ allOnes(BitSize), LSB, Length)) {
787 assert(LSB > 0 && "Bottom bit must be set");
788 assert(LSB + Length < BitSize && "Top bit must be set");
789 Start = 63 - (LSB - 1);
790 End = 63 - (LSB + Length);
797 unsigned SystemZInstrInfo::getCompareAndBranch(unsigned Opcode,
798 const MachineInstr *MI) const {
803 return SystemZ::CGRJ;
805 return MI && isInt<8>(MI->getOperand(1).getImm()) ? SystemZ::CIJ : 0;
807 return MI && isInt<8>(MI->getOperand(1).getImm()) ? SystemZ::CGIJ : 0;
813 void SystemZInstrInfo::loadImmediate(MachineBasicBlock &MBB,
814 MachineBasicBlock::iterator MBBI,
815 unsigned Reg, uint64_t Value) const {
816 DebugLoc DL = MBBI != MBB.end() ? MBBI->getDebugLoc() : DebugLoc();
818 if (isInt<16>(Value))
819 Opcode = SystemZ::LGHI;
820 else if (SystemZ::isImmLL(Value))
821 Opcode = SystemZ::LLILL;
822 else if (SystemZ::isImmLH(Value)) {
823 Opcode = SystemZ::LLILH;
826 assert(isInt<32>(Value) && "Huge values not handled yet");
827 Opcode = SystemZ::LGFI;
829 BuildMI(MBB, MBBI, DL, get(Opcode), Reg).addImm(Value);