lib/Target/SystemZ/SystemZInstrFP.td

   1 //===- SystemZInstrFP.td - SystemZ FP Instruction defs --------*- tblgen-*-===//
   2 //
   3 //                     The LLVM Compiler Infrastructure
   4 //
   5 // This file is distributed under the University of Illinois Open Source
   6 // License. See LICENSE.TXT for details.
   7 //
   8 //===----------------------------------------------------------------------===//
   9 //
  10 // This file describes the SystemZ (binary) floating point instructions in
  11 // TableGen format.
  12 //
  13 //===----------------------------------------------------------------------===//
  14
  15 // FIXME: multiclassify!
  16
  17 //===----------------------------------------------------------------------===//
  18 // Move Instructions
  19
  20 let neverHasSideEffects = 1 in {
  21 def FMOV32rr : Pseudo<(outs FP32:$dst), (ins FP32:$src),
  22                       "ler\t{$dst, $src}",
  23                       []>;
  24 def FMOV64rr : Pseudo<(outs FP64:$dst), (ins FP64:$src),
  25                       "ldr\t{$dst, $src}",
  26                       []>;
  27 }
  28
  29 let canFoldAsLoad = 1, isReMaterializable = 1, mayHaveSideEffects = 1 in {
  30 def FMOV32rm  : Pseudo<(outs FP32:$dst), (ins rriaddr12:$src),
  31                       "le\t{$dst, $src}",
  32                       [(set FP32:$dst, (load rriaddr12:$src))]>;
  33 def FMOV32rmy : Pseudo<(outs FP32:$dst), (ins rriaddr:$src),
  34                       "ley\t{$dst, $src}",
  35                       [(set FP32:$dst, (load rriaddr:$src))]>;
  36 def FMOV64rm  : Pseudo<(outs FP64:$dst), (ins rriaddr12:$src),
  37                       "ld\t{$dst, $src}",
  38                       [(set FP64:$dst, (load rriaddr12:$src))]>;
  39 def FMOV64rmy : Pseudo<(outs FP64:$dst), (ins rriaddr:$src),
  40                       "ldy\t{$dst, $src}",
  41                       [(set FP64:$dst, (load rriaddr:$src))]>;
  42 }
  43
  44 def FMOV32mr  : Pseudo<(outs), (ins rriaddr12:$dst, FP32:$src),
  45                        "ste\t{$src, $dst}",
  46                        [(store FP32:$src, rriaddr12:$dst)]>;
  47 def FMOV32mry : Pseudo<(outs), (ins rriaddr:$dst, FP32:$src),
  48                        "stey\t{$src, $dst}",
  49                        [(store FP32:$src, rriaddr:$dst)]>;
  50 def FMOV64mr  : Pseudo<(outs), (ins rriaddr12:$dst, FP64:$src),
  51                        "std\t{$src, $dst}",
  52                        [(store FP64:$src, rriaddr12:$dst)]>;
  53 def FMOV64mry : Pseudo<(outs), (ins rriaddr:$dst, FP64:$src),
  54                        "stdy\t{$src, $dst}",
  55                        [(store FP64:$src, rriaddr:$dst)]>;
  56
  57 //===----------------------------------------------------------------------===//
  58 // Arithmetic Instructions
  59
  60
  61
  62 let isTwoAddress = 1 in {
  63 def FNEG32rr : Pseudo<(outs FP32:$dst), (ins FP32:$src),
  64                        "lcebr\t{$dst}",
  65                        [(set FP32:$dst, (fneg FP32:$src))]>;
  66 def FNEG64rr : Pseudo<(outs FP64:$dst), (ins FP64:$src),
  67                        "lcdbr\t{$dst}",
  68                        [(set FP64:$dst, (fneg FP64:$src))]>;
  69
  70 // FIXME: Add peephole for fneg(fabs) => load negative
  71
  72 def FABS32rr : Pseudo<(outs FP32:$dst), (ins FP32:$src),
  73                        "lpebr\t{$dst}",
  74                        [(set FP32:$dst, (fabs FP32:$src))]>;
  75 def FABS64rr : Pseudo<(outs FP64:$dst), (ins FP64:$src),
  76                        "lpdbr\t{$dst}",
  77                        [(set FP64:$dst, (fabs FP64:$src))]>;
  78
  79 let isCommutable = 1 in { // X = ADD Y, Z  == X = ADD Z, Y
  80 def FADD32rr : Pseudo<(outs FP32:$dst), (ins FP32:$src1, FP32:$src2),
  81                        "aebr\t{$dst, $src2}",
  82                        [(set FP32:$dst, (fadd FP32:$src1, FP32:$src2))]>;
  83 def FADD64rr : Pseudo<(outs FP64:$dst), (ins FP64:$src1, FP64:$src2),
  84                        "adbr\t{$dst, $src2}",
  85                        [(set FP64:$dst, (fadd FP64:$src1, FP64:$src2))]>;
  86 }
  87
  88 def FADD32rm : Pseudo<(outs FP32:$dst), (ins FP32:$src1, rriaddr:$src2),
  89                        "aeb\t{$dst, $src2}",
  90                        [(set FP32:$dst, (fadd FP32:$src1, (load rriaddr:$src2)))]>;
  91 def FADD64rm : Pseudo<(outs FP64:$dst), (ins FP64:$src1, rriaddr:$src2),
  92                        "adb\t{$dst, $src2}",
  93                        [(set FP64:$dst, (fadd FP64:$src1, (load rriaddr:$src2)))]>;
  94
  95 def FSUB32rr : Pseudo<(outs FP32:$dst), (ins FP32:$src1, FP32:$src2),
  96                        "sebr\t{$dst, $src2}",
  97                        [(set FP32:$dst, (fsub FP32:$src1, FP32:$src2))]>;
  98 def FSUB64rr : Pseudo<(outs FP64:$dst), (ins FP64:$src1, FP64:$src2),
  99                        "sdbr\t{$dst, $src2}",
 100                        [(set FP64:$dst, (fsub FP64:$src1, FP64:$src2))]>;
 101
 102 def FSUB32rm : Pseudo<(outs FP32:$dst), (ins FP32:$src1, rriaddr:$src2),
 103                        "seb\t{$dst, $src2}",
 104                        [(set FP32:$dst, (fsub FP32:$src1, (load rriaddr:$src2)))]>;
 105 def FSUB64rm : Pseudo<(outs FP64:$dst), (ins FP64:$src1, rriaddr:$src2),
 106                        "sdb\t{$dst, $src2}",
 107                        [(set FP64:$dst, (fsub FP64:$src1, (load rriaddr:$src2)))]>;
 108
 109 let isCommutable = 1 in { // X = MUL Y, Z  == X = MUL Z, Y
 110 def FMUL32rr : Pseudo<(outs FP32:$dst), (ins FP32:$src1, FP32:$src2),
 111                        "meebr\t{$dst, $src2}",
 112                        [(set FP32:$dst, (fmul FP32:$src1, FP32:$src2))]>;
 113 def FMUL64rr : Pseudo<(outs FP64:$dst), (ins FP64:$src1, FP64:$src2),
 114                        "mdbr\t{$dst, $src2}",
 115                        [(set FP64:$dst, (fmul FP64:$src1, FP64:$src2))]>;
 116 }
 117
 118 def FMUL32rm : Pseudo<(outs FP32:$dst), (ins FP32:$src1, rriaddr:$src2),
 119                        "meeb\t{$dst, $src2}",
 120                        [(set FP32:$dst, (fmul FP32:$src1, (load rriaddr:$src2)))]>;
 121 def FMUL64rm : Pseudo<(outs FP64:$dst), (ins FP64:$src1, rriaddr:$src2),
 122                        "mdb\t{$dst, $src2}",
 123                        [(set FP64:$dst, (fmul FP64:$src1, (load rriaddr:$src2)))]>;
 124
 125 def FDIV32rr : Pseudo<(outs FP32:$dst), (ins FP32:$src1, FP32:$src2),
 126                        "debr\t{$dst, $src2}",
 127                        [(set FP32:$dst, (fdiv FP32:$src1, FP32:$src2))]>;
 128 def FDIV64rr : Pseudo<(outs FP64:$dst), (ins FP64:$src1, FP64:$src2),
 129                        "ddbr\t{$dst, $src2}",
 130                        [(set FP64:$dst, (fdiv FP64:$src1, FP64:$src2))]>;
 131
 132 def FDIV32rm : Pseudo<(outs FP32:$dst), (ins FP32:$src1, rriaddr:$src2),
 133                        "deb\t{$dst, $src2}",
 134                        [(set FP32:$dst, (fdiv FP32:$src1, (load rriaddr:$src2)))]>;
 135 def FDIV64rm : Pseudo<(outs FP64:$dst), (ins FP64:$src1, rriaddr:$src2),
 136                        "ddb\t{$dst, $src2}",
 137                        [(set FP64:$dst, (fdiv FP64:$src1, (load rriaddr:$src2)))]>;
 138
 139 } // isTwoAddress = 1
 140
 141 def FROUND64r32 : Pseudo<(outs FP32:$dst), (ins FP64:$src),
 142                          "ledbr\t{$dst, $src}",
 143                          [(set FP32:$dst, (fround FP64:$src))]>;
 144
 145 def FCONVFP32   : Pseudo<(outs FP32:$dst), (ins GR32:$src),
 146                          "cefbr\t{$dst, $src}",
 147                          [(set FP32:$dst, (sint_to_fp GR32:$src))]>;
 148 def FCONVFP32r64: Pseudo<(outs FP32:$dst), (ins GR64:$src),
 149                          "cegbr\t{$dst, $src}",
 150                          [(set FP32:$dst, (sint_to_fp GR64:$src))]>;
 151
 152 def FCONVFP64r32: Pseudo<(outs FP64:$dst), (ins GR32:$src),
 153                          "cdfbr\t{$dst, $src}",
 154                          [(set FP64:$dst, (sint_to_fp GR32:$src))]>;
 155
 156 def FCONVFP64   : Pseudo<(outs FP64:$dst), (ins GR64:$src),
 157                          "cdgbr\t{$dst, $src}",
 158                          [(set FP64:$dst, (sint_to_fp GR64:$src))]>;
 159
 160 //===----------------------------------------------------------------------===//
 161 // Test instructions (like AND but do not produce any result)
 162
 163 // Integer comparisons
 164 let Defs = [PSW] in {
 165 def FCMP32rr : Pseudo<(outs), (ins FP32:$src1, FP32:$src2),
 166                       "cebr\t$src1, $src2",
 167                       [(SystemZcmp FP32:$src1, FP32:$src2), (implicit PSW)]>;
 168 def FCMP64rr : Pseudo<(outs), (ins FP64:$src1, FP64:$src2),
 169                       "cdbr\t$src1, $src2",
 170                       [(SystemZcmp FP64:$src1, FP64:$src2), (implicit PSW)]>;
 171
 172 def FCMP32rm : Pseudo<(outs), (ins FP32:$src1, rriaddr:$src2),
 173                       "ceb\t$src1, $src2",
 174                       [(SystemZcmp FP32:$src1, (load rriaddr:$src2)),
 175                        (implicit PSW)]>;
 176 def FCMP64rm : Pseudo<(outs), (ins FP64:$src1, rriaddr:$src2),
 177                       "cdb\t$src1, $src2",
 178                       [(SystemZcmp FP64:$src1, (load rriaddr:$src2)),
 179                        (implicit PSW)]>;
 180 } // Defs = [PSW]