lib/Target/SystemZ/SystemZInstrFP.td

   1 //===- SystemZInstrFP.td - SystemZ FP Instruction defs --------*- tblgen-*-===//
   2 //
   3 //                     The LLVM Compiler Infrastructure
   4 //
   5 // This file is distributed under the University of Illinois Open Source
   6 // License. See LICENSE.TXT for details.
   7 //
   8 //===----------------------------------------------------------------------===//
   9 //
  10 // This file describes the SystemZ (binary) floating point instructions in
  11 // TableGen format.
  12 //
  13 //===----------------------------------------------------------------------===//
  14
  15 // FIXME: multiclassify!
  16
  17 let usesCustomDAGSchedInserter = 1 in {
  18   def SelectF32 : Pseudo<(outs FP32:$dst), (ins FP32:$src1, FP32:$src2, i8imm:$cc),
  19                         "# SelectF32 PSEUDO",
  20                         [(set FP32:$dst,
  21                               (SystemZselect FP32:$src1, FP32:$src2, imm:$cc))]>;
  22   def SelectF64 : Pseudo<(outs FP64:$dst), (ins FP64:$src1, FP64:$src2, i8imm:$cc),
  23                         "# SelectF64 PSEUDO",
  24                         [(set FP64:$dst,
  25                               (SystemZselect FP64:$src1, FP64:$src2, imm:$cc))]>;
  26 }
  27
  28 //===----------------------------------------------------------------------===//
  29 // Move Instructions
  30
  31 let neverHasSideEffects = 1 in {
  32 def FMOV32rr : Pseudo<(outs FP32:$dst), (ins FP32:$src),
  33                       "ler\t{$dst, $src}",
  34                       []>;
  35 def FMOV64rr : Pseudo<(outs FP64:$dst), (ins FP64:$src),
  36                       "ldr\t{$dst, $src}",
  37                       []>;
  38 }
  39
  40 let canFoldAsLoad = 1, isReMaterializable = 1, mayHaveSideEffects = 1 in {
  41 def FMOV32rm  : Pseudo<(outs FP32:$dst), (ins rriaddr12:$src),
  42                       "le\t{$dst, $src}",
  43                       [(set FP32:$dst, (load rriaddr12:$src))]>;
  44 def FMOV32rmy : Pseudo<(outs FP32:$dst), (ins rriaddr:$src),
  45                       "ley\t{$dst, $src}",
  46                       [(set FP32:$dst, (load rriaddr:$src))]>;
  47 def FMOV64rm  : Pseudo<(outs FP64:$dst), (ins rriaddr12:$src),
  48                       "ld\t{$dst, $src}",
  49                       [(set FP64:$dst, (load rriaddr12:$src))]>;
  50 def FMOV64rmy : Pseudo<(outs FP64:$dst), (ins rriaddr:$src),
  51                       "ldy\t{$dst, $src}",
  52                       [(set FP64:$dst, (load rriaddr:$src))]>;
  53 }
  54
  55 def FMOV32mr  : Pseudo<(outs), (ins rriaddr12:$dst, FP32:$src),
  56                        "ste\t{$src, $dst}",
  57                        [(store FP32:$src, rriaddr12:$dst)]>;
  58 def FMOV32mry : Pseudo<(outs), (ins rriaddr:$dst, FP32:$src),
  59                        "stey\t{$src, $dst}",
  60                        [(store FP32:$src, rriaddr:$dst)]>;
  61 def FMOV64mr  : Pseudo<(outs), (ins rriaddr12:$dst, FP64:$src),
  62                        "std\t{$src, $dst}",
  63                        [(store FP64:$src, rriaddr12:$dst)]>;
  64 def FMOV64mry : Pseudo<(outs), (ins rriaddr:$dst, FP64:$src),
  65                        "stdy\t{$src, $dst}",
  66                        [(store FP64:$src, rriaddr:$dst)]>;
  67
  68 //===----------------------------------------------------------------------===//
  69 // Arithmetic Instructions
  70
  71
  72 let Defs = [PSW] in {
  73 def FNEG32rr : Pseudo<(outs FP32:$dst), (ins FP32:$src),
  74                        "lcebr\t{$dst, $src}",
  75                        [(set FP32:$dst, (fneg FP32:$src)),
  76                         (implicit PSW)]>;
  77 def FNEG64rr : Pseudo<(outs FP64:$dst), (ins FP64:$src),
  78                        "lcdbr\t{$dst, $src}",
  79                        [(set FP64:$dst, (fneg FP64:$src)),
  80                         (implicit PSW)]>;
  81 }
  82
  83 let isTwoAddress = 1 in {
  84 let Defs = [PSW] in {
  85
  86 def FABS32rr : Pseudo<(outs FP32:$dst), (ins FP32:$src),
  87                        "lpebr\t{$dst}",
  88                        [(set FP32:$dst, (fabs FP32:$src)),
  89                         (implicit PSW)]>;
  90 def FABS64rr : Pseudo<(outs FP64:$dst), (ins FP64:$src),
  91                        "lpdbr\t{$dst}",
  92                        [(set FP64:$dst, (fabs FP64:$src)),
  93                         (implicit PSW)]>;
  94
  95 def FNABS32rr : Pseudo<(outs FP32:$dst), (ins FP32:$src),
  96                        "lnebr\t{$dst}",
  97                        [(set FP32:$dst, (fneg(fabs FP32:$src))),
  98                         (implicit PSW)]>;
  99 def FNABS64rr : Pseudo<(outs FP64:$dst), (ins FP64:$src),
 100                        "lndbr\t{$dst}",
 101                        [(set FP64:$dst, (fneg(fabs FP64:$src))),
 102                         (implicit PSW)]>;
 103
 104 let isCommutable = 1 in { // X = ADD Y, Z  == X = ADD Z, Y
 105 def FADD32rr : Pseudo<(outs FP32:$dst), (ins FP32:$src1, FP32:$src2),
 106                        "aebr\t{$dst, $src2}",
 107                        [(set FP32:$dst, (fadd FP32:$src1, FP32:$src2)),
 108                         (implicit PSW)]>;
 109 def FADD64rr : Pseudo<(outs FP64:$dst), (ins FP64:$src1, FP64:$src2),
 110                        "adbr\t{$dst, $src2}",
 111                        [(set FP64:$dst, (fadd FP64:$src1, FP64:$src2)),
 112                         (implicit PSW)]>;
 113 }
 114
 115 def FADD32rm : Pseudo<(outs FP32:$dst), (ins FP32:$src1, rriaddr:$src2),
 116                        "aeb\t{$dst, $src2}",
 117                        [(set FP32:$dst, (fadd FP32:$src1, (load rriaddr:$src2))),
 118                         (implicit PSW)]>;
 119 def FADD64rm : Pseudo<(outs FP64:$dst), (ins FP64:$src1, rriaddr:$src2),
 120                        "adb\t{$dst, $src2}",
 121                        [(set FP64:$dst, (fadd FP64:$src1, (load rriaddr:$src2))),
 122                         (implicit PSW)]>;
 123
 124 def FSUB32rr : Pseudo<(outs FP32:$dst), (ins FP32:$src1, FP32:$src2),
 125                        "sebr\t{$dst, $src2}",
 126                        [(set FP32:$dst, (fsub FP32:$src1, FP32:$src2)),
 127                         (implicit PSW)]>;
 128 def FSUB64rr : Pseudo<(outs FP64:$dst), (ins FP64:$src1, FP64:$src2),
 129                        "sdbr\t{$dst, $src2}",
 130                        [(set FP64:$dst, (fsub FP64:$src1, FP64:$src2)),
 131                         (implicit PSW)]>;
 132
 133 def FSUB32rm : Pseudo<(outs FP32:$dst), (ins FP32:$src1, rriaddr:$src2),
 134                        "seb\t{$dst, $src2}",
 135                        [(set FP32:$dst, (fsub FP32:$src1, (load rriaddr:$src2))),
 136                         (implicit PSW)]>;
 137 def FSUB64rm : Pseudo<(outs FP64:$dst), (ins FP64:$src1, rriaddr:$src2),
 138                        "sdb\t{$dst, $src2}",
 139                        [(set FP64:$dst, (fsub FP64:$src1, (load rriaddr:$src2))),
 140                         (implicit PSW)]>;
 141 } // Defs = [PSW]
 142
 143 let isCommutable = 1 in { // X = MUL Y, Z  == X = MUL Z, Y
 144 def FMUL32rr : Pseudo<(outs FP32:$dst), (ins FP32:$src1, FP32:$src2),
 145                        "meebr\t{$dst, $src2}",
 146                        [(set FP32:$dst, (fmul FP32:$src1, FP32:$src2))]>;
 147 def FMUL64rr : Pseudo<(outs FP64:$dst), (ins FP64:$src1, FP64:$src2),
 148                        "mdbr\t{$dst, $src2}",
 149                        [(set FP64:$dst, (fmul FP64:$src1, FP64:$src2))]>;
 150 }
 151
 152 def FMUL32rm : Pseudo<(outs FP32:$dst), (ins FP32:$src1, rriaddr:$src2),
 153                        "meeb\t{$dst, $src2}",
 154                        [(set FP32:$dst, (fmul FP32:$src1, (load rriaddr:$src2)))]>;
 155 def FMUL64rm : Pseudo<(outs FP64:$dst), (ins FP64:$src1, rriaddr:$src2),
 156                        "mdb\t{$dst, $src2}",
 157                        [(set FP64:$dst, (fmul FP64:$src1, (load rriaddr:$src2)))]>;
 158
 159 def FMADD32rr : Pseudo<(outs FP32:$dst), (ins FP32:$src1, FP32:$src2, FP32:$src3),
 160                        "maebr\t{$dst, $src3, $src2}",
 161                        [(set FP32:$dst, (fadd (fmul FP32:$src2, FP32:$src3),
 162                                               FP32:$src1))]>;
 163 def FMADD32rm : Pseudo<(outs FP32:$dst), (ins FP32:$src1, rriaddr:$src2, FP32:$src3),
 164                        "maeb\t{$dst, $src3, $src2}",
 165                        [(set FP32:$dst, (fadd (fmul (load rriaddr:$src2),
 166                                                      FP32:$src3),
 167                                               FP32:$src1))]>;
 168
 169 def FMADD64rr : Pseudo<(outs FP64:$dst), (ins FP64:$src1, FP64:$src2, FP64:$src3),
 170                        "madbr\t{$dst, $src3, $src2}",
 171                        [(set FP64:$dst, (fadd (fmul FP64:$src2, FP64:$src3),
 172                                               FP64:$src1))]>;
 173 def FMADD64rm : Pseudo<(outs FP64:$dst), (ins FP64:$src1, rriaddr:$src2, FP64:$src3),
 174                        "madb\t{$dst, $src3, $src2}",
 175                        [(set FP64:$dst, (fadd (fmul (load rriaddr:$src2),
 176                                                      FP64:$src3),
 177                                               FP64:$src1))]>;
 178
 179 def FMSUB32rr : Pseudo<(outs FP32:$dst), (ins FP32:$src1, FP32:$src2, FP32:$src3),
 180                        "msebr\t{$dst, $src3, $src2}",
 181                        [(set FP32:$dst, (fsub (fmul FP32:$src2, FP32:$src3),
 182                                               FP32:$src1))]>;
 183 def FMSUB32rm : Pseudo<(outs FP32:$dst), (ins FP32:$src1, rriaddr:$src2, FP32:$src3),
 184                        "mseb\t{$dst, $src3, $src2}",
 185                        [(set FP32:$dst, (fsub (fmul (load rriaddr:$src2),
 186                                                      FP32:$src3),
 187                                               FP32:$src1))]>;
 188
 189 def FMSUB64rr : Pseudo<(outs FP64:$dst), (ins FP64:$src1, FP64:$src2, FP64:$src3),
 190                        "msdbr\t{$dst, $src3, $src2}",
 191                        [(set FP64:$dst, (fsub (fmul FP64:$src2, FP64:$src3),
 192                                               FP64:$src1))]>;
 193 def FMSUB64rm : Pseudo<(outs FP64:$dst), (ins FP64:$src1, rriaddr:$src2, FP64:$src3),
 194                        "msdb\t{$dst, $src3, $src2}",
 195                        [(set FP64:$dst, (fsub (fmul (load rriaddr:$src2),
 196                                                      FP64:$src3),
 197                                               FP64:$src1))]>;
 198
 199 def FDIV32rr : Pseudo<(outs FP32:$dst), (ins FP32:$src1, FP32:$src2),
 200                        "debr\t{$dst, $src2}",
 201                        [(set FP32:$dst, (fdiv FP32:$src1, FP32:$src2))]>;
 202 def FDIV64rr : Pseudo<(outs FP64:$dst), (ins FP64:$src1, FP64:$src2),
 203                        "ddbr\t{$dst, $src2}",
 204                        [(set FP64:$dst, (fdiv FP64:$src1, FP64:$src2))]>;
 205
 206 def FDIV32rm : Pseudo<(outs FP32:$dst), (ins FP32:$src1, rriaddr:$src2),
 207                        "deb\t{$dst, $src2}",
 208                        [(set FP32:$dst, (fdiv FP32:$src1, (load rriaddr:$src2)))]>;
 209 def FDIV64rm : Pseudo<(outs FP64:$dst), (ins FP64:$src1, rriaddr:$src2),
 210                        "ddb\t{$dst, $src2}",
 211                        [(set FP64:$dst, (fdiv FP64:$src1, (load rriaddr:$src2)))]>;
 212
 213 } // isTwoAddress = 1
 214
 215 def FROUND64r32 : Pseudo<(outs FP32:$dst), (ins FP64:$src),
 216                          "ledbr\t{$dst, $src}",
 217                          [(set FP32:$dst, (fround FP64:$src))]>;
 218
 219 def FEXT32r64   : Pseudo<(outs FP64:$dst), (ins FP32:$src),
 220                          "ldebr\t{$dst, $src}",
 221                          [(set FP64:$dst, (fextend FP32:$src))]>;
 222 def FEXT32m64   : Pseudo<(outs FP64:$dst), (ins rriaddr:$src),
 223                          "ldeb\t{$dst, $src}",
 224                          [(set FP64:$dst, (fextend (load rriaddr:$src)))]>;
 225
 226 let Defs = [PSW] in {
 227 def FCONVFP32   : Pseudo<(outs FP32:$dst), (ins GR32:$src),
 228                          "cefbr\t{$dst, $src}",
 229                          [(set FP32:$dst, (sint_to_fp GR32:$src)),
 230                           (implicit PSW)]>;
 231 def FCONVFP32r64: Pseudo<(outs FP32:$dst), (ins GR64:$src),
 232                          "cegbr\t{$dst, $src}",
 233                          [(set FP32:$dst, (sint_to_fp GR64:$src)),
 234                           (implicit PSW)]>;
 235
 236 def FCONVFP64r32: Pseudo<(outs FP64:$dst), (ins GR32:$src),
 237                          "cdfbr\t{$dst, $src}",
 238                          [(set FP64:$dst, (sint_to_fp GR32:$src)),
 239                           (implicit PSW)]>;
 240 def FCONVFP64   : Pseudo<(outs FP64:$dst), (ins GR64:$src),
 241                          "cdgbr\t{$dst, $src}",
 242                          [(set FP64:$dst, (sint_to_fp GR64:$src)),
 243                           (implicit PSW)]>;
 244
 245 def FCONVGR32   : Pseudo<(outs GR32:$dst), (ins FP32:$src),
 246                          "cfebr\t{$dst, $src}",
 247                          [(set GR32:$dst, (fp_to_sint FP32:$src)),
 248                           (implicit PSW)]>;
 249 def FCONVGR32r64: Pseudo<(outs GR32:$dst), (ins FP64:$src),
 250                          "cgebr\t{$dst, $src}",
 251                          [(set GR32:$dst, (fp_to_sint FP64:$src)),
 252                           (implicit PSW)]>;
 253
 254 def FCONVGR64r32: Pseudo<(outs GR64:$dst), (ins FP32:$src),
 255                          "cfdbr\t{$dst, $src}",
 256                          [(set GR64:$dst, (fp_to_sint FP32:$src)),
 257                           (implicit PSW)]>;
 258 def FCONVGR64   : Pseudo<(outs GR64:$dst), (ins FP64:$src),
 259                          "cgdbr\t{$dst, $src}",
 260                          [(set GR64:$dst, (fp_to_sint FP64:$src)),
 261                           (implicit PSW)]>;
 262 } // Defs = [PSW]
 263
 264 //===----------------------------------------------------------------------===//
 265 // Test instructions (like AND but do not produce any result)
 266
 267 // Integer comparisons
 268 let Defs = [PSW] in {
 269 def FCMP32rr : Pseudo<(outs), (ins FP32:$src1, FP32:$src2),
 270                       "cebr\t$src1, $src2",
 271                       [(SystemZcmp FP32:$src1, FP32:$src2), (implicit PSW)]>;
 272 def FCMP64rr : Pseudo<(outs), (ins FP64:$src1, FP64:$src2),
 273                       "cdbr\t$src1, $src2",
 274                       [(SystemZcmp FP64:$src1, FP64:$src2), (implicit PSW)]>;
 275
 276 def FCMP32rm : Pseudo<(outs), (ins FP32:$src1, rriaddr:$src2),
 277                       "ceb\t$src1, $src2",
 278                       [(SystemZcmp FP32:$src1, (load rriaddr:$src2)),
 279                        (implicit PSW)]>;
 280 def FCMP64rm : Pseudo<(outs), (ins FP64:$src1, rriaddr:$src2),
 281                       "cdb\t$src1, $src2",
 282                       [(SystemZcmp FP64:$src1, (load rriaddr:$src2)),
 283                        (implicit PSW)]>;
 284 } // Defs = [PSW]