1 //==- SystemZInstrFP.td - Floating-point SystemZ instructions --*- tblgen-*-==//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 //===----------------------------------------------------------------------===//
11 // Select instructions
12 //===----------------------------------------------------------------------===//
14 // C's ?: operator for floating-point operands.
15 def SelectF32 : SelectWrapper<FP32>;
16 def SelectF64 : SelectWrapper<FP64>;
17 def SelectF128 : SelectWrapper<FP128>;
19 defm CondStoreF32 : CondStores<FP32, nonvolatile_store,
20 nonvolatile_load, bdxaddr20only>;
21 defm CondStoreF64 : CondStores<FP64, nonvolatile_store,
22 nonvolatile_load, bdxaddr20only>;
24 //===----------------------------------------------------------------------===//
26 //===----------------------------------------------------------------------===//
29 let neverHasSideEffects = 1, isAsCheapAsAMove = 1, isMoveImm = 1 in {
30 def LZER : InherentRRE<"lzer", 0xB374, FP32, (fpimm0)>;
31 def LZDR : InherentRRE<"lzdr", 0xB375, FP64, (fpimm0)>;
32 def LZXR : InherentRRE<"lzxr", 0xB376, FP128, (fpimm0)>;
35 // Moves between two floating-point registers.
36 let neverHasSideEffects = 1 in {
37 def LER : UnaryRR <"le", 0x38, null_frag, FP32, FP32>;
38 def LDR : UnaryRR <"ld", 0x28, null_frag, FP64, FP64>;
39 def LXR : UnaryRRE<"lx", 0xB365, null_frag, FP128, FP128>;
42 // Moves between two floating-point registers that also set the condition
44 let Defs = [CC], CCValues = 0xF, CompareZeroCCMask = 0xF in {
45 defm LTEBR : LoadAndTestRRE<"lteb", 0xB302, FP32>;
46 defm LTDBR : LoadAndTestRRE<"ltdb", 0xB312, FP64>;
47 defm LTXBR : LoadAndTestRRE<"ltxb", 0xB342, FP128>;
49 defm : CompareZeroFP<LTEBRCompare, FP32>;
50 defm : CompareZeroFP<LTDBRCompare, FP64>;
51 defm : CompareZeroFP<LTXBRCompare, FP128>;
53 // Moves between 64-bit integer and floating-point registers.
54 def LGDR : UnaryRRE<"lgd", 0xB3CD, bitconvert, GR64, FP64>;
55 def LDGR : UnaryRRE<"ldg", 0xB3C1, bitconvert, FP64, GR64>;
57 // fcopysign with an FP32 result.
58 let isCodeGenOnly = 1 in {
59 def CPSDRss : BinaryRRF<"cpsd", 0xB372, fcopysign, FP32, FP32>;
60 def CPSDRsd : BinaryRRF<"cpsd", 0xB372, fcopysign, FP32, FP64>;
63 // The sign of an FP128 is in the high register.
64 def : Pat<(fcopysign FP32:$src1, FP128:$src2),
65 (CPSDRsd FP32:$src1, (EXTRACT_SUBREG FP128:$src2, subreg_h64))>;
67 // fcopysign with an FP64 result.
68 let isCodeGenOnly = 1 in
69 def CPSDRds : BinaryRRF<"cpsd", 0xB372, fcopysign, FP64, FP32>;
70 def CPSDRdd : BinaryRRF<"cpsd", 0xB372, fcopysign, FP64, FP64>;
72 // The sign of an FP128 is in the high register.
73 def : Pat<(fcopysign FP64:$src1, FP128:$src2),
74 (CPSDRdd FP64:$src1, (EXTRACT_SUBREG FP128:$src2, subreg_h64))>;
76 // fcopysign with an FP128 result. Use "upper" as the high half and leave
77 // the low half as-is.
78 class CopySign128<RegisterOperand cls, dag upper>
79 : Pat<(fcopysign FP128:$src1, cls:$src2),
80 (INSERT_SUBREG FP128:$src1, upper, subreg_h64)>;
82 def : CopySign128<FP32, (CPSDRds (EXTRACT_SUBREG FP128:$src1, subreg_h64),
84 def : CopySign128<FP64, (CPSDRdd (EXTRACT_SUBREG FP128:$src1, subreg_h64),
86 def : CopySign128<FP128, (CPSDRdd (EXTRACT_SUBREG FP128:$src1, subreg_h64),
87 (EXTRACT_SUBREG FP128:$src2, subreg_h64))>;
89 defm LoadStoreF32 : MVCLoadStore<load, f32, MVCSequence, 4>;
90 defm LoadStoreF64 : MVCLoadStore<load, f64, MVCSequence, 8>;
91 defm LoadStoreF128 : MVCLoadStore<load, f128, MVCSequence, 16>;
93 //===----------------------------------------------------------------------===//
95 //===----------------------------------------------------------------------===//
97 let canFoldAsLoad = 1, SimpleBDXLoad = 1 in {
98 defm LE : UnaryRXPair<"le", 0x78, 0xED64, load, FP32, 4>;
99 defm LD : UnaryRXPair<"ld", 0x68, 0xED65, load, FP64, 8>;
101 // These instructions are split after register allocation, so we don't
102 // want a custom inserter.
103 let Has20BitOffset = 1, HasIndex = 1, Is128Bit = 1 in {
104 def LX : Pseudo<(outs FP128:$dst), (ins bdxaddr20only128:$src),
105 [(set FP128:$dst, (load bdxaddr20only128:$src))]>;
109 //===----------------------------------------------------------------------===//
110 // Store instructions
111 //===----------------------------------------------------------------------===//
113 let SimpleBDXStore = 1 in {
114 defm STE : StoreRXPair<"ste", 0x70, 0xED66, store, FP32, 4>;
115 defm STD : StoreRXPair<"std", 0x60, 0xED67, store, FP64, 8>;
117 // These instructions are split after register allocation, so we don't
118 // want a custom inserter.
119 let Has20BitOffset = 1, HasIndex = 1, Is128Bit = 1 in {
120 def STX : Pseudo<(outs), (ins FP128:$src, bdxaddr20only128:$dst),
121 [(store FP128:$src, bdxaddr20only128:$dst)]>;
125 //===----------------------------------------------------------------------===//
126 // Conversion instructions
127 //===----------------------------------------------------------------------===//
129 // Convert floating-point values to narrower representations, rounding
130 // according to the current mode. The destination of LEXBR and LDXBR
131 // is a 128-bit value, but only the first register of the pair is used.
132 def LEDBR : UnaryRRE<"ledb", 0xB344, fround, FP32, FP64>;
133 def LEXBR : UnaryRRE<"lexb", 0xB346, null_frag, FP128, FP128>;
134 def LDXBR : UnaryRRE<"ldxb", 0xB345, null_frag, FP128, FP128>;
136 def : Pat<(f32 (fround FP128:$src)),
137 (EXTRACT_SUBREG (LEXBR FP128:$src), subreg_hh32)>;
138 def : Pat<(f64 (fround FP128:$src)),
139 (EXTRACT_SUBREG (LDXBR FP128:$src), subreg_h64)>;
141 // Extend register floating-point values to wider representations.
142 def LDEBR : UnaryRRE<"ldeb", 0xB304, fextend, FP64, FP32>;
143 def LXEBR : UnaryRRE<"lxeb", 0xB306, fextend, FP128, FP32>;
144 def LXDBR : UnaryRRE<"lxdb", 0xB305, fextend, FP128, FP64>;
146 // Extend memory floating-point values to wider representations.
147 def LDEB : UnaryRXE<"ldeb", 0xED04, extloadf32, FP64, 4>;
148 def LXEB : UnaryRXE<"lxeb", 0xED06, extloadf32, FP128, 4>;
149 def LXDB : UnaryRXE<"lxdb", 0xED05, extloadf64, FP128, 8>;
151 // Convert a signed integer register value to a floating-point one.
152 def CEFBR : UnaryRRE<"cefb", 0xB394, sint_to_fp, FP32, GR32>;
153 def CDFBR : UnaryRRE<"cdfb", 0xB395, sint_to_fp, FP64, GR32>;
154 def CXFBR : UnaryRRE<"cxfb", 0xB396, sint_to_fp, FP128, GR32>;
156 def CEGBR : UnaryRRE<"cegb", 0xB3A4, sint_to_fp, FP32, GR64>;
157 def CDGBR : UnaryRRE<"cdgb", 0xB3A5, sint_to_fp, FP64, GR64>;
158 def CXGBR : UnaryRRE<"cxgb", 0xB3A6, sint_to_fp, FP128, GR64>;
160 // Convert am unsigned integer register value to a floating-point one.
161 let Predicates = [FeatureFPExtension] in {
162 def CELFBR : UnaryRRF4<"celfbr", 0xB390, FP32, GR32>;
163 def CDLFBR : UnaryRRF4<"cdlfbr", 0xB391, FP64, GR32>;
164 def CXLFBR : UnaryRRF4<"cxlfbr", 0xB392, FP128, GR32>;
166 def CELGBR : UnaryRRF4<"celgbr", 0xB3A0, FP32, GR64>;
167 def CDLGBR : UnaryRRF4<"cdlgbr", 0xB3A1, FP64, GR64>;
168 def CXLGBR : UnaryRRF4<"cxlgbr", 0xB3A2, FP128, GR64>;
170 def : Pat<(f32 (uint_to_fp GR32:$src)), (CELFBR 0, GR32:$src, 0)>;
171 def : Pat<(f64 (uint_to_fp GR32:$src)), (CDLFBR 0, GR32:$src, 0)>;
172 def : Pat<(f128 (uint_to_fp GR32:$src)), (CXLFBR 0, GR32:$src, 0)>;
174 def : Pat<(f32 (uint_to_fp GR64:$src)), (CELGBR 0, GR64:$src, 0)>;
175 def : Pat<(f64 (uint_to_fp GR64:$src)), (CDLGBR 0, GR64:$src, 0)>;
176 def : Pat<(f128 (uint_to_fp GR64:$src)), (CXLGBR 0, GR64:$src, 0)>;
179 // Convert a floating-point register value to a signed integer value,
180 // with the second operand (modifier M3) specifying the rounding mode.
182 def CFEBR : UnaryRRF<"cfeb", 0xB398, GR32, FP32>;
183 def CFDBR : UnaryRRF<"cfdb", 0xB399, GR32, FP64>;
184 def CFXBR : UnaryRRF<"cfxb", 0xB39A, GR32, FP128>;
186 def CGEBR : UnaryRRF<"cgeb", 0xB3A8, GR64, FP32>;
187 def CGDBR : UnaryRRF<"cgdb", 0xB3A9, GR64, FP64>;
188 def CGXBR : UnaryRRF<"cgxb", 0xB3AA, GR64, FP128>;
191 // fp_to_sint always rounds towards zero, which is modifier value 5.
192 def : Pat<(i32 (fp_to_sint FP32:$src)), (CFEBR 5, FP32:$src)>;
193 def : Pat<(i32 (fp_to_sint FP64:$src)), (CFDBR 5, FP64:$src)>;
194 def : Pat<(i32 (fp_to_sint FP128:$src)), (CFXBR 5, FP128:$src)>;
196 def : Pat<(i64 (fp_to_sint FP32:$src)), (CGEBR 5, FP32:$src)>;
197 def : Pat<(i64 (fp_to_sint FP64:$src)), (CGDBR 5, FP64:$src)>;
198 def : Pat<(i64 (fp_to_sint FP128:$src)), (CGXBR 5, FP128:$src)>;
200 // Convert a floating-point register value to an unsigned integer value.
201 let Predicates = [FeatureFPExtension] in {
203 def CLFEBR : UnaryRRF4<"clfebr", 0xB39C, GR32, FP32>;
204 def CLFDBR : UnaryRRF4<"clfdbr", 0xB39D, GR32, FP64>;
205 def CLFXBR : UnaryRRF4<"clfxbr", 0xB39E, GR32, FP128>;
207 def CLGEBR : UnaryRRF4<"clgebr", 0xB3AC, GR64, FP32>;
208 def CLGDBR : UnaryRRF4<"clgdbr", 0xB3AD, GR64, FP64>;
209 def CLGXBR : UnaryRRF4<"clgxbr", 0xB3AE, GR64, FP128>;
212 def : Pat<(i32 (fp_to_uint FP32:$src)), (CLFEBR 5, FP32:$src, 0)>;
213 def : Pat<(i32 (fp_to_uint FP64:$src)), (CLFDBR 5, FP64:$src, 0)>;
214 def : Pat<(i32 (fp_to_uint FP128:$src)), (CLFXBR 5, FP128:$src, 0)>;
216 def : Pat<(i64 (fp_to_uint FP32:$src)), (CLGEBR 5, FP32:$src, 0)>;
217 def : Pat<(i64 (fp_to_uint FP64:$src)), (CLGDBR 5, FP64:$src, 0)>;
218 def : Pat<(i64 (fp_to_uint FP128:$src)), (CLGXBR 5, FP128:$src, 0)>;
222 //===----------------------------------------------------------------------===//
224 //===----------------------------------------------------------------------===//
226 // Negation (Load Complement).
227 let Defs = [CC], CCValues = 0xF, CompareZeroCCMask = 0xF in {
228 def LCEBR : UnaryRRE<"lceb", 0xB303, fneg, FP32, FP32>;
229 def LCDBR : UnaryRRE<"lcdb", 0xB313, fneg, FP64, FP64>;
230 def LCXBR : UnaryRRE<"lcxb", 0xB343, fneg, FP128, FP128>;
233 // Absolute value (Load Positive).
234 let Defs = [CC], CCValues = 0xF, CompareZeroCCMask = 0xF in {
235 def LPEBR : UnaryRRE<"lpeb", 0xB300, fabs, FP32, FP32>;
236 def LPDBR : UnaryRRE<"lpdb", 0xB310, fabs, FP64, FP64>;
237 def LPXBR : UnaryRRE<"lpxb", 0xB340, fabs, FP128, FP128>;
240 // Negative absolute value (Load Negative).
241 let Defs = [CC], CCValues = 0xF, CompareZeroCCMask = 0xF in {
242 def LNEBR : UnaryRRE<"lneb", 0xB301, fnabs, FP32, FP32>;
243 def LNDBR : UnaryRRE<"lndb", 0xB311, fnabs, FP64, FP64>;
244 def LNXBR : UnaryRRE<"lnxb", 0xB341, fnabs, FP128, FP128>;
248 def SQEBR : UnaryRRE<"sqeb", 0xB314, fsqrt, FP32, FP32>;
249 def SQDBR : UnaryRRE<"sqdb", 0xB315, fsqrt, FP64, FP64>;
250 def SQXBR : UnaryRRE<"sqxb", 0xB316, fsqrt, FP128, FP128>;
252 def SQEB : UnaryRXE<"sqeb", 0xED14, loadu<fsqrt>, FP32, 4>;
253 def SQDB : UnaryRXE<"sqdb", 0xED15, loadu<fsqrt>, FP64, 8>;
255 // Round to an integer, with the second operand (modifier M3) specifying
256 // the rounding mode. These forms always check for inexact conditions.
257 def FIEBR : UnaryRRF<"fieb", 0xB357, FP32, FP32>;
258 def FIDBR : UnaryRRF<"fidb", 0xB35F, FP64, FP64>;
259 def FIXBR : UnaryRRF<"fixb", 0xB347, FP128, FP128>;
261 // frint rounds according to the current mode (modifier 0) and detects
262 // inexact conditions.
263 def : Pat<(frint FP32:$src), (FIEBR 0, FP32:$src)>;
264 def : Pat<(frint FP64:$src), (FIDBR 0, FP64:$src)>;
265 def : Pat<(frint FP128:$src), (FIXBR 0, FP128:$src)>;
267 let Predicates = [FeatureFPExtension] in {
268 // Extended forms of the FIxBR instructions. M4 can be set to 4
269 // to suppress detection of inexact conditions.
270 def FIEBRA : UnaryRRF4<"fiebra", 0xB357, FP32, FP32>;
271 def FIDBRA : UnaryRRF4<"fidbra", 0xB35F, FP64, FP64>;
272 def FIXBRA : UnaryRRF4<"fixbra", 0xB347, FP128, FP128>;
274 // fnearbyint is like frint but does not detect inexact conditions.
275 def : Pat<(fnearbyint FP32:$src), (FIEBRA 0, FP32:$src, 4)>;
276 def : Pat<(fnearbyint FP64:$src), (FIDBRA 0, FP64:$src, 4)>;
277 def : Pat<(fnearbyint FP128:$src), (FIXBRA 0, FP128:$src, 4)>;
279 // floor is no longer allowed to raise an inexact condition,
280 // so restrict it to the cases where the condition can be suppressed.
281 // Mode 7 is round towards -inf.
282 def : Pat<(ffloor FP32:$src), (FIEBRA 7, FP32:$src, 4)>;
283 def : Pat<(ffloor FP64:$src), (FIDBRA 7, FP64:$src, 4)>;
284 def : Pat<(ffloor FP128:$src), (FIXBRA 7, FP128:$src, 4)>;
286 // Same idea for ceil, where mode 6 is round towards +inf.
287 def : Pat<(fceil FP32:$src), (FIEBRA 6, FP32:$src, 4)>;
288 def : Pat<(fceil FP64:$src), (FIDBRA 6, FP64:$src, 4)>;
289 def : Pat<(fceil FP128:$src), (FIXBRA 6, FP128:$src, 4)>;
291 // Same idea for trunc, where mode 5 is round towards zero.
292 def : Pat<(ftrunc FP32:$src), (FIEBRA 5, FP32:$src, 4)>;
293 def : Pat<(ftrunc FP64:$src), (FIDBRA 5, FP64:$src, 4)>;
294 def : Pat<(ftrunc FP128:$src), (FIXBRA 5, FP128:$src, 4)>;
296 // Same idea for round, where mode 1 is round towards nearest with
297 // ties away from zero.
298 def : Pat<(frnd FP32:$src), (FIEBRA 1, FP32:$src, 4)>;
299 def : Pat<(frnd FP64:$src), (FIDBRA 1, FP64:$src, 4)>;
300 def : Pat<(frnd FP128:$src), (FIXBRA 1, FP128:$src, 4)>;
303 //===----------------------------------------------------------------------===//
305 //===----------------------------------------------------------------------===//
308 let Defs = [CC], CCValues = 0xF, CompareZeroCCMask = 0xF in {
309 let isCommutable = 1 in {
310 def AEBR : BinaryRRE<"aeb", 0xB30A, fadd, FP32, FP32>;
311 def ADBR : BinaryRRE<"adb", 0xB31A, fadd, FP64, FP64>;
312 def AXBR : BinaryRRE<"axb", 0xB34A, fadd, FP128, FP128>;
314 def AEB : BinaryRXE<"aeb", 0xED0A, fadd, FP32, load, 4>;
315 def ADB : BinaryRXE<"adb", 0xED1A, fadd, FP64, load, 8>;
319 let Defs = [CC], CCValues = 0xF, CompareZeroCCMask = 0xF in {
320 def SEBR : BinaryRRE<"seb", 0xB30B, fsub, FP32, FP32>;
321 def SDBR : BinaryRRE<"sdb", 0xB31B, fsub, FP64, FP64>;
322 def SXBR : BinaryRRE<"sxb", 0xB34B, fsub, FP128, FP128>;
324 def SEB : BinaryRXE<"seb", 0xED0B, fsub, FP32, load, 4>;
325 def SDB : BinaryRXE<"sdb", 0xED1B, fsub, FP64, load, 8>;
329 let isCommutable = 1 in {
330 def MEEBR : BinaryRRE<"meeb", 0xB317, fmul, FP32, FP32>;
331 def MDBR : BinaryRRE<"mdb", 0xB31C, fmul, FP64, FP64>;
332 def MXBR : BinaryRRE<"mxb", 0xB34C, fmul, FP128, FP128>;
334 def MEEB : BinaryRXE<"meeb", 0xED17, fmul, FP32, load, 4>;
335 def MDB : BinaryRXE<"mdb", 0xED1C, fmul, FP64, load, 8>;
337 // f64 multiplication of two FP32 registers.
338 def MDEBR : BinaryRRE<"mdeb", 0xB30C, null_frag, FP64, FP32>;
339 def : Pat<(fmul (f64 (fextend FP32:$src1)), (f64 (fextend FP32:$src2))),
340 (MDEBR (INSERT_SUBREG (f64 (IMPLICIT_DEF)),
341 FP32:$src1, subreg_h32), FP32:$src2)>;
343 // f64 multiplication of an FP32 register and an f32 memory.
344 def MDEB : BinaryRXE<"mdeb", 0xED0C, null_frag, FP64, load, 4>;
345 def : Pat<(fmul (f64 (fextend FP32:$src1)),
346 (f64 (extloadf32 bdxaddr12only:$addr))),
347 (MDEB (INSERT_SUBREG (f64 (IMPLICIT_DEF)), FP32:$src1, subreg_h32),
348 bdxaddr12only:$addr)>;
350 // f128 multiplication of two FP64 registers.
351 def MXDBR : BinaryRRE<"mxdb", 0xB307, null_frag, FP128, FP64>;
352 def : Pat<(fmul (f128 (fextend FP64:$src1)), (f128 (fextend FP64:$src2))),
353 (MXDBR (INSERT_SUBREG (f128 (IMPLICIT_DEF)),
354 FP64:$src1, subreg_h64), FP64:$src2)>;
356 // f128 multiplication of an FP64 register and an f64 memory.
357 def MXDB : BinaryRXE<"mxdb", 0xED07, null_frag, FP128, load, 8>;
358 def : Pat<(fmul (f128 (fextend FP64:$src1)),
359 (f128 (extloadf64 bdxaddr12only:$addr))),
360 (MXDB (INSERT_SUBREG (f128 (IMPLICIT_DEF)), FP64:$src1, subreg_h64),
361 bdxaddr12only:$addr)>;
363 // Fused multiply-add.
364 def MAEBR : TernaryRRD<"maeb", 0xB30E, z_fma, FP32>;
365 def MADBR : TernaryRRD<"madb", 0xB31E, z_fma, FP64>;
367 def MAEB : TernaryRXF<"maeb", 0xED0E, z_fma, FP32, load, 4>;
368 def MADB : TernaryRXF<"madb", 0xED1E, z_fma, FP64, load, 8>;
370 // Fused multiply-subtract.
371 def MSEBR : TernaryRRD<"mseb", 0xB30F, z_fms, FP32>;
372 def MSDBR : TernaryRRD<"msdb", 0xB31F, z_fms, FP64>;
374 def MSEB : TernaryRXF<"mseb", 0xED0F, z_fms, FP32, load, 4>;
375 def MSDB : TernaryRXF<"msdb", 0xED1F, z_fms, FP64, load, 8>;
378 def DEBR : BinaryRRE<"deb", 0xB30D, fdiv, FP32, FP32>;
379 def DDBR : BinaryRRE<"ddb", 0xB31D, fdiv, FP64, FP64>;
380 def DXBR : BinaryRRE<"dxb", 0xB34D, fdiv, FP128, FP128>;
382 def DEB : BinaryRXE<"deb", 0xED0D, fdiv, FP32, load, 4>;
383 def DDB : BinaryRXE<"ddb", 0xED1D, fdiv, FP64, load, 8>;
385 //===----------------------------------------------------------------------===//
387 //===----------------------------------------------------------------------===//
389 let Defs = [CC], CCValues = 0xF in {
390 def CEBR : CompareRRE<"ceb", 0xB309, z_fcmp, FP32, FP32>;
391 def CDBR : CompareRRE<"cdb", 0xB319, z_fcmp, FP64, FP64>;
392 def CXBR : CompareRRE<"cxb", 0xB349, z_fcmp, FP128, FP128>;
394 def CEB : CompareRXE<"ceb", 0xED09, z_fcmp, FP32, load, 4>;
395 def CDB : CompareRXE<"cdb", 0xED19, z_fcmp, FP64, load, 8>;
398 //===----------------------------------------------------------------------===//
400 //===----------------------------------------------------------------------===//
402 def : Pat<(f32 fpimmneg0), (LCEBR (LZER))>;
403 def : Pat<(f64 fpimmneg0), (LCDBR (LZDR))>;
404 def : Pat<(f128 fpimmneg0), (LCXBR (LZXR))>;