1 //===-- SystemZISelLowering.h - SystemZ DAG lowering interface --*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the interfaces that SystemZ uses to lower LLVM code into a
13 //===----------------------------------------------------------------------===//
15 #ifndef LLVM_LIB_TARGET_SYSTEMZ_SYSTEMZISELLOWERING_H
16 #define LLVM_LIB_TARGET_SYSTEMZ_SYSTEMZISELLOWERING_H
19 #include "llvm/CodeGen/MachineBasicBlock.h"
20 #include "llvm/CodeGen/SelectionDAG.h"
21 #include "llvm/Target/TargetLowering.h"
24 namespace SystemZISD {
25 enum NodeType : unsigned {
26 FIRST_NUMBER = ISD::BUILTIN_OP_END,
28 // Return with a flag operand. Operand 0 is the chain operand.
31 // Calls a function. Operand 0 is the chain operand and operand 1
32 // is the target address. The arguments start at operand 2.
33 // There is an optional glue operand at the end.
37 // TLS calls. Like regular calls, except operand 1 is the TLS symbol.
38 // (The call target is implicitly __tls_get_offset.)
42 // Wraps a TargetGlobalAddress that should be loaded using PC-relative
43 // accesses (LARL). Operand 0 is the address.
46 // Used in cases where an offset is applied to a TargetGlobalAddress.
47 // Operand 0 is the full TargetGlobalAddress and operand 1 is a
48 // PCREL_WRAPPER for an anchor point. This is used so that we can
49 // cheaply refer to either the full address or the anchor point
50 // as a register base.
56 // Integer comparisons. There are three operands: the two values
57 // to compare, and an integer of type SystemZICMP.
60 // Floating-point comparisons. The two operands are the values to compare.
63 // Test under mask. The first operand is ANDed with the second operand
64 // and the condition codes are set on the result. The third operand is
65 // a boolean that is true if the condition codes need to distinguish
66 // between CCMASK_TM_MIXED_MSB_0 and CCMASK_TM_MIXED_MSB_1 (which the
67 // register forms do but the memory forms don't).
70 // Branches if a condition is true. Operand 0 is the chain operand;
71 // operand 1 is the 4-bit condition-code mask, with bit N in
72 // big-endian order meaning "branch if CC=N"; operand 2 is the
73 // target block and operand 3 is the flag operand.
76 // Selects between operand 0 and operand 1. Operand 2 is the
77 // mask of condition-code values for which operand 0 should be
78 // chosen over operand 1; it has the same form as BR_CCMASK.
79 // Operand 3 is the flag operand.
82 // Evaluates to the gap between the stack pointer and the
83 // base of the dynamically-allocatable area.
86 // Extracts the value of a 32-bit access register. Operand 0 is
87 // the number of the register.
90 // Count number of bits set in operand 0 per byte.
93 // Wrappers around the ISD opcodes of the same name. The output and
94 // first input operands are GR128s. The trailing numbers are the
95 // widths of the second operand in bits.
102 // Use a series of MVCs to copy bytes from one memory location to another.
104 // - the target address
105 // - the source address
106 // - the constant length
108 // This isn't a memory opcode because we'd need to attach two
109 // MachineMemOperands rather than one.
112 // Like MVC, but implemented as a loop that handles X*256 bytes
113 // followed by straight-line code to handle the rest (if any).
114 // The value of X is passed as an additional operand.
117 // Similar to MVC and MVC_LOOP, but for logic operations (AND, OR, XOR).
125 // Use CLC to compare two blocks of memory, with the same comments
126 // as for MVC and MVC_LOOP.
130 // Use an MVST-based sequence to implement stpcpy().
133 // Use a CLST-based sequence to implement strcmp(). The two input operands
134 // are the addresses of the strings to compare.
137 // Use an SRST-based sequence to search a block of memory. The first
138 // operand is the end address, the second is the start, and the third
139 // is the character to search for. CC is set to 1 on success and 2
143 // Store the CC value in bits 29 and 28 of an integer.
146 // Perform a serialization operation. (BCR 15,0 or BCR 14,0.)
149 // Transaction begin. The first operand is the chain, the second
150 // the TDB pointer, and the third the immediate control field.
151 // Returns chain and glue.
155 // Transaction end. Just the chain operand. Returns chain and glue.
158 // Create a vector constant by filling byte N of the result with bit
159 // 15-N of the single operand.
162 // Create a vector constant by replicating an element-sized RISBG-style mask.
163 // The first operand specifies the starting set bit and the second operand
164 // specifies the ending set bit. Both operands count from the MSB of the
168 // Replicate a GPR scalar value into all elements of a vector.
171 // Create a vector from two i64 GPRs.
174 // Replicate one element of a vector into all elements. The first operand
175 // is the vector and the second is the index of the element to replicate.
178 // Interleave elements from the high half of operand 0 and the high half
182 // Likewise for the low halves.
185 // Concatenate the vectors in the first two operands, shift them left
186 // by the third operand, and take the first half of the result.
189 // Take one element of the first v2i64 operand and the one element of
190 // the second v2i64 operand and concatenate them to form a v2i64 result.
191 // The third operand is a 4-bit value of the form 0A0B, where A and B
192 // are the element selectors for the first operand and second operands
196 // Perform a general vector permute on vector operands 0 and 1.
197 // Each byte of operand 2 controls the corresponding byte of the result,
198 // in the same way as a byte-level VECTOR_SHUFFLE mask.
201 // Pack vector operands 0 and 1 into a single vector with half-sized elements.
204 // Likewise, but saturate the result and set CC. PACKS_CC does signed
205 // saturation and PACKLS_CC does unsigned saturation.
209 // Unpack the first half of vector operand 0 into double-sized elements.
210 // UNPACK_HIGH sign-extends and UNPACKL_HIGH zero-extends.
214 // Likewise for the second half.
218 // Shift each element of vector operand 0 by the number of bits specified
219 // by scalar operand 1.
224 // For each element of the output type, sum across all sub-elements of
225 // operand 0 belonging to the corresponding element, and add in the
226 // rightmost sub-element of the corresponding element of operand 1.
229 // Compare integer vector operands 0 and 1 to produce the usual 0/-1
230 // vector result. VICMPE is for equality, VICMPH for "signed greater than"
231 // and VICMPHL for "unsigned greater than".
236 // Likewise, but also set the condition codes on the result.
241 // Compare floating-point vector operands 0 and 1 to preoduce the usual 0/-1
242 // vector result. VFCMPE is for "ordered and equal", VFCMPH for "ordered and
243 // greater than" and VFCMPHE for "ordered and greater than or equal to".
248 // Likewise, but also set the condition codes on the result.
253 // Test floating-point data class for vectors.
256 // Extend the even f32 elements of vector operand 0 to produce a vector
260 // Round the f64 elements of vector operand 0 to f32s and store them in the
261 // even elements of the result.
264 // AND the two vector operands together and set CC based on the result.
267 // String operations that set CC as a side-effect.
278 // Wrappers around the inner loop of an 8- or 16-bit ATOMIC_SWAP or
281 // Operand 0: the address of the containing 32-bit-aligned field
282 // Operand 1: the second operand of <op>, in the high bits of an i32
283 // for everything except ATOMIC_SWAPW
284 // Operand 2: how many bits to rotate the i32 left to bring the first
285 // operand into the high bits
286 // Operand 3: the negative of operand 2, for rotating the other way
287 // Operand 4: the width of the field in bits (8 or 16)
288 ATOMIC_SWAPW = ISD::FIRST_TARGET_MEMORY_OPCODE,
300 // A wrapper around the inner loop of an ATOMIC_CMP_SWAP.
302 // Operand 0: the address of the containing 32-bit-aligned field
303 // Operand 1: the compare value, in the low bits of an i32
304 // Operand 2: the swap value, in the low bits of an i32
305 // Operand 3: how many bits to rotate the i32 left to bring the first
306 // operand into the high bits
307 // Operand 4: the negative of operand 2, for rotating the other way
308 // Operand 5: the width of the field in bits (8 or 16)
311 // Prefetch from the second operand using the 4-bit control code in
312 // the first operand. The code is 1 for a load prefetch and 2 for
317 // Return true if OPCODE is some kind of PC-relative address.
318 inline bool isPCREL(unsigned Opcode) {
319 return Opcode == PCREL_WRAPPER || Opcode == PCREL_OFFSET;
321 } // end namespace SystemZISD
323 namespace SystemZICMP {
324 // Describes whether an integer comparison needs to be signed or unsigned,
325 // or whether either type is OK.
331 } // end namespace SystemZICMP
333 class SystemZSubtarget;
334 class SystemZTargetMachine;
336 class SystemZTargetLowering : public TargetLowering {
338 explicit SystemZTargetLowering(const TargetMachine &TM,
339 const SystemZSubtarget &STI);
341 // Override TargetLowering.
342 MVT getScalarShiftAmountTy(EVT LHSTy) const override {
345 MVT getVectorIdxTy() const override {
346 // Only the lower 12 bits of an element index are used, so we don't
347 // want to clobber the upper 32 bits of a GPR unnecessarily.
350 TargetLoweringBase::LegalizeTypeAction getPreferredVectorAction(EVT VT)
352 // Widen subvectors to the full width rather than promoting integer
353 // elements. This is better because:
355 // (a) it means that we can handle the ABI for passing and returning
356 // sub-128 vectors without having to handle them as legal types.
358 // (b) we don't have instructions to extend on load and truncate on store,
359 // so promoting the integers is less efficient.
361 // (c) there are no multiplication instructions for the widest integer
363 if (VT.getVectorElementType().getSizeInBits() % 8 == 0)
364 return TypeWidenVector;
365 return TargetLoweringBase::getPreferredVectorAction(VT);
367 EVT getSetCCResultType(LLVMContext &, EVT) const override;
368 bool isFMAFasterThanFMulAndFAdd(EVT VT) const override;
369 bool isFPImmLegal(const APFloat &Imm, EVT VT) const override;
370 bool isLegalICmpImmediate(int64_t Imm) const override;
371 bool isLegalAddImmediate(int64_t Imm) const override;
372 bool isLegalAddressingMode(const AddrMode &AM, Type *Ty,
373 unsigned AS) const override;
374 bool allowsMisalignedMemoryAccesses(EVT VT, unsigned AS,
376 bool *Fast) const override;
377 bool isTruncateFree(Type *, Type *) const override;
378 bool isTruncateFree(EVT, EVT) const override;
379 const char *getTargetNodeName(unsigned Opcode) const override;
380 std::pair<unsigned, const TargetRegisterClass *>
381 getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI,
382 const std::string &Constraint,
383 MVT VT) const override;
384 TargetLowering::ConstraintType
385 getConstraintType(const std::string &Constraint) const override;
386 TargetLowering::ConstraintWeight
387 getSingleConstraintMatchWeight(AsmOperandInfo &info,
388 const char *constraint) const override;
389 void LowerAsmOperandForConstraint(SDValue Op,
390 std::string &Constraint,
391 std::vector<SDValue> &Ops,
392 SelectionDAG &DAG) const override;
394 unsigned getInlineAsmMemConstraint(
395 const std::string &ConstraintCode) const override {
396 if (ConstraintCode.size() == 1) {
397 switch(ConstraintCode[0]) {
401 return InlineAsm::Constraint_Q;
403 return InlineAsm::Constraint_R;
405 return InlineAsm::Constraint_S;
407 return InlineAsm::Constraint_T;
410 return TargetLowering::getInlineAsmMemConstraint(ConstraintCode);
413 MachineBasicBlock *EmitInstrWithCustomInserter(MachineInstr *MI,
414 MachineBasicBlock *BB) const
416 SDValue LowerOperation(SDValue Op, SelectionDAG &DAG) const override;
417 bool allowTruncateForTailCall(Type *, Type *) const override;
418 bool mayBeEmittedAsTailCall(CallInst *CI) const override;
419 SDValue LowerFormalArguments(SDValue Chain, CallingConv::ID CallConv,
421 const SmallVectorImpl<ISD::InputArg> &Ins,
422 SDLoc DL, SelectionDAG &DAG,
423 SmallVectorImpl<SDValue> &InVals) const override;
424 SDValue LowerCall(CallLoweringInfo &CLI,
425 SmallVectorImpl<SDValue> &InVals) const override;
427 SDValue LowerReturn(SDValue Chain, CallingConv::ID CallConv, bool IsVarArg,
428 const SmallVectorImpl<ISD::OutputArg> &Outs,
429 const SmallVectorImpl<SDValue> &OutVals,
430 SDLoc DL, SelectionDAG &DAG) const override;
431 SDValue prepareVolatileOrAtomicLoad(SDValue Chain, SDLoc DL,
432 SelectionDAG &DAG) const override;
433 SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const override;
436 const SystemZSubtarget &Subtarget;
438 // Implement LowerOperation for individual opcodes.
439 SDValue lowerSETCC(SDValue Op, SelectionDAG &DAG) const;
440 SDValue lowerBR_CC(SDValue Op, SelectionDAG &DAG) const;
441 SDValue lowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const;
442 SDValue lowerGlobalAddress(GlobalAddressSDNode *Node,
443 SelectionDAG &DAG) const;
444 SDValue lowerTLSGetOffset(GlobalAddressSDNode *Node,
445 SelectionDAG &DAG, unsigned Opcode,
446 SDValue GOTOffset) const;
447 SDValue lowerGlobalTLSAddress(GlobalAddressSDNode *Node,
448 SelectionDAG &DAG) const;
449 SDValue lowerBlockAddress(BlockAddressSDNode *Node,
450 SelectionDAG &DAG) const;
451 SDValue lowerJumpTable(JumpTableSDNode *JT, SelectionDAG &DAG) const;
452 SDValue lowerConstantPool(ConstantPoolSDNode *CP, SelectionDAG &DAG) const;
453 SDValue lowerVASTART(SDValue Op, SelectionDAG &DAG) const;
454 SDValue lowerVACOPY(SDValue Op, SelectionDAG &DAG) const;
455 SDValue lowerDYNAMIC_STACKALLOC(SDValue Op, SelectionDAG &DAG) const;
456 SDValue lowerSMUL_LOHI(SDValue Op, SelectionDAG &DAG) const;
457 SDValue lowerUMUL_LOHI(SDValue Op, SelectionDAG &DAG) const;
458 SDValue lowerSDIVREM(SDValue Op, SelectionDAG &DAG) const;
459 SDValue lowerUDIVREM(SDValue Op, SelectionDAG &DAG) const;
460 SDValue lowerBITCAST(SDValue Op, SelectionDAG &DAG) const;
461 SDValue lowerOR(SDValue Op, SelectionDAG &DAG) const;
462 SDValue lowerCTPOP(SDValue Op, SelectionDAG &DAG) const;
463 SDValue lowerATOMIC_LOAD(SDValue Op, SelectionDAG &DAG) const;
464 SDValue lowerATOMIC_STORE(SDValue Op, SelectionDAG &DAG) const;
465 SDValue lowerATOMIC_LOAD_OP(SDValue Op, SelectionDAG &DAG,
466 unsigned Opcode) const;
467 SDValue lowerATOMIC_LOAD_SUB(SDValue Op, SelectionDAG &DAG) const;
468 SDValue lowerATOMIC_CMP_SWAP(SDValue Op, SelectionDAG &DAG) const;
469 SDValue lowerLOAD_SEQUENCE_POINT(SDValue Op, SelectionDAG &DAG) const;
470 SDValue lowerSTACKSAVE(SDValue Op, SelectionDAG &DAG) const;
471 SDValue lowerSTACKRESTORE(SDValue Op, SelectionDAG &DAG) const;
472 SDValue lowerPREFETCH(SDValue Op, SelectionDAG &DAG) const;
473 SDValue lowerINTRINSIC_W_CHAIN(SDValue Op, SelectionDAG &DAG) const;
474 SDValue lowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG) const;
475 SDValue lowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG) const;
476 SDValue lowerVECTOR_SHUFFLE(SDValue Op, SelectionDAG &DAG) const;
477 SDValue lowerSCALAR_TO_VECTOR(SDValue Op, SelectionDAG &DAG) const;
478 SDValue lowerINSERT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) const;
479 SDValue lowerEXTRACT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) const;
480 SDValue lowerExtendVectorInreg(SDValue Op, SelectionDAG &DAG,
481 unsigned UnpackHigh) const;
482 SDValue lowerShift(SDValue Op, SelectionDAG &DAG, unsigned ByScalar) const;
484 SDValue combineExtract(SDLoc DL, EVT ElemVT, EVT VecVT, SDValue OrigOp,
485 unsigned Index, DAGCombinerInfo &DCI,
487 SDValue combineTruncateExtract(SDLoc DL, EVT TruncVT, SDValue Op,
488 DAGCombinerInfo &DCI) const;
490 // If the last instruction before MBBI in MBB was some form of COMPARE,
491 // try to replace it with a COMPARE AND BRANCH just before MBBI.
492 // CCMask and Target are the BRC-like operands for the branch.
493 // Return true if the change was made.
494 bool convertPrevCompareToBranch(MachineBasicBlock *MBB,
495 MachineBasicBlock::iterator MBBI,
497 MachineBasicBlock *Target) const;
499 // Implement EmitInstrWithCustomInserter for individual operation types.
500 MachineBasicBlock *emitSelect(MachineInstr *MI,
501 MachineBasicBlock *BB) const;
502 MachineBasicBlock *emitCondStore(MachineInstr *MI,
503 MachineBasicBlock *BB,
504 unsigned StoreOpcode, unsigned STOCOpcode,
506 MachineBasicBlock *emitExt128(MachineInstr *MI,
507 MachineBasicBlock *MBB,
508 bool ClearEven, unsigned SubReg) const;
509 MachineBasicBlock *emitAtomicLoadBinary(MachineInstr *MI,
510 MachineBasicBlock *BB,
511 unsigned BinOpcode, unsigned BitSize,
512 bool Invert = false) const;
513 MachineBasicBlock *emitAtomicLoadMinMax(MachineInstr *MI,
514 MachineBasicBlock *MBB,
515 unsigned CompareOpcode,
516 unsigned KeepOldMask,
517 unsigned BitSize) const;
518 MachineBasicBlock *emitAtomicCmpSwapW(MachineInstr *MI,
519 MachineBasicBlock *BB) const;
520 MachineBasicBlock *emitMemMemWrapper(MachineInstr *MI,
521 MachineBasicBlock *BB,
522 unsigned Opcode) const;
523 MachineBasicBlock *emitStringWrapper(MachineInstr *MI,
524 MachineBasicBlock *BB,
525 unsigned Opcode) const;
526 MachineBasicBlock *emitTransactionBegin(MachineInstr *MI,
527 MachineBasicBlock *MBB,
531 } // end namespace llvm