1 //===-- SystemZISelLowering.h - SystemZ DAG lowering interface --*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the interfaces that SystemZ uses to lower LLVM code into a
13 //===----------------------------------------------------------------------===//
15 #ifndef LLVM_TARGET_SystemZ_ISELLOWERING_H
16 #define LLVM_TARGET_SystemZ_ISELLOWERING_H
19 #include "llvm/CodeGen/MachineBasicBlock.h"
20 #include "llvm/CodeGen/SelectionDAG.h"
21 #include "llvm/Target/TargetLowering.h"
24 namespace SystemZISD {
26 FIRST_NUMBER = ISD::BUILTIN_OP_END,
28 // Return with a flag operand. Operand 0 is the chain operand.
31 // Calls a function. Operand 0 is the chain operand and operand 1
32 // is the target address. The arguments start at operand 2.
33 // There is an optional glue operand at the end.
37 // Wraps a TargetGlobalAddress that should be loaded using PC-relative
38 // accesses (LARL). Operand 0 is the address.
41 // Used in cases where an offset is applied to a TargetGlobalAddress.
42 // Operand 0 is the full TargetGlobalAddress and operand 1 is a
43 // PCREL_WRAPPER for an anchor point. This is used so that we can
44 // cheaply refer to either the full address or the anchor point
45 // as a register base.
51 // Integer comparisons. There are three operands: the two values
52 // to compare, and an integer of type SystemZICMP.
55 // Floating-point comparisons. The two operands are the values to compare.
58 // Test under mask. The first operand is ANDed with the second operand
59 // and the condition codes are set on the result. The third operand is
60 // a boolean that is true if the condition codes need to distinguish
61 // between CCMASK_TM_MIXED_MSB_0 and CCMASK_TM_MIXED_MSB_1 (which the
62 // register forms do but the memory forms don't).
65 // Branches if a condition is true. Operand 0 is the chain operand;
66 // operand 1 is the 4-bit condition-code mask, with bit N in
67 // big-endian order meaning "branch if CC=N"; operand 2 is the
68 // target block and operand 3 is the flag operand.
71 // Selects between operand 0 and operand 1. Operand 2 is the
72 // mask of condition-code values for which operand 0 should be
73 // chosen over operand 1; it has the same form as BR_CCMASK.
74 // Operand 3 is the flag operand.
77 // Evaluates to the gap between the stack pointer and the
78 // base of the dynamically-allocatable area.
81 // Extracts the value of a 32-bit access register. Operand 0 is
82 // the number of the register.
85 // Wrappers around the ISD opcodes of the same name. The output and
86 // first input operands are GR128s. The trailing numbers are the
87 // widths of the second operand in bits.
94 // Use a series of MVCs to copy bytes from one memory location to another.
96 // - the target address
97 // - the source address
98 // - the constant length
100 // This isn't a memory opcode because we'd need to attach two
101 // MachineMemOperands rather than one.
104 // Like MVC, but implemented as a loop that handles X*256 bytes
105 // followed by straight-line code to handle the rest (if any).
106 // The value of X is passed as an additional operand.
109 // Similar to MVC and MVC_LOOP, but for logic operations (AND, OR, XOR).
117 // Use CLC to compare two blocks of memory, with the same comments
118 // as for MVC and MVC_LOOP.
122 // Use an MVST-based sequence to implement stpcpy().
125 // Use a CLST-based sequence to implement strcmp(). The two input operands
126 // are the addresses of the strings to compare.
129 // Use an SRST-based sequence to search a block of memory. The first
130 // operand is the end address, the second is the start, and the third
131 // is the character to search for. CC is set to 1 on success and 2
135 // Store the CC value in bits 29 and 28 of an integer.
138 // Perform a serialization operation. (BCR 15,0 or BCR 14,0.)
141 // Wrappers around the inner loop of an 8- or 16-bit ATOMIC_SWAP or
144 // Operand 0: the address of the containing 32-bit-aligned field
145 // Operand 1: the second operand of <op>, in the high bits of an i32
146 // for everything except ATOMIC_SWAPW
147 // Operand 2: how many bits to rotate the i32 left to bring the first
148 // operand into the high bits
149 // Operand 3: the negative of operand 2, for rotating the other way
150 // Operand 4: the width of the field in bits (8 or 16)
151 ATOMIC_SWAPW = ISD::FIRST_TARGET_MEMORY_OPCODE,
163 // A wrapper around the inner loop of an ATOMIC_CMP_SWAP.
165 // Operand 0: the address of the containing 32-bit-aligned field
166 // Operand 1: the compare value, in the low bits of an i32
167 // Operand 2: the swap value, in the low bits of an i32
168 // Operand 3: how many bits to rotate the i32 left to bring the first
169 // operand into the high bits
170 // Operand 4: the negative of operand 2, for rotating the other way
171 // Operand 5: the width of the field in bits (8 or 16)
174 // Prefetch from the second operand using the 4-bit control code in
175 // the first operand. The code is 1 for a load prefetch and 2 for
180 // Return true if OPCODE is some kind of PC-relative address.
181 inline bool isPCREL(unsigned Opcode) {
182 return Opcode == PCREL_WRAPPER || Opcode == PCREL_OFFSET;
186 namespace SystemZICMP {
187 // Describes whether an integer comparison needs to be signed or unsigned,
188 // or whether either type is OK.
196 class SystemZSubtarget;
197 class SystemZTargetMachine;
199 class SystemZTargetLowering : public TargetLowering {
201 explicit SystemZTargetLowering(SystemZTargetMachine &TM);
203 // Override TargetLowering.
204 virtual MVT getScalarShiftAmountTy(EVT LHSTy) const LLVM_OVERRIDE {
207 virtual EVT getSetCCResultType(LLVMContext &, EVT) const LLVM_OVERRIDE;
208 virtual bool isFMAFasterThanFMulAndFAdd(EVT VT) const LLVM_OVERRIDE;
209 virtual bool isFPImmLegal(const APFloat &Imm, EVT VT) const LLVM_OVERRIDE;
210 virtual bool isLegalAddressingMode(const AddrMode &AM, Type *Ty) const
212 virtual bool allowsUnalignedMemoryAccesses(EVT VT, bool *Fast) const
214 virtual bool isTruncateFree(Type *, Type *) const LLVM_OVERRIDE;
215 virtual bool isTruncateFree(EVT, EVT) const LLVM_OVERRIDE;
216 virtual const char *getTargetNodeName(unsigned Opcode) const LLVM_OVERRIDE;
217 virtual std::pair<unsigned, const TargetRegisterClass *>
218 getRegForInlineAsmConstraint(const std::string &Constraint,
219 MVT VT) const LLVM_OVERRIDE;
220 virtual TargetLowering::ConstraintType
221 getConstraintType(const std::string &Constraint) const LLVM_OVERRIDE;
222 virtual TargetLowering::ConstraintWeight
223 getSingleConstraintMatchWeight(AsmOperandInfo &info,
224 const char *constraint) const LLVM_OVERRIDE;
226 LowerAsmOperandForConstraint(SDValue Op,
227 std::string &Constraint,
228 std::vector<SDValue> &Ops,
229 SelectionDAG &DAG) const LLVM_OVERRIDE;
230 virtual MachineBasicBlock *
231 EmitInstrWithCustomInserter(MachineInstr *MI,
232 MachineBasicBlock *BB) const LLVM_OVERRIDE;
233 virtual SDValue LowerOperation(SDValue Op,
234 SelectionDAG &DAG) const LLVM_OVERRIDE;
235 virtual bool allowTruncateForTailCall(Type *, Type *) const LLVM_OVERRIDE;
236 virtual bool mayBeEmittedAsTailCall(CallInst *CI) const LLVM_OVERRIDE;
238 LowerFormalArguments(SDValue Chain,
239 CallingConv::ID CallConv, bool isVarArg,
240 const SmallVectorImpl<ISD::InputArg> &Ins,
241 SDLoc DL, SelectionDAG &DAG,
242 SmallVectorImpl<SDValue> &InVals) const LLVM_OVERRIDE;
244 LowerCall(CallLoweringInfo &CLI,
245 SmallVectorImpl<SDValue> &InVals) const LLVM_OVERRIDE;
248 LowerReturn(SDValue Chain,
249 CallingConv::ID CallConv, bool IsVarArg,
250 const SmallVectorImpl<ISD::OutputArg> &Outs,
251 const SmallVectorImpl<SDValue> &OutVals,
252 SDLoc DL, SelectionDAG &DAG) const LLVM_OVERRIDE;
253 virtual SDValue prepareVolatileOrAtomicLoad(SDValue Chain, SDLoc DL,
254 SelectionDAG &DAG) const
258 const SystemZSubtarget &Subtarget;
259 const SystemZTargetMachine &TM;
261 // Implement LowerOperation for individual opcodes.
262 SDValue lowerSETCC(SDValue Op, SelectionDAG &DAG) const;
263 SDValue lowerBR_CC(SDValue Op, SelectionDAG &DAG) const;
264 SDValue lowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const;
265 SDValue lowerGlobalAddress(GlobalAddressSDNode *Node,
266 SelectionDAG &DAG) const;
267 SDValue lowerGlobalTLSAddress(GlobalAddressSDNode *Node,
268 SelectionDAG &DAG) const;
269 SDValue lowerBlockAddress(BlockAddressSDNode *Node,
270 SelectionDAG &DAG) const;
271 SDValue lowerJumpTable(JumpTableSDNode *JT, SelectionDAG &DAG) const;
272 SDValue lowerConstantPool(ConstantPoolSDNode *CP, SelectionDAG &DAG) const;
273 SDValue lowerVASTART(SDValue Op, SelectionDAG &DAG) const;
274 SDValue lowerVACOPY(SDValue Op, SelectionDAG &DAG) const;
275 SDValue lowerDYNAMIC_STACKALLOC(SDValue Op, SelectionDAG &DAG) const;
276 SDValue lowerSMUL_LOHI(SDValue Op, SelectionDAG &DAG) const;
277 SDValue lowerUMUL_LOHI(SDValue Op, SelectionDAG &DAG) const;
278 SDValue lowerSDIVREM(SDValue Op, SelectionDAG &DAG) const;
279 SDValue lowerUDIVREM(SDValue Op, SelectionDAG &DAG) const;
280 SDValue lowerBITCAST(SDValue Op, SelectionDAG &DAG) const;
281 SDValue lowerOR(SDValue Op, SelectionDAG &DAG) const;
282 SDValue lowerSIGN_EXTEND(SDValue Op, SelectionDAG &DAG) const;
283 SDValue lowerATOMIC_LOAD(SDValue Op, SelectionDAG &DAG) const;
284 SDValue lowerATOMIC_STORE(SDValue Op, SelectionDAG &DAG) const;
285 SDValue lowerATOMIC_LOAD_OP(SDValue Op, SelectionDAG &DAG,
286 unsigned Opcode) const;
287 SDValue lowerATOMIC_LOAD_SUB(SDValue Op, SelectionDAG &DAG) const;
288 SDValue lowerATOMIC_CMP_SWAP(SDValue Op, SelectionDAG &DAG) const;
289 SDValue lowerLOAD_SEQUENCE_POINT(SDValue Op, SelectionDAG &DAG) const;
290 SDValue lowerSTACKSAVE(SDValue Op, SelectionDAG &DAG) const;
291 SDValue lowerSTACKRESTORE(SDValue Op, SelectionDAG &DAG) const;
292 SDValue lowerPREFETCH(SDValue Op, SelectionDAG &DAG) const;
294 // If the last instruction before MBBI in MBB was some form of COMPARE,
295 // try to replace it with a COMPARE AND BRANCH just before MBBI.
296 // CCMask and Target are the BRC-like operands for the branch.
297 // Return true if the change was made.
298 bool convertPrevCompareToBranch(MachineBasicBlock *MBB,
299 MachineBasicBlock::iterator MBBI,
301 MachineBasicBlock *Target) const;
303 // Implement EmitInstrWithCustomInserter for individual operation types.
304 MachineBasicBlock *emitSelect(MachineInstr *MI,
305 MachineBasicBlock *BB) const;
306 MachineBasicBlock *emitCondStore(MachineInstr *MI,
307 MachineBasicBlock *BB,
308 unsigned StoreOpcode, unsigned STOCOpcode,
310 MachineBasicBlock *emitExt128(MachineInstr *MI,
311 MachineBasicBlock *MBB,
312 bool ClearEven, unsigned SubReg) const;
313 MachineBasicBlock *emitAtomicLoadBinary(MachineInstr *MI,
314 MachineBasicBlock *BB,
315 unsigned BinOpcode, unsigned BitSize,
316 bool Invert = false) const;
317 MachineBasicBlock *emitAtomicLoadMinMax(MachineInstr *MI,
318 MachineBasicBlock *MBB,
319 unsigned CompareOpcode,
320 unsigned KeepOldMask,
321 unsigned BitSize) const;
322 MachineBasicBlock *emitAtomicCmpSwapW(MachineInstr *MI,
323 MachineBasicBlock *BB) const;
324 MachineBasicBlock *emitMemMemWrapper(MachineInstr *MI,
325 MachineBasicBlock *BB,
326 unsigned Opcode) const;
327 MachineBasicBlock *emitStringWrapper(MachineInstr *MI,
328 MachineBasicBlock *BB,
329 unsigned Opcode) const;
331 } // end namespace llvm
333 #endif // LLVM_TARGET_SystemZ_ISELLOWERING_H