1 //===-- SystemZISelLowering.h - SystemZ DAG lowering interface --*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines the interfaces that SystemZ uses to lower LLVM code into a
13 //===----------------------------------------------------------------------===//
15 #ifndef LLVM_TARGET_SystemZ_ISELLOWERING_H
16 #define LLVM_TARGET_SystemZ_ISELLOWERING_H
19 #include "llvm/CodeGen/MachineBasicBlock.h"
20 #include "llvm/CodeGen/SelectionDAG.h"
21 #include "llvm/Target/TargetLowering.h"
24 namespace SystemZISD {
26 FIRST_NUMBER = ISD::BUILTIN_OP_END,
28 // Return with a flag operand. Operand 0 is the chain operand.
31 // Calls a function. Operand 0 is the chain operand and operand 1
32 // is the target address. The arguments start at operand 2.
33 // There is an optional glue operand at the end.
36 // Wraps a TargetGlobalAddress that should be loaded using PC-relative
37 // accesses (LARL). Operand 0 is the address.
40 // Signed integer and floating-point comparisons. The operands are the
41 // two values to compare.
44 // Likewise unsigned integer comparison.
47 // Branches if a condition is true. Operand 0 is the chain operand;
48 // operand 1 is the 4-bit condition-code mask, with bit N in
49 // big-endian order meaning "branch if CC=N"; operand 2 is the
50 // target block and operand 3 is the flag operand.
53 // Selects between operand 0 and operand 1. Operand 2 is the
54 // mask of condition-code values for which operand 0 should be
55 // chosen over operand 1; it has the same form as BR_CCMASK.
56 // Operand 3 is the flag operand.
59 // Evaluates to the gap between the stack pointer and the
60 // base of the dynamically-allocatable area.
63 // Extracts the value of a 32-bit access register. Operand 0 is
64 // the number of the register.
67 // Wrappers around the ISD opcodes of the same name. The output and
68 // first input operands are GR128s. The trailing numbers are the
69 // widths of the second operand in bits.
76 // Use MVC to copy bytes from one memory location to another.
77 // The first operand is the target address, the second operand is the
78 // source address, and the third operand is the constant length.
79 // This isn't a memory opcode because we'd need to attach two
80 // MachineMemOperands rather than one.
83 // Use CLC to compare two blocks of memory, with the same comments
87 // Store the CC value in bits 29 and 28 of an integer.
90 // Wrappers around the inner loop of an 8- or 16-bit ATOMIC_SWAP or
93 // Operand 0: the address of the containing 32-bit-aligned field
94 // Operand 1: the second operand of <op>, in the high bits of an i32
95 // for everything except ATOMIC_SWAPW
96 // Operand 2: how many bits to rotate the i32 left to bring the first
97 // operand into the high bits
98 // Operand 3: the negative of operand 2, for rotating the other way
99 // Operand 4: the width of the field in bits (8 or 16)
100 ATOMIC_SWAPW = ISD::FIRST_TARGET_MEMORY_OPCODE,
112 // A wrapper around the inner loop of an ATOMIC_CMP_SWAP.
114 // Operand 0: the address of the containing 32-bit-aligned field
115 // Operand 1: the compare value, in the low bits of an i32
116 // Operand 2: the swap value, in the low bits of an i32
117 // Operand 3: how many bits to rotate the i32 left to bring the first
118 // operand into the high bits
119 // Operand 4: the negative of operand 2, for rotating the other way
120 // Operand 5: the width of the field in bits (8 or 16)
125 class SystemZSubtarget;
126 class SystemZTargetMachine;
128 class SystemZTargetLowering : public TargetLowering {
130 explicit SystemZTargetLowering(SystemZTargetMachine &TM);
132 // Override TargetLowering.
133 virtual MVT getScalarShiftAmountTy(EVT LHSTy) const LLVM_OVERRIDE {
136 virtual EVT getSetCCResultType(LLVMContext &, EVT) const LLVM_OVERRIDE {
139 virtual bool isFMAFasterThanFMulAndFAdd(EVT VT) const LLVM_OVERRIDE;
140 virtual bool isFPImmLegal(const APFloat &Imm, EVT VT) const LLVM_OVERRIDE;
141 virtual bool isLegalAddressingMode(const AddrMode &AM, Type *Ty) const
143 virtual bool allowsUnalignedMemoryAccesses(EVT VT, bool *Fast) const
145 virtual const char *getTargetNodeName(unsigned Opcode) const LLVM_OVERRIDE;
146 virtual std::pair<unsigned, const TargetRegisterClass *>
147 getRegForInlineAsmConstraint(const std::string &Constraint,
148 MVT VT) const LLVM_OVERRIDE;
149 virtual TargetLowering::ConstraintType
150 getConstraintType(const std::string &Constraint) const LLVM_OVERRIDE;
151 virtual TargetLowering::ConstraintWeight
152 getSingleConstraintMatchWeight(AsmOperandInfo &info,
153 const char *constraint) const LLVM_OVERRIDE;
155 LowerAsmOperandForConstraint(SDValue Op,
156 std::string &Constraint,
157 std::vector<SDValue> &Ops,
158 SelectionDAG &DAG) const LLVM_OVERRIDE;
159 virtual MachineBasicBlock *
160 EmitInstrWithCustomInserter(MachineInstr *MI,
161 MachineBasicBlock *BB) const LLVM_OVERRIDE;
162 virtual SDValue LowerOperation(SDValue Op,
163 SelectionDAG &DAG) const LLVM_OVERRIDE;
165 LowerFormalArguments(SDValue Chain,
166 CallingConv::ID CallConv, bool isVarArg,
167 const SmallVectorImpl<ISD::InputArg> &Ins,
168 SDLoc DL, SelectionDAG &DAG,
169 SmallVectorImpl<SDValue> &InVals) const LLVM_OVERRIDE;
171 LowerCall(CallLoweringInfo &CLI,
172 SmallVectorImpl<SDValue> &InVals) const LLVM_OVERRIDE;
175 LowerReturn(SDValue Chain,
176 CallingConv::ID CallConv, bool IsVarArg,
177 const SmallVectorImpl<ISD::OutputArg> &Outs,
178 const SmallVectorImpl<SDValue> &OutVals,
179 SDLoc DL, SelectionDAG &DAG) const LLVM_OVERRIDE;
182 const SystemZSubtarget &Subtarget;
183 const SystemZTargetMachine &TM;
185 // Implement LowerOperation for individual opcodes.
186 SDValue lowerBR_CC(SDValue Op, SelectionDAG &DAG) const;
187 SDValue lowerSELECT_CC(SDValue Op, SelectionDAG &DAG) const;
188 SDValue lowerGlobalAddress(GlobalAddressSDNode *Node,
189 SelectionDAG &DAG) const;
190 SDValue lowerGlobalTLSAddress(GlobalAddressSDNode *Node,
191 SelectionDAG &DAG) const;
192 SDValue lowerBlockAddress(BlockAddressSDNode *Node,
193 SelectionDAG &DAG) const;
194 SDValue lowerJumpTable(JumpTableSDNode *JT, SelectionDAG &DAG) const;
195 SDValue lowerConstantPool(ConstantPoolSDNode *CP, SelectionDAG &DAG) const;
196 SDValue lowerVASTART(SDValue Op, SelectionDAG &DAG) const;
197 SDValue lowerVACOPY(SDValue Op, SelectionDAG &DAG) const;
198 SDValue lowerDYNAMIC_STACKALLOC(SDValue Op, SelectionDAG &DAG) const;
199 SDValue lowerUMUL_LOHI(SDValue Op, SelectionDAG &DAG) const;
200 SDValue lowerSDIVREM(SDValue Op, SelectionDAG &DAG) const;
201 SDValue lowerUDIVREM(SDValue Op, SelectionDAG &DAG) const;
202 SDValue lowerBITCAST(SDValue Op, SelectionDAG &DAG) const;
203 SDValue lowerOR(SDValue Op, SelectionDAG &DAG) const;
204 SDValue lowerATOMIC_LOAD(SDValue Op, SelectionDAG &DAG,
205 unsigned Opcode) const;
206 SDValue lowerATOMIC_CMP_SWAP(SDValue Op, SelectionDAG &DAG) const;
207 SDValue lowerSTACKSAVE(SDValue Op, SelectionDAG &DAG) const;
208 SDValue lowerSTACKRESTORE(SDValue Op, SelectionDAG &DAG) const;
210 // If the last instruction before MBBI in MBB was some form of COMPARE,
211 // try to replace it with a COMPARE AND BRANCH just before MBBI.
212 // CCMask and Target are the BRC-like operands for the branch.
213 // Return true if the change was made.
214 bool convertPrevCompareToBranch(MachineBasicBlock *MBB,
215 MachineBasicBlock::iterator MBBI,
217 MachineBasicBlock *Target) const;
219 // Implement EmitInstrWithCustomInserter for individual operation types.
220 MachineBasicBlock *emitSelect(MachineInstr *MI,
221 MachineBasicBlock *BB) const;
222 MachineBasicBlock *emitCondStore(MachineInstr *MI,
223 MachineBasicBlock *BB,
224 unsigned StoreOpcode, unsigned STOCOpcode,
226 MachineBasicBlock *emitExt128(MachineInstr *MI,
227 MachineBasicBlock *MBB,
228 bool ClearEven, unsigned SubReg) const;
229 MachineBasicBlock *emitAtomicLoadBinary(MachineInstr *MI,
230 MachineBasicBlock *BB,
231 unsigned BinOpcode, unsigned BitSize,
232 bool Invert = false) const;
233 MachineBasicBlock *emitAtomicLoadMinMax(MachineInstr *MI,
234 MachineBasicBlock *MBB,
235 unsigned CompareOpcode,
236 unsigned KeepOldMask,
237 unsigned BitSize) const;
238 MachineBasicBlock *emitAtomicCmpSwapW(MachineInstr *MI,
239 MachineBasicBlock *BB) const;
240 MachineBasicBlock *emitMemMemWrapper(MachineInstr *MI,
241 MachineBasicBlock *BB,
242 unsigned Opcode) const;
244 } // end namespace llvm
246 #endif // LLVM_TARGET_SystemZ_ISELLOWERING_H