1 //===-- SystemZISelLowering.cpp - SystemZ DAG Lowering Implementation -----==//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements the SystemZTargetLowering class.
12 //===----------------------------------------------------------------------===//
14 #define DEBUG_TYPE "systemz-lower"
16 #include "SystemZISelLowering.h"
18 #include "SystemZTargetMachine.h"
19 #include "SystemZSubtarget.h"
20 #include "llvm/DerivedTypes.h"
21 #include "llvm/Function.h"
22 #include "llvm/Intrinsics.h"
23 #include "llvm/CallingConv.h"
24 #include "llvm/GlobalVariable.h"
25 #include "llvm/GlobalAlias.h"
26 #include "llvm/CodeGen/CallingConvLower.h"
27 #include "llvm/CodeGen/MachineFrameInfo.h"
28 #include "llvm/CodeGen/MachineFunction.h"
29 #include "llvm/CodeGen/MachineInstrBuilder.h"
30 #include "llvm/CodeGen/MachineRegisterInfo.h"
31 #include "llvm/CodeGen/PseudoSourceValue.h"
32 #include "llvm/CodeGen/SelectionDAGISel.h"
33 #include "llvm/CodeGen/ValueTypes.h"
34 #include "llvm/Support/Debug.h"
35 #include "llvm/ADT/VectorExtras.h"
38 SystemZTargetLowering::SystemZTargetLowering(SystemZTargetMachine &tm) :
39 TargetLowering(tm), Subtarget(*tm.getSubtargetImpl()), TM(tm) {
41 // Set up the register classes.
42 addRegisterClass(MVT::i32, SystemZ::GR32RegisterClass);
43 addRegisterClass(MVT::i64, SystemZ::GR64RegisterClass);
45 // Compute derived properties from the register classes
46 computeRegisterProperties();
48 // Set shifts properties
49 setShiftAmountFlavor(Extend);
50 setShiftAmountType(MVT::i32);
52 // Provide all sorts of operation actions
54 setStackPointerRegisterToSaveRestore(SystemZ::R15D);
55 setSchedulingPreference(SchedulingForLatency);
57 setOperationAction(ISD::RET, MVT::Other, Custom);
61 SDValue SystemZTargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) {
62 switch (Op.getOpcode()) {
63 case ISD::FORMAL_ARGUMENTS: return LowerFORMAL_ARGUMENTS(Op, DAG);
64 case ISD::RET: return LowerRET(Op, DAG);
66 assert(0 && "unimplemented operand");
71 //===----------------------------------------------------------------------===//
72 // Calling Convention Implementation
73 //===----------------------------------------------------------------------===//
75 #include "SystemZGenCallingConv.inc"
77 SDValue SystemZTargetLowering::LowerFORMAL_ARGUMENTS(SDValue Op,
79 unsigned CC = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
82 assert(0 && "Unsupported calling convention");
84 case CallingConv::Fast:
85 return LowerCCCArguments(Op, DAG);
89 /// LowerCCCArguments - transform physical registers into virtual registers and
90 /// generate load operations for arguments places on the stack.
91 // FIXME: struct return stuff
93 SDValue SystemZTargetLowering::LowerCCCArguments(SDValue Op,
95 MachineFunction &MF = DAG.getMachineFunction();
96 MachineFrameInfo *MFI = MF.getFrameInfo();
97 MachineRegisterInfo &RegInfo = MF.getRegInfo();
98 SDValue Root = Op.getOperand(0);
99 bool isVarArg = cast<ConstantSDNode>(Op.getOperand(2))->getZExtValue() != 0;
100 unsigned CC = MF.getFunction()->getCallingConv();
101 DebugLoc dl = Op.getDebugLoc();
103 // Assign locations to all of the incoming arguments.
104 SmallVector<CCValAssign, 16> ArgLocs;
105 CCState CCInfo(CC, isVarArg, getTargetMachine(), ArgLocs);
106 CCInfo.AnalyzeFormalArguments(Op.getNode(), CC_SystemZ);
108 assert(!isVarArg && "Varargs not supported yet");
110 SmallVector<SDValue, 16> ArgValues;
111 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
112 CCValAssign &VA = ArgLocs[i];
114 // Arguments passed in registers
115 MVT RegVT = VA.getLocVT();
116 switch (RegVT.getSimpleVT()) {
118 cerr << "LowerFORMAL_ARGUMENTS Unhandled argument type: "
119 << RegVT.getSimpleVT()
124 RegInfo.createVirtualRegister(SystemZ::GR64RegisterClass);
125 RegInfo.addLiveIn(VA.getLocReg(), VReg);
126 SDValue ArgValue = DAG.getCopyFromReg(Root, dl, VReg, RegVT);
128 // If this is an 8/16/32-bit value, it is really passed promoted to 64
129 // bits. Insert an assert[sz]ext to capture this, then truncate to the
131 if (VA.getLocInfo() == CCValAssign::SExt)
132 ArgValue = DAG.getNode(ISD::AssertSext, dl, RegVT, ArgValue,
133 DAG.getValueType(VA.getValVT()));
134 else if (VA.getLocInfo() == CCValAssign::ZExt)
135 ArgValue = DAG.getNode(ISD::AssertZext, dl, RegVT, ArgValue,
136 DAG.getValueType(VA.getValVT()));
138 if (VA.getLocInfo() != CCValAssign::Full)
139 ArgValue = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), ArgValue);
141 ArgValues.push_back(ArgValue);
145 assert(VA.isMemLoc());
146 // Load the argument to a virtual register
147 unsigned ObjSize = VA.getLocVT().getSizeInBits()/8;
149 cerr << "LowerFORMAL_ARGUMENTS Unhandled argument type: "
150 << VA.getLocVT().getSimpleVT()
153 // Create the frame index object for this incoming parameter...
154 int FI = MFI->CreateFixedObject(ObjSize, VA.getLocMemOffset());
156 // Create the SelectionDAG nodes corresponding to a load
157 //from this parameter
158 SDValue FIN = DAG.getFrameIndex(FI, MVT::i64);
159 ArgValues.push_back(DAG.getLoad(VA.getLocVT(), dl, Root, FIN,
160 PseudoSourceValue::getFixedStack(FI), 0));
164 ArgValues.push_back(Root);
166 // Return the new list of results.
167 return DAG.getNode(ISD::MERGE_VALUES, dl, Op.getNode()->getVTList(),
168 &ArgValues[0], ArgValues.size()).getValue(Op.getResNo());
171 SDValue SystemZTargetLowering::LowerRET(SDValue Op, SelectionDAG &DAG) {
172 // CCValAssign - represent the assignment of the return value to a location
173 SmallVector<CCValAssign, 16> RVLocs;
174 unsigned CC = DAG.getMachineFunction().getFunction()->getCallingConv();
175 bool isVarArg = DAG.getMachineFunction().getFunction()->isVarArg();
176 DebugLoc dl = Op.getDebugLoc();
178 // CCState - Info about the registers and stack slot.
179 CCState CCInfo(CC, isVarArg, getTargetMachine(), RVLocs);
181 // Analize return values of ISD::RET
182 CCInfo.AnalyzeReturn(Op.getNode(), RetCC_SystemZ);
184 // If this is the first return lowered for this function, add the regs to the
185 // liveout set for the function.
186 if (DAG.getMachineFunction().getRegInfo().liveout_empty()) {
187 for (unsigned i = 0; i != RVLocs.size(); ++i)
188 if (RVLocs[i].isRegLoc())
189 DAG.getMachineFunction().getRegInfo().addLiveOut(RVLocs[i].getLocReg());
192 // The chain is always operand #0
193 SDValue Chain = Op.getOperand(0);
196 // Copy the result values into the output registers.
197 for (unsigned i = 0; i != RVLocs.size(); ++i) {
198 CCValAssign &VA = RVLocs[i];
199 SDValue ResValue = Op.getOperand(i*2+1);
200 assert(VA.isRegLoc() && "Can only return in registers!");
202 // If this is an 8/16/32-bit value, it is really should be passed promoted
204 if (VA.getLocInfo() == CCValAssign::SExt)
205 ResValue = DAG.getNode(ISD::SIGN_EXTEND, dl, VA.getLocVT(), ResValue);
206 else if (VA.getLocInfo() == CCValAssign::ZExt)
207 ResValue = DAG.getNode(ISD::ZERO_EXTEND, dl, VA.getLocVT(), ResValue);
208 else if (VA.getLocInfo() == CCValAssign::AExt)
209 ResValue = DAG.getNode(ISD::ANY_EXTEND, dl, VA.getLocVT(), ResValue);
211 // ISD::RET => ret chain, (regnum1,val1), ...
212 // So i*2+1 index only the regnums
213 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), ResValue, Flag);
215 // Guarantee that all emitted copies are stuck together,
216 // avoiding something bad.
217 Flag = Chain.getValue(1);
221 return DAG.getNode(SystemZISD::RET_FLAG, dl, MVT::Other, Chain, Flag);
224 return DAG.getNode(SystemZISD::RET_FLAG, dl, MVT::Other, Chain);
227 const char *SystemZTargetLowering::getTargetNodeName(unsigned Opcode) const {
229 case SystemZISD::RET_FLAG: return "SystemZISD::RET_FLAG";
230 default: return NULL;