1 //===-- SystemZISelLowering.cpp - SystemZ DAG Lowering Implementation -----==//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements the SystemZTargetLowering class.
12 //===----------------------------------------------------------------------===//
14 #define DEBUG_TYPE "systemz-lower"
16 #include "SystemZISelLowering.h"
18 #include "SystemZTargetMachine.h"
19 #include "SystemZSubtarget.h"
20 #include "llvm/DerivedTypes.h"
21 #include "llvm/Function.h"
22 #include "llvm/Intrinsics.h"
23 #include "llvm/CallingConv.h"
24 #include "llvm/GlobalVariable.h"
25 #include "llvm/GlobalAlias.h"
26 #include "llvm/CodeGen/CallingConvLower.h"
27 #include "llvm/CodeGen/MachineFrameInfo.h"
28 #include "llvm/CodeGen/MachineFunction.h"
29 #include "llvm/CodeGen/MachineInstrBuilder.h"
30 #include "llvm/CodeGen/MachineRegisterInfo.h"
31 #include "llvm/CodeGen/PseudoSourceValue.h"
32 #include "llvm/CodeGen/SelectionDAGISel.h"
33 #include "llvm/CodeGen/ValueTypes.h"
34 #include "llvm/Support/Debug.h"
35 #include "llvm/ADT/VectorExtras.h"
38 SystemZTargetLowering::SystemZTargetLowering(SystemZTargetMachine &tm) :
39 TargetLowering(tm), Subtarget(*tm.getSubtargetImpl()), TM(tm) {
41 RegInfo = TM.getRegisterInfo();
43 // Set up the register classes.
44 addRegisterClass(MVT::i32, SystemZ::GR32RegisterClass);
45 addRegisterClass(MVT::i64, SystemZ::GR64RegisterClass);
46 addRegisterClass(MVT::i128, SystemZ::GR128RegisterClass);
48 // Compute derived properties from the register classes
49 computeRegisterProperties();
51 // Set shifts properties
52 setShiftAmountFlavor(Extend);
53 setShiftAmountType(MVT::i32);
55 // Provide all sorts of operation actions
56 setLoadExtAction(ISD::SEXTLOAD, MVT::i1, Promote);
57 setLoadExtAction(ISD::ZEXTLOAD, MVT::i1, Promote);
58 setLoadExtAction(ISD::EXTLOAD, MVT::i1, Promote);
60 setStackPointerRegisterToSaveRestore(SystemZ::R15D);
61 setSchedulingPreference(SchedulingForLatency);
63 setOperationAction(ISD::RET, MVT::Other, Custom);
65 setOperationAction(ISD::BR_JT, MVT::Other, Expand);
66 setOperationAction(ISD::BRCOND, MVT::Other, Expand);
67 setOperationAction(ISD::BR_CC, MVT::i32, Custom);
68 setOperationAction(ISD::BR_CC, MVT::i64, Custom);
69 setOperationAction(ISD::GlobalAddress, MVT::i64, Custom);
70 setOperationAction(ISD::JumpTable, MVT::i64, Custom);
71 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i64, Expand);
73 // FIXME: Can we lower these 2 efficiently?
74 setOperationAction(ISD::SETCC, MVT::i32, Expand);
75 setOperationAction(ISD::SETCC, MVT::i64, Expand);
76 setOperationAction(ISD::SELECT, MVT::i32, Expand);
77 setOperationAction(ISD::SELECT, MVT::i64, Expand);
78 setOperationAction(ISD::SELECT_CC, MVT::i32, Custom);
79 setOperationAction(ISD::SELECT_CC, MVT::i64, Custom);
81 // Funny enough: we don't have 64-bit signed versions of these stuff, but have
83 setOperationAction(ISD::MULHS, MVT::i64, Expand);
84 setOperationAction(ISD::SMUL_LOHI, MVT::i64, Expand);
87 SDValue SystemZTargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) {
88 switch (Op.getOpcode()) {
89 case ISD::FORMAL_ARGUMENTS: return LowerFORMAL_ARGUMENTS(Op, DAG);
90 case ISD::RET: return LowerRET(Op, DAG);
91 case ISD::CALL: return LowerCALL(Op, DAG);
92 case ISD::BR_CC: return LowerBR_CC(Op, DAG);
93 case ISD::SELECT_CC: return LowerSELECT_CC(Op, DAG);
94 case ISD::GlobalAddress: return LowerGlobalAddress(Op, DAG);
95 case ISD::JumpTable: return LowerJumpTable(Op, DAG);
97 assert(0 && "unimplemented operand");
102 //===----------------------------------------------------------------------===//
103 // Calling Convention Implementation
104 //===----------------------------------------------------------------------===//
106 #include "SystemZGenCallingConv.inc"
108 SDValue SystemZTargetLowering::LowerFORMAL_ARGUMENTS(SDValue Op,
110 unsigned CC = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
113 assert(0 && "Unsupported calling convention");
115 case CallingConv::Fast:
116 return LowerCCCArguments(Op, DAG);
120 SDValue SystemZTargetLowering::LowerCALL(SDValue Op, SelectionDAG &DAG) {
121 CallSDNode *TheCall = cast<CallSDNode>(Op.getNode());
122 unsigned CallingConv = TheCall->getCallingConv();
123 switch (CallingConv) {
125 assert(0 && "Unsupported calling convention");
126 case CallingConv::Fast:
128 return LowerCCCCallTo(Op, DAG, CallingConv);
132 /// LowerCCCArguments - transform physical registers into virtual registers and
133 /// generate load operations for arguments places on the stack.
134 // FIXME: struct return stuff
136 SDValue SystemZTargetLowering::LowerCCCArguments(SDValue Op,
138 MachineFunction &MF = DAG.getMachineFunction();
139 MachineFrameInfo *MFI = MF.getFrameInfo();
140 MachineRegisterInfo &RegInfo = MF.getRegInfo();
141 SDValue Root = Op.getOperand(0);
142 bool isVarArg = cast<ConstantSDNode>(Op.getOperand(2))->getZExtValue() != 0;
143 unsigned CC = MF.getFunction()->getCallingConv();
144 DebugLoc dl = Op.getDebugLoc();
146 // Assign locations to all of the incoming arguments.
147 SmallVector<CCValAssign, 16> ArgLocs;
148 CCState CCInfo(CC, isVarArg, getTargetMachine(), ArgLocs);
149 CCInfo.AnalyzeFormalArguments(Op.getNode(), CC_SystemZ);
151 assert(!isVarArg && "Varargs not supported yet");
153 SmallVector<SDValue, 16> ArgValues;
154 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
155 CCValAssign &VA = ArgLocs[i];
157 // Arguments passed in registers
158 MVT RegVT = VA.getLocVT();
159 switch (RegVT.getSimpleVT()) {
161 cerr << "LowerFORMAL_ARGUMENTS Unhandled argument type: "
162 << RegVT.getSimpleVT()
167 RegInfo.createVirtualRegister(SystemZ::GR64RegisterClass);
168 RegInfo.addLiveIn(VA.getLocReg(), VReg);
169 SDValue ArgValue = DAG.getCopyFromReg(Root, dl, VReg, RegVT);
171 // If this is an 8/16/32-bit value, it is really passed promoted to 64
172 // bits. Insert an assert[sz]ext to capture this, then truncate to the
174 if (VA.getLocInfo() == CCValAssign::SExt)
175 ArgValue = DAG.getNode(ISD::AssertSext, dl, RegVT, ArgValue,
176 DAG.getValueType(VA.getValVT()));
177 else if (VA.getLocInfo() == CCValAssign::ZExt)
178 ArgValue = DAG.getNode(ISD::AssertZext, dl, RegVT, ArgValue,
179 DAG.getValueType(VA.getValVT()));
181 if (VA.getLocInfo() != CCValAssign::Full)
182 ArgValue = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), ArgValue);
184 ArgValues.push_back(ArgValue);
188 assert(VA.isMemLoc());
190 // Create the nodes corresponding to a load from this parameter slot.
191 // Create the frame index object for this incoming parameter...
192 int FI = MFI->CreateFixedObject(VA.getValVT().getSizeInBits()/8,
193 VA.getLocMemOffset());
195 // Create the SelectionDAG nodes corresponding to a load
196 //from this parameter
197 SDValue FIN = DAG.getFrameIndex(FI, getPointerTy());
198 ArgValues.push_back(DAG.getLoad(VA.getValVT(), dl, Root, FIN,
199 PseudoSourceValue::getFixedStack(FI), 0));
203 ArgValues.push_back(Root);
205 // Return the new list of results.
206 return DAG.getNode(ISD::MERGE_VALUES, dl, Op.getNode()->getVTList(),
207 &ArgValues[0], ArgValues.size()).getValue(Op.getResNo());
210 /// LowerCCCCallTo - functions arguments are copied from virtual regs to
211 /// (physical regs)/(stack frame), CALLSEQ_START and CALLSEQ_END are emitted.
213 SDValue SystemZTargetLowering::LowerCCCCallTo(SDValue Op, SelectionDAG &DAG,
215 CallSDNode *TheCall = cast<CallSDNode>(Op.getNode());
216 SDValue Chain = TheCall->getChain();
217 SDValue Callee = TheCall->getCallee();
218 bool isVarArg = TheCall->isVarArg();
219 DebugLoc dl = Op.getDebugLoc();
220 MachineFunction &MF = DAG.getMachineFunction();
222 // Offset to first argument stack slot.
223 const unsigned FirstArgOffset = 160;
225 // Analyze operands of the call, assigning locations to each operand.
226 SmallVector<CCValAssign, 16> ArgLocs;
227 CCState CCInfo(CC, isVarArg, getTargetMachine(), ArgLocs);
229 CCInfo.AnalyzeCallOperands(TheCall, CC_SystemZ);
231 // Get a count of how many bytes are to be pushed on the stack.
232 unsigned NumBytes = CCInfo.getNextStackOffset();
234 Chain = DAG.getCALLSEQ_START(Chain ,DAG.getConstant(NumBytes,
235 getPointerTy(), true));
237 SmallVector<std::pair<unsigned, SDValue>, 4> RegsToPass;
238 SmallVector<SDValue, 12> MemOpChains;
241 // Walk the register/memloc assignments, inserting copies/loads.
242 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
243 CCValAssign &VA = ArgLocs[i];
245 // Arguments start after the 5 first operands of ISD::CALL
246 SDValue Arg = TheCall->getArg(i);
248 // Promote the value if needed.
249 switch (VA.getLocInfo()) {
250 default: assert(0 && "Unknown loc info!");
251 case CCValAssign::Full: break;
252 case CCValAssign::SExt:
253 Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, VA.getLocVT(), Arg);
255 case CCValAssign::ZExt:
256 Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, VA.getLocVT(), Arg);
258 case CCValAssign::AExt:
259 Arg = DAG.getNode(ISD::ANY_EXTEND, dl, VA.getLocVT(), Arg);
263 // Arguments that can be passed on register must be kept at RegsToPass
266 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg));
268 assert(VA.isMemLoc());
270 if (StackPtr.getNode() == 0)
272 DAG.getCopyFromReg(Chain, dl,
273 (RegInfo->hasFP(MF) ?
274 SystemZ::R11D : SystemZ::R15D),
277 unsigned Offset = FirstArgOffset + VA.getLocMemOffset();
278 SDValue PtrOff = DAG.getNode(ISD::ADD, dl, getPointerTy(),
280 DAG.getIntPtrConstant(Offset));
282 MemOpChains.push_back(DAG.getStore(Chain, dl, Arg, PtrOff,
283 PseudoSourceValue::getStack(), Offset));
287 // Transform all store nodes into one single node because all store nodes are
288 // independent of each other.
289 if (!MemOpChains.empty())
290 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
291 &MemOpChains[0], MemOpChains.size());
293 // Build a sequence of copy-to-reg nodes chained together with token chain and
294 // flag operands which copy the outgoing args into registers. The InFlag in
295 // necessary since all emited instructions must be stuck together.
297 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
298 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
299 RegsToPass[i].second, InFlag);
300 InFlag = Chain.getValue(1);
303 // If the callee is a GlobalAddress node (quite common, every direct call is)
304 // turn it into a TargetGlobalAddress node so that legalize doesn't hack it.
305 // Likewise ExternalSymbol -> TargetExternalSymbol.
306 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee))
307 Callee = DAG.getTargetGlobalAddress(G->getGlobal(), getPointerTy());
308 else if (ExternalSymbolSDNode *E = dyn_cast<ExternalSymbolSDNode>(Callee))
309 Callee = DAG.getTargetExternalSymbol(E->getSymbol(), getPointerTy());
311 // Returns a chain & a flag for retval copy to use.
312 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Flag);
313 SmallVector<SDValue, 8> Ops;
314 Ops.push_back(Chain);
315 Ops.push_back(Callee);
317 // Add argument registers to the end of the list so that they are
318 // known live into the call.
319 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i)
320 Ops.push_back(DAG.getRegister(RegsToPass[i].first,
321 RegsToPass[i].second.getValueType()));
323 if (InFlag.getNode())
324 Ops.push_back(InFlag);
326 Chain = DAG.getNode(SystemZISD::CALL, dl, NodeTys, &Ops[0], Ops.size());
327 InFlag = Chain.getValue(1);
329 // Create the CALLSEQ_END node.
330 Chain = DAG.getCALLSEQ_END(Chain,
331 DAG.getConstant(NumBytes, getPointerTy(), true),
332 DAG.getConstant(0, getPointerTy(), true),
334 InFlag = Chain.getValue(1);
336 // Handle result values, copying them out of physregs into vregs that we
338 return SDValue(LowerCallResult(Chain, InFlag, TheCall, CC, DAG),
342 /// LowerCallResult - Lower the result values of an ISD::CALL into the
343 /// appropriate copies out of appropriate physical registers. This assumes that
344 /// Chain/InFlag are the input chain/flag to use, and that TheCall is the call
345 /// being lowered. Returns a SDNode with the same number of values as the
348 SystemZTargetLowering::LowerCallResult(SDValue Chain, SDValue InFlag,
350 unsigned CallingConv,
352 bool isVarArg = TheCall->isVarArg();
353 DebugLoc dl = TheCall->getDebugLoc();
355 // Assign locations to each value returned by this call.
356 SmallVector<CCValAssign, 16> RVLocs;
357 CCState CCInfo(CallingConv, isVarArg, getTargetMachine(), RVLocs);
359 CCInfo.AnalyzeCallResult(TheCall, RetCC_SystemZ);
360 SmallVector<SDValue, 8> ResultVals;
362 // Copy all of the result registers out of their specified physreg.
363 for (unsigned i = 0; i != RVLocs.size(); ++i) {
364 CCValAssign &VA = RVLocs[i];
366 Chain = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(),
367 VA.getLocVT(), InFlag).getValue(1);
368 SDValue RetValue = Chain.getValue(0);
369 InFlag = Chain.getValue(2);
371 // If this is an 8/16/32-bit value, it is really passed promoted to 64
372 // bits. Insert an assert[sz]ext to capture this, then truncate to the
374 if (VA.getLocInfo() == CCValAssign::SExt)
375 RetValue = DAG.getNode(ISD::AssertSext, dl, VA.getLocVT(), RetValue,
376 DAG.getValueType(VA.getValVT()));
377 else if (VA.getLocInfo() == CCValAssign::ZExt)
378 RetValue = DAG.getNode(ISD::AssertZext, dl, VA.getLocVT(), RetValue,
379 DAG.getValueType(VA.getValVT()));
381 if (VA.getLocInfo() != CCValAssign::Full)
382 RetValue = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), RetValue);
384 ResultVals.push_back(RetValue);
387 ResultVals.push_back(Chain);
389 // Merge everything together with a MERGE_VALUES node.
390 return DAG.getNode(ISD::MERGE_VALUES, dl, TheCall->getVTList(),
391 &ResultVals[0], ResultVals.size()).getNode();
395 SDValue SystemZTargetLowering::LowerRET(SDValue Op, SelectionDAG &DAG) {
396 // CCValAssign - represent the assignment of the return value to a location
397 SmallVector<CCValAssign, 16> RVLocs;
398 unsigned CC = DAG.getMachineFunction().getFunction()->getCallingConv();
399 bool isVarArg = DAG.getMachineFunction().getFunction()->isVarArg();
400 DebugLoc dl = Op.getDebugLoc();
402 // CCState - Info about the registers and stack slot.
403 CCState CCInfo(CC, isVarArg, getTargetMachine(), RVLocs);
405 // Analize return values of ISD::RET
406 CCInfo.AnalyzeReturn(Op.getNode(), RetCC_SystemZ);
408 // If this is the first return lowered for this function, add the regs to the
409 // liveout set for the function.
410 if (DAG.getMachineFunction().getRegInfo().liveout_empty()) {
411 for (unsigned i = 0; i != RVLocs.size(); ++i)
412 if (RVLocs[i].isRegLoc())
413 DAG.getMachineFunction().getRegInfo().addLiveOut(RVLocs[i].getLocReg());
416 // The chain is always operand #0
417 SDValue Chain = Op.getOperand(0);
420 // Copy the result values into the output registers.
421 for (unsigned i = 0; i != RVLocs.size(); ++i) {
422 CCValAssign &VA = RVLocs[i];
423 SDValue ResValue = Op.getOperand(i*2+1);
424 assert(VA.isRegLoc() && "Can only return in registers!");
426 // If this is an 8/16/32-bit value, it is really should be passed promoted
428 if (VA.getLocInfo() == CCValAssign::SExt)
429 ResValue = DAG.getNode(ISD::SIGN_EXTEND, dl, VA.getLocVT(), ResValue);
430 else if (VA.getLocInfo() == CCValAssign::ZExt)
431 ResValue = DAG.getNode(ISD::ZERO_EXTEND, dl, VA.getLocVT(), ResValue);
432 else if (VA.getLocInfo() == CCValAssign::AExt)
433 ResValue = DAG.getNode(ISD::ANY_EXTEND, dl, VA.getLocVT(), ResValue);
435 // ISD::RET => ret chain, (regnum1,val1), ...
436 // So i*2+1 index only the regnums
437 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), ResValue, Flag);
439 // Guarantee that all emitted copies are stuck together,
440 // avoiding something bad.
441 Flag = Chain.getValue(1);
445 return DAG.getNode(SystemZISD::RET_FLAG, dl, MVT::Other, Chain, Flag);
448 return DAG.getNode(SystemZISD::RET_FLAG, dl, MVT::Other, Chain);
451 SDValue SystemZTargetLowering::EmitCmp(SDValue LHS, SDValue RHS,
452 ISD::CondCode CC, SDValue &SystemZCC,
454 assert(!LHS.getValueType().isFloatingPoint() && "We don't handle FP yet");
456 // FIXME: Emit a test if RHS is zero
458 bool isUnsigned = false;
459 SystemZCC::CondCodes TCC;
461 default: assert(0 && "Invalid integer condition!");
469 isUnsigned = true; // FALLTHROUGH
474 isUnsigned = true; // FALLTHROUGH
481 TCC = SystemZCC::H; // FALLTHROUGH
485 case ISD::SETLT: // FALLTHROUGH
490 SystemZCC = DAG.getConstant(TCC, MVT::i32);
492 DebugLoc dl = LHS.getDebugLoc();
493 return DAG.getNode((isUnsigned ? SystemZISD::UCMP : SystemZISD::CMP),
494 dl, MVT::Flag, LHS, RHS);
498 SDValue SystemZTargetLowering::LowerBR_CC(SDValue Op, SelectionDAG &DAG) {
499 SDValue Chain = Op.getOperand(0);
500 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(1))->get();
501 SDValue LHS = Op.getOperand(2);
502 SDValue RHS = Op.getOperand(3);
503 SDValue Dest = Op.getOperand(4);
504 DebugLoc dl = Op.getDebugLoc();
507 SDValue Flag = EmitCmp(LHS, RHS, CC, SystemZCC, DAG);
508 return DAG.getNode(SystemZISD::BRCOND, dl, Op.getValueType(),
509 Chain, Dest, SystemZCC, Flag);
512 SDValue SystemZTargetLowering::LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) {
513 SDValue LHS = Op.getOperand(0);
514 SDValue RHS = Op.getOperand(1);
515 SDValue TrueV = Op.getOperand(2);
516 SDValue FalseV = Op.getOperand(3);
517 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(4))->get();
518 DebugLoc dl = Op.getDebugLoc();
521 SDValue Flag = EmitCmp(LHS, RHS, CC, SystemZCC, DAG);
523 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::Flag);
524 SmallVector<SDValue, 4> Ops;
525 Ops.push_back(TrueV);
526 Ops.push_back(FalseV);
527 Ops.push_back(SystemZCC);
530 return DAG.getNode(SystemZISD::SELECT, dl, VTs, &Ops[0], Ops.size());
533 SDValue SystemZTargetLowering::LowerGlobalAddress(SDValue Op,
535 DebugLoc dl = Op.getDebugLoc();
536 GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
537 SDValue GA = DAG.getTargetGlobalAddress(GV, getPointerTy());
539 // FIXME: Verify stuff for constant globals entries
540 return DAG.getNode(SystemZISD::PCRelativeWrapper, dl, getPointerTy(), GA);
544 SDValue SystemZTargetLowering::LowerJumpTable(SDValue Op,
546 DebugLoc dl = Op.getDebugLoc();
547 JumpTableSDNode *JT = cast<JumpTableSDNode>(Op);
548 SDValue Result = DAG.getTargetJumpTable(JT->getIndex(), getPointerTy());
550 return DAG.getNode(SystemZISD::PCRelativeWrapper, dl, getPointerTy(), Result);
553 const char *SystemZTargetLowering::getTargetNodeName(unsigned Opcode) const {
555 case SystemZISD::RET_FLAG: return "SystemZISD::RET_FLAG";
556 case SystemZISD::CALL: return "SystemZISD::CALL";
557 case SystemZISD::BRCOND: return "SystemZISD::BRCOND";
558 case SystemZISD::CMP: return "SystemZISD::CMP";
559 case SystemZISD::UCMP: return "SystemZISD::UCMP";
560 case SystemZISD::SELECT: return "SystemZISD::SELECT";
561 case SystemZISD::PCRelativeWrapper: return "SystemZISD::PCRelativeWrapper";
562 default: return NULL;
566 //===----------------------------------------------------------------------===//
567 // Other Lowering Code
568 //===----------------------------------------------------------------------===//
571 SystemZTargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
572 MachineBasicBlock *BB) const {
573 const SystemZInstrInfo &TII = *TM.getInstrInfo();
574 DebugLoc dl = MI->getDebugLoc();
575 assert((MI->getOpcode() == SystemZ::Select32 ||
576 MI->getOpcode() == SystemZ::Select64) &&
577 "Unexpected instr type to insert");
579 // To "insert" a SELECT instruction, we actually have to insert the diamond
580 // control-flow pattern. The incoming instruction knows the destination vreg
581 // to set, the condition code register to branch on, the true/false values to
582 // select between, and a branch opcode to use.
583 const BasicBlock *LLVM_BB = BB->getBasicBlock();
584 MachineFunction::iterator I = BB;
592 // fallthrough --> copy0MBB
593 MachineBasicBlock *thisMBB = BB;
594 MachineFunction *F = BB->getParent();
595 MachineBasicBlock *copy0MBB = F->CreateMachineBasicBlock(LLVM_BB);
596 MachineBasicBlock *copy1MBB = F->CreateMachineBasicBlock(LLVM_BB);
597 SystemZCC::CondCodes CC = (SystemZCC::CondCodes)MI->getOperand(3).getImm();
598 BuildMI(BB, dl, TII.getBrCond(CC)).addMBB(copy1MBB);
599 F->insert(I, copy0MBB);
600 F->insert(I, copy1MBB);
601 // Update machine-CFG edges by transferring all successors of the current
602 // block to the new block which will contain the Phi node for the select.
603 copy1MBB->transferSuccessors(BB);
604 // Next, add the true and fallthrough blocks as its successors.
605 BB->addSuccessor(copy0MBB);
606 BB->addSuccessor(copy1MBB);
610 // # fallthrough to copy1MBB
613 // Update machine-CFG edges
614 BB->addSuccessor(copy1MBB);
617 // %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ]
620 BuildMI(BB, dl, TII.get(SystemZ::PHI),
621 MI->getOperand(0).getReg())
622 .addReg(MI->getOperand(2).getReg()).addMBB(copy0MBB)
623 .addReg(MI->getOperand(1).getReg()).addMBB(thisMBB);
625 F->DeleteMachineInstr(MI); // The pseudo instruction is gone now.