1 //===-- SystemZISelLowering.cpp - SystemZ DAG Lowering Implementation -----==//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements the SystemZTargetLowering class.
12 //===----------------------------------------------------------------------===//
14 #define DEBUG_TYPE "systemz-lower"
16 #include "SystemZISelLowering.h"
18 #include "SystemZTargetMachine.h"
19 #include "SystemZSubtarget.h"
20 #include "llvm/DerivedTypes.h"
21 #include "llvm/Function.h"
22 #include "llvm/Intrinsics.h"
23 #include "llvm/CallingConv.h"
24 #include "llvm/GlobalVariable.h"
25 #include "llvm/GlobalAlias.h"
26 #include "llvm/CodeGen/CallingConvLower.h"
27 #include "llvm/CodeGen/MachineFrameInfo.h"
28 #include "llvm/CodeGen/MachineFunction.h"
29 #include "llvm/CodeGen/MachineInstrBuilder.h"
30 #include "llvm/CodeGen/MachineRegisterInfo.h"
31 #include "llvm/CodeGen/PseudoSourceValue.h"
32 #include "llvm/CodeGen/SelectionDAGISel.h"
33 #include "llvm/CodeGen/ValueTypes.h"
34 #include "llvm/Target/TargetOptions.h"
35 #include "llvm/Target/TargetLoweringObjectFile.h"
36 #include "llvm/Support/Debug.h"
37 #include "llvm/ADT/VectorExtras.h"
40 SystemZTargetLowering::SystemZTargetLowering(SystemZTargetMachine &tm) :
41 TargetLowering(tm, new TargetLoweringObjectFileELF()),
42 Subtarget(*tm.getSubtargetImpl()), TM(tm) {
44 RegInfo = TM.getRegisterInfo();
46 // Set up the register classes.
47 addRegisterClass(MVT::i32, SystemZ::GR32RegisterClass);
48 addRegisterClass(MVT::i64, SystemZ::GR64RegisterClass);
49 addRegisterClass(MVT::v2i32,SystemZ::GR64PRegisterClass);
50 addRegisterClass(MVT::v2i64,SystemZ::GR128RegisterClass);
53 addRegisterClass(MVT::f32, SystemZ::FP32RegisterClass);
54 addRegisterClass(MVT::f64, SystemZ::FP64RegisterClass);
56 addLegalFPImmediate(APFloat(+0.0)); // lzer
57 addLegalFPImmediate(APFloat(+0.0f)); // lzdr
58 addLegalFPImmediate(APFloat(-0.0)); // lzer + lner
59 addLegalFPImmediate(APFloat(-0.0f)); // lzdr + lndr
62 // Compute derived properties from the register classes
63 computeRegisterProperties();
65 // Set shifts properties
66 setShiftAmountType(MVT::i64);
68 // Provide all sorts of operation actions
69 setLoadExtAction(ISD::SEXTLOAD, MVT::i1, Promote);
70 setLoadExtAction(ISD::ZEXTLOAD, MVT::i1, Promote);
71 setLoadExtAction(ISD::EXTLOAD, MVT::i1, Promote);
73 setLoadExtAction(ISD::SEXTLOAD, MVT::f32, Expand);
74 setLoadExtAction(ISD::ZEXTLOAD, MVT::f32, Expand);
75 setLoadExtAction(ISD::EXTLOAD, MVT::f32, Expand);
77 setLoadExtAction(ISD::SEXTLOAD, MVT::f64, Expand);
78 setLoadExtAction(ISD::ZEXTLOAD, MVT::f64, Expand);
79 setLoadExtAction(ISD::EXTLOAD, MVT::f64, Expand);
81 setStackPointerRegisterToSaveRestore(SystemZ::R15D);
82 setSchedulingPreference(SchedulingForLatency);
83 setBooleanContents(ZeroOrOneBooleanContent);
85 setOperationAction(ISD::BR_JT, MVT::Other, Expand);
86 setOperationAction(ISD::BRCOND, MVT::Other, Expand);
87 setOperationAction(ISD::BR_CC, MVT::i32, Custom);
88 setOperationAction(ISD::BR_CC, MVT::i64, Custom);
89 setOperationAction(ISD::BR_CC, MVT::f32, Custom);
90 setOperationAction(ISD::BR_CC, MVT::f64, Custom);
91 setOperationAction(ISD::ConstantPool, MVT::i32, Custom);
92 setOperationAction(ISD::ConstantPool, MVT::i64, Custom);
93 setOperationAction(ISD::GlobalAddress, MVT::i64, Custom);
94 setOperationAction(ISD::JumpTable, MVT::i64, Custom);
95 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i64, Expand);
97 setOperationAction(ISD::SDIV, MVT::i32, Expand);
98 setOperationAction(ISD::UDIV, MVT::i32, Expand);
99 setOperationAction(ISD::SDIV, MVT::i64, Expand);
100 setOperationAction(ISD::UDIV, MVT::i64, Expand);
101 setOperationAction(ISD::SREM, MVT::i32, Expand);
102 setOperationAction(ISD::UREM, MVT::i32, Expand);
103 setOperationAction(ISD::SREM, MVT::i64, Expand);
104 setOperationAction(ISD::UREM, MVT::i64, Expand);
106 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand);
108 setOperationAction(ISD::CTPOP, MVT::i32, Expand);
109 setOperationAction(ISD::CTPOP, MVT::i64, Expand);
110 setOperationAction(ISD::CTTZ, MVT::i32, Expand);
111 setOperationAction(ISD::CTTZ, MVT::i64, Expand);
112 setOperationAction(ISD::CTLZ, MVT::i32, Promote);
113 setOperationAction(ISD::CTLZ, MVT::i64, Legal);
115 // FIXME: Can we lower these 2 efficiently?
116 setOperationAction(ISD::SETCC, MVT::i32, Expand);
117 setOperationAction(ISD::SETCC, MVT::i64, Expand);
118 setOperationAction(ISD::SETCC, MVT::f32, Expand);
119 setOperationAction(ISD::SETCC, MVT::f64, Expand);
120 setOperationAction(ISD::SELECT, MVT::i32, Expand);
121 setOperationAction(ISD::SELECT, MVT::i64, Expand);
122 setOperationAction(ISD::SELECT, MVT::f32, Expand);
123 setOperationAction(ISD::SELECT, MVT::f64, Expand);
124 setOperationAction(ISD::SELECT_CC, MVT::i32, Custom);
125 setOperationAction(ISD::SELECT_CC, MVT::i64, Custom);
126 setOperationAction(ISD::SELECT_CC, MVT::f32, Custom);
127 setOperationAction(ISD::SELECT_CC, MVT::f64, Custom);
129 // Funny enough: we don't have 64-bit signed versions of these stuff, but have
131 setOperationAction(ISD::MULHS, MVT::i64, Expand);
132 setOperationAction(ISD::SMUL_LOHI, MVT::i64, Expand);
134 // Lower some FP stuff
135 setOperationAction(ISD::FSIN, MVT::f32, Expand);
136 setOperationAction(ISD::FSIN, MVT::f64, Expand);
137 setOperationAction(ISD::FCOS, MVT::f32, Expand);
138 setOperationAction(ISD::FCOS, MVT::f64, Expand);
139 setOperationAction(ISD::FREM, MVT::f32, Expand);
140 setOperationAction(ISD::FREM, MVT::f64, Expand);
142 // We have only 64-bit bitconverts
143 setOperationAction(ISD::BIT_CONVERT, MVT::f32, Expand);
144 setOperationAction(ISD::BIT_CONVERT, MVT::i32, Expand);
146 setOperationAction(ISD::UINT_TO_FP, MVT::i32, Expand);
147 setOperationAction(ISD::UINT_TO_FP, MVT::i64, Expand);
148 setOperationAction(ISD::FP_TO_UINT, MVT::i32, Expand);
149 setOperationAction(ISD::FP_TO_UINT, MVT::i64, Expand);
151 setTruncStoreAction(MVT::f64, MVT::f32, Expand);
154 SDValue SystemZTargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) {
155 switch (Op.getOpcode()) {
156 case ISD::BR_CC: return LowerBR_CC(Op, DAG);
157 case ISD::SELECT_CC: return LowerSELECT_CC(Op, DAG);
158 case ISD::GlobalAddress: return LowerGlobalAddress(Op, DAG);
159 case ISD::JumpTable: return LowerJumpTable(Op, DAG);
160 case ISD::ConstantPool: return LowerConstantPool(Op, DAG);
162 llvm_unreachable("Should not custom lower this!");
167 //===----------------------------------------------------------------------===//
168 // SystemZ Inline Assembly Support
169 //===----------------------------------------------------------------------===//
171 /// getConstraintType - Given a constraint letter, return the type of
172 /// constraint it is for this target.
173 TargetLowering::ConstraintType
174 SystemZTargetLowering::getConstraintType(const std::string &Constraint) const {
175 if (Constraint.size() == 1) {
176 switch (Constraint[0]) {
178 return C_RegisterClass;
183 return TargetLowering::getConstraintType(Constraint);
186 std::pair<unsigned, const TargetRegisterClass*>
187 SystemZTargetLowering::
188 getRegForInlineAsmConstraint(const std::string &Constraint,
190 if (Constraint.size() == 1) {
191 // GCC Constraint Letters
192 switch (Constraint[0]) {
194 case 'r': // GENERAL_REGS
196 return std::make_pair(0U, SystemZ::GR32RegisterClass);
197 else if (VT == MVT::i128)
198 return std::make_pair(0U, SystemZ::GR128RegisterClass);
200 return std::make_pair(0U, SystemZ::GR64RegisterClass);
204 return TargetLowering::getRegForInlineAsmConstraint(Constraint, VT);
207 //===----------------------------------------------------------------------===//
208 // Calling Convention Implementation
209 //===----------------------------------------------------------------------===//
211 #include "SystemZGenCallingConv.inc"
214 SystemZTargetLowering::LowerFormalArguments(SDValue Chain,
217 const SmallVectorImpl<ISD::InputArg>
221 SmallVectorImpl<SDValue> &InVals) {
225 llvm_unreachable("Unsupported calling convention");
227 case CallingConv::Fast:
228 return LowerCCCArguments(Chain, CallConv, isVarArg, Ins, dl, DAG, InVals);
233 SystemZTargetLowering::LowerCall(SDValue Chain, SDValue Callee,
234 unsigned CallConv, bool isVarArg,
236 const SmallVectorImpl<ISD::OutputArg> &Outs,
237 const SmallVectorImpl<ISD::InputArg> &Ins,
238 DebugLoc dl, SelectionDAG &DAG,
239 SmallVectorImpl<SDValue> &InVals) {
243 llvm_unreachable("Unsupported calling convention");
244 case CallingConv::Fast:
246 return LowerCCCCallTo(Chain, Callee, CallConv, isVarArg, isTailCall,
247 Outs, Ins, dl, DAG, InVals);
251 /// LowerCCCArguments - transform physical registers into virtual registers and
252 /// generate load operations for arguments places on the stack.
253 // FIXME: struct return stuff
256 SystemZTargetLowering::LowerCCCArguments(SDValue Chain,
259 const SmallVectorImpl<ISD::InputArg>
263 SmallVectorImpl<SDValue> &InVals) {
265 MachineFunction &MF = DAG.getMachineFunction();
266 MachineFrameInfo *MFI = MF.getFrameInfo();
267 MachineRegisterInfo &RegInfo = MF.getRegInfo();
269 // Assign locations to all of the incoming arguments.
270 SmallVector<CCValAssign, 16> ArgLocs;
271 CCState CCInfo(CallConv, isVarArg, getTargetMachine(),
272 ArgLocs, *DAG.getContext());
273 CCInfo.AnalyzeFormalArguments(Ins, CC_SystemZ);
276 llvm_report_error("Varargs not supported yet");
278 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
280 CCValAssign &VA = ArgLocs[i];
281 EVT LocVT = VA.getLocVT();
283 // Arguments passed in registers
284 TargetRegisterClass *RC;
285 switch (LocVT.getSimpleVT().SimpleTy) {
288 cerr << "LowerFormalArguments Unhandled argument type: "
289 << LocVT.getSimpleVT().SimpleTy
294 RC = SystemZ::GR64RegisterClass;
297 RC = SystemZ::FP32RegisterClass;
300 RC = SystemZ::FP64RegisterClass;
304 unsigned VReg = RegInfo.createVirtualRegister(RC);
305 RegInfo.addLiveIn(VA.getLocReg(), VReg);
306 ArgValue = DAG.getCopyFromReg(Chain, dl, VReg, LocVT);
309 assert(VA.isMemLoc());
311 // Create the nodes corresponding to a load from this parameter slot.
312 // Create the frame index object for this incoming parameter...
313 int FI = MFI->CreateFixedObject(LocVT.getSizeInBits()/8,
314 VA.getLocMemOffset());
316 // Create the SelectionDAG nodes corresponding to a load
317 // from this parameter
318 SDValue FIN = DAG.getFrameIndex(FI, getPointerTy());
319 ArgValue = DAG.getLoad(LocVT, dl, Chain, FIN,
320 PseudoSourceValue::getFixedStack(FI), 0);
323 // If this is an 8/16/32-bit value, it is really passed promoted to 64
324 // bits. Insert an assert[sz]ext to capture this, then truncate to the
326 if (VA.getLocInfo() == CCValAssign::SExt)
327 ArgValue = DAG.getNode(ISD::AssertSext, dl, LocVT, ArgValue,
328 DAG.getValueType(VA.getValVT()));
329 else if (VA.getLocInfo() == CCValAssign::ZExt)
330 ArgValue = DAG.getNode(ISD::AssertZext, dl, LocVT, ArgValue,
331 DAG.getValueType(VA.getValVT()));
333 if (VA.getLocInfo() != CCValAssign::Full)
334 ArgValue = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), ArgValue);
336 InVals.push_back(ArgValue);
342 /// LowerCCCCallTo - functions arguments are copied from virtual regs to
343 /// (physical regs)/(stack frame), CALLSEQ_START and CALLSEQ_END are emitted.
346 SystemZTargetLowering::LowerCCCCallTo(SDValue Chain, SDValue Callee,
347 unsigned CallConv, bool isVarArg,
349 const SmallVectorImpl<ISD::OutputArg>
351 const SmallVectorImpl<ISD::InputArg> &Ins,
352 DebugLoc dl, SelectionDAG &DAG,
353 SmallVectorImpl<SDValue> &InVals) {
355 MachineFunction &MF = DAG.getMachineFunction();
357 // Offset to first argument stack slot.
358 const unsigned FirstArgOffset = 160;
360 // Analyze operands of the call, assigning locations to each operand.
361 SmallVector<CCValAssign, 16> ArgLocs;
362 CCState CCInfo(CallConv, isVarArg, getTargetMachine(),
363 ArgLocs, *DAG.getContext());
365 CCInfo.AnalyzeCallOperands(Outs, CC_SystemZ);
367 // Get a count of how many bytes are to be pushed on the stack.
368 unsigned NumBytes = CCInfo.getNextStackOffset();
370 Chain = DAG.getCALLSEQ_START(Chain ,DAG.getConstant(NumBytes,
371 getPointerTy(), true));
373 SmallVector<std::pair<unsigned, SDValue>, 4> RegsToPass;
374 SmallVector<SDValue, 12> MemOpChains;
377 // Walk the register/memloc assignments, inserting copies/loads.
378 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
379 CCValAssign &VA = ArgLocs[i];
381 SDValue Arg = Outs[i].Val;
383 // Promote the value if needed.
384 switch (VA.getLocInfo()) {
385 default: assert(0 && "Unknown loc info!");
386 case CCValAssign::Full: break;
387 case CCValAssign::SExt:
388 Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, VA.getLocVT(), Arg);
390 case CCValAssign::ZExt:
391 Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, VA.getLocVT(), Arg);
393 case CCValAssign::AExt:
394 Arg = DAG.getNode(ISD::ANY_EXTEND, dl, VA.getLocVT(), Arg);
398 // Arguments that can be passed on register must be kept at RegsToPass
401 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg));
403 assert(VA.isMemLoc());
405 if (StackPtr.getNode() == 0)
407 DAG.getCopyFromReg(Chain, dl,
408 (RegInfo->hasFP(MF) ?
409 SystemZ::R11D : SystemZ::R15D),
412 unsigned Offset = FirstArgOffset + VA.getLocMemOffset();
413 SDValue PtrOff = DAG.getNode(ISD::ADD, dl, getPointerTy(),
415 DAG.getIntPtrConstant(Offset));
417 MemOpChains.push_back(DAG.getStore(Chain, dl, Arg, PtrOff,
418 PseudoSourceValue::getStack(), Offset));
422 // Transform all store nodes into one single node because all store nodes are
423 // independent of each other.
424 if (!MemOpChains.empty())
425 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
426 &MemOpChains[0], MemOpChains.size());
428 // Build a sequence of copy-to-reg nodes chained together with token chain and
429 // flag operands which copy the outgoing args into registers. The InFlag in
430 // necessary since all emited instructions must be stuck together.
432 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
433 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
434 RegsToPass[i].second, InFlag);
435 InFlag = Chain.getValue(1);
438 // If the callee is a GlobalAddress node (quite common, every direct call is)
439 // turn it into a TargetGlobalAddress node so that legalize doesn't hack it.
440 // Likewise ExternalSymbol -> TargetExternalSymbol.
441 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee))
442 Callee = DAG.getTargetGlobalAddress(G->getGlobal(), getPointerTy());
443 else if (ExternalSymbolSDNode *E = dyn_cast<ExternalSymbolSDNode>(Callee))
444 Callee = DAG.getTargetExternalSymbol(E->getSymbol(), getPointerTy());
446 // Returns a chain & a flag for retval copy to use.
447 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Flag);
448 SmallVector<SDValue, 8> Ops;
449 Ops.push_back(Chain);
450 Ops.push_back(Callee);
452 // Add argument registers to the end of the list so that they are
453 // known live into the call.
454 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i)
455 Ops.push_back(DAG.getRegister(RegsToPass[i].first,
456 RegsToPass[i].second.getValueType()));
458 if (InFlag.getNode())
459 Ops.push_back(InFlag);
461 Chain = DAG.getNode(SystemZISD::CALL, dl, NodeTys, &Ops[0], Ops.size());
462 InFlag = Chain.getValue(1);
464 // Create the CALLSEQ_END node.
465 Chain = DAG.getCALLSEQ_END(Chain,
466 DAG.getConstant(NumBytes, getPointerTy(), true),
467 DAG.getConstant(0, getPointerTy(), true),
469 InFlag = Chain.getValue(1);
471 // Handle result values, copying them out of physregs into vregs that we
473 return LowerCallResult(Chain, InFlag, CallConv, isVarArg, Ins, dl,
477 /// LowerCallResult - Lower the result values of a call into the
478 /// appropriate copies out of appropriate physical registers.
481 SystemZTargetLowering::LowerCallResult(SDValue Chain, SDValue InFlag,
482 unsigned CallConv, bool isVarArg,
483 const SmallVectorImpl<ISD::InputArg>
485 DebugLoc dl, SelectionDAG &DAG,
486 SmallVectorImpl<SDValue> &InVals) {
488 // Assign locations to each value returned by this call.
489 SmallVector<CCValAssign, 16> RVLocs;
490 CCState CCInfo(CallConv, isVarArg, getTargetMachine(), RVLocs,
493 CCInfo.AnalyzeCallResult(Ins, RetCC_SystemZ);
495 // Copy all of the result registers out of their specified physreg.
496 for (unsigned i = 0; i != RVLocs.size(); ++i) {
497 CCValAssign &VA = RVLocs[i];
499 Chain = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(),
500 VA.getLocVT(), InFlag).getValue(1);
501 SDValue RetValue = Chain.getValue(0);
502 InFlag = Chain.getValue(2);
504 // If this is an 8/16/32-bit value, it is really passed promoted to 64
505 // bits. Insert an assert[sz]ext to capture this, then truncate to the
507 if (VA.getLocInfo() == CCValAssign::SExt)
508 RetValue = DAG.getNode(ISD::AssertSext, dl, VA.getLocVT(), RetValue,
509 DAG.getValueType(VA.getValVT()));
510 else if (VA.getLocInfo() == CCValAssign::ZExt)
511 RetValue = DAG.getNode(ISD::AssertZext, dl, VA.getLocVT(), RetValue,
512 DAG.getValueType(VA.getValVT()));
514 if (VA.getLocInfo() != CCValAssign::Full)
515 RetValue = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), RetValue);
517 InVals.push_back(RetValue);
525 SystemZTargetLowering::LowerReturn(SDValue Chain,
526 unsigned CallConv, bool isVarArg,
527 const SmallVectorImpl<ISD::OutputArg> &Outs,
528 DebugLoc dl, SelectionDAG &DAG) {
530 // CCValAssign - represent the assignment of the return value to a location
531 SmallVector<CCValAssign, 16> RVLocs;
533 // CCState - Info about the registers and stack slot.
534 CCState CCInfo(CallConv, isVarArg, getTargetMachine(),
535 RVLocs, *DAG.getContext());
537 // Analize return values.
538 CCInfo.AnalyzeReturn(Outs, RetCC_SystemZ);
540 // If this is the first return lowered for this function, add the regs to the
541 // liveout set for the function.
542 if (DAG.getMachineFunction().getRegInfo().liveout_empty()) {
543 for (unsigned i = 0; i != RVLocs.size(); ++i)
544 if (RVLocs[i].isRegLoc())
545 DAG.getMachineFunction().getRegInfo().addLiveOut(RVLocs[i].getLocReg());
550 // Copy the result values into the output registers.
551 for (unsigned i = 0; i != RVLocs.size(); ++i) {
552 CCValAssign &VA = RVLocs[i];
553 SDValue ResValue = Outs[i].Val;
554 assert(VA.isRegLoc() && "Can only return in registers!");
556 // If this is an 8/16/32-bit value, it is really should be passed promoted
558 if (VA.getLocInfo() == CCValAssign::SExt)
559 ResValue = DAG.getNode(ISD::SIGN_EXTEND, dl, VA.getLocVT(), ResValue);
560 else if (VA.getLocInfo() == CCValAssign::ZExt)
561 ResValue = DAG.getNode(ISD::ZERO_EXTEND, dl, VA.getLocVT(), ResValue);
562 else if (VA.getLocInfo() == CCValAssign::AExt)
563 ResValue = DAG.getNode(ISD::ANY_EXTEND, dl, VA.getLocVT(), ResValue);
565 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), ResValue, Flag);
567 // Guarantee that all emitted copies are stuck together,
568 // avoiding something bad.
569 Flag = Chain.getValue(1);
573 return DAG.getNode(SystemZISD::RET_FLAG, dl, MVT::Other, Chain, Flag);
576 return DAG.getNode(SystemZISD::RET_FLAG, dl, MVT::Other, Chain);
579 SDValue SystemZTargetLowering::EmitCmp(SDValue LHS, SDValue RHS,
580 ISD::CondCode CC, SDValue &SystemZCC,
582 // FIXME: Emit a test if RHS is zero
584 bool isUnsigned = false;
585 SystemZCC::CondCodes TCC;
588 llvm_unreachable("Invalid integer condition!");
594 TCC = SystemZCC::NLH;
610 if (LHS.getValueType().isFloatingPoint()) {
614 isUnsigned = true; // FALLTHROUGH
620 if (LHS.getValueType().isFloatingPoint()) {
624 isUnsigned = true; // FALLTHROUGH
630 if (LHS.getValueType().isFloatingPoint()) {
631 TCC = SystemZCC::NLE;
634 isUnsigned = true; // FALLTHROUGH
640 if (LHS.getValueType().isFloatingPoint()) {
641 TCC = SystemZCC::NHE;
644 isUnsigned = true; // FALLTHROUGH
651 SystemZCC = DAG.getConstant(TCC, MVT::i32);
653 DebugLoc dl = LHS.getDebugLoc();
654 return DAG.getNode((isUnsigned ? SystemZISD::UCMP : SystemZISD::CMP),
655 dl, MVT::Flag, LHS, RHS);
659 SDValue SystemZTargetLowering::LowerBR_CC(SDValue Op, SelectionDAG &DAG) {
660 SDValue Chain = Op.getOperand(0);
661 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(1))->get();
662 SDValue LHS = Op.getOperand(2);
663 SDValue RHS = Op.getOperand(3);
664 SDValue Dest = Op.getOperand(4);
665 DebugLoc dl = Op.getDebugLoc();
668 SDValue Flag = EmitCmp(LHS, RHS, CC, SystemZCC, DAG);
669 return DAG.getNode(SystemZISD::BRCOND, dl, Op.getValueType(),
670 Chain, Dest, SystemZCC, Flag);
673 SDValue SystemZTargetLowering::LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) {
674 SDValue LHS = Op.getOperand(0);
675 SDValue RHS = Op.getOperand(1);
676 SDValue TrueV = Op.getOperand(2);
677 SDValue FalseV = Op.getOperand(3);
678 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(4))->get();
679 DebugLoc dl = Op.getDebugLoc();
682 SDValue Flag = EmitCmp(LHS, RHS, CC, SystemZCC, DAG);
684 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::Flag);
685 SmallVector<SDValue, 4> Ops;
686 Ops.push_back(TrueV);
687 Ops.push_back(FalseV);
688 Ops.push_back(SystemZCC);
691 return DAG.getNode(SystemZISD::SELECT, dl, VTs, &Ops[0], Ops.size());
694 SDValue SystemZTargetLowering::LowerGlobalAddress(SDValue Op,
696 DebugLoc dl = Op.getDebugLoc();
697 GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
698 int64_t Offset = cast<GlobalAddressSDNode>(Op)->getOffset();
700 bool IsPic = getTargetMachine().getRelocationModel() == Reloc::PIC_;
701 bool ExtraLoadRequired =
702 Subtarget.GVRequiresExtraLoad(GV, getTargetMachine(), false);
705 if (!IsPic && !ExtraLoadRequired) {
706 Result = DAG.getTargetGlobalAddress(GV, getPointerTy(), Offset);
709 unsigned char OpFlags = 0;
710 if (ExtraLoadRequired)
711 OpFlags = SystemZII::MO_GOTENT;
713 Result = DAG.getTargetGlobalAddress(GV, getPointerTy(), 0, OpFlags);
716 Result = DAG.getNode(SystemZISD::PCRelativeWrapper, dl,
717 getPointerTy(), Result);
719 if (ExtraLoadRequired)
720 Result = DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(), Result,
721 PseudoSourceValue::getGOT(), 0);
723 // If there was a non-zero offset that we didn't fold, create an explicit
726 Result = DAG.getNode(ISD::ADD, dl, getPointerTy(), Result,
727 DAG.getConstant(Offset, getPointerTy()));
733 SDValue SystemZTargetLowering::LowerJumpTable(SDValue Op,
735 DebugLoc dl = Op.getDebugLoc();
736 JumpTableSDNode *JT = cast<JumpTableSDNode>(Op);
737 SDValue Result = DAG.getTargetJumpTable(JT->getIndex(), getPointerTy());
739 return DAG.getNode(SystemZISD::PCRelativeWrapper, dl, getPointerTy(), Result);
744 // FIXME: This is just dirty hack. We need to lower cpool properly
745 SDValue SystemZTargetLowering::LowerConstantPool(SDValue Op,
747 DebugLoc dl = Op.getDebugLoc();
748 ConstantPoolSDNode *CP = cast<ConstantPoolSDNode>(Op);
750 SDValue Result = DAG.getTargetConstantPool(CP->getConstVal(), getPointerTy(),
754 return DAG.getNode(SystemZISD::PCRelativeWrapper, dl, getPointerTy(), Result);
757 const char *SystemZTargetLowering::getTargetNodeName(unsigned Opcode) const {
759 case SystemZISD::RET_FLAG: return "SystemZISD::RET_FLAG";
760 case SystemZISD::CALL: return "SystemZISD::CALL";
761 case SystemZISD::BRCOND: return "SystemZISD::BRCOND";
762 case SystemZISD::CMP: return "SystemZISD::CMP";
763 case SystemZISD::UCMP: return "SystemZISD::UCMP";
764 case SystemZISD::SELECT: return "SystemZISD::SELECT";
765 case SystemZISD::PCRelativeWrapper: return "SystemZISD::PCRelativeWrapper";
766 default: return NULL;
770 //===----------------------------------------------------------------------===//
771 // Other Lowering Code
772 //===----------------------------------------------------------------------===//
775 SystemZTargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
776 MachineBasicBlock *BB) const {
777 const SystemZInstrInfo &TII = *TM.getInstrInfo();
778 DebugLoc dl = MI->getDebugLoc();
779 assert((MI->getOpcode() == SystemZ::Select32 ||
780 MI->getOpcode() == SystemZ::SelectF32 ||
781 MI->getOpcode() == SystemZ::Select64 ||
782 MI->getOpcode() == SystemZ::SelectF64) &&
783 "Unexpected instr type to insert");
785 // To "insert" a SELECT instruction, we actually have to insert the diamond
786 // control-flow pattern. The incoming instruction knows the destination vreg
787 // to set, the condition code register to branch on, the true/false values to
788 // select between, and a branch opcode to use.
789 const BasicBlock *LLVM_BB = BB->getBasicBlock();
790 MachineFunction::iterator I = BB;
798 // fallthrough --> copy0MBB
799 MachineBasicBlock *thisMBB = BB;
800 MachineFunction *F = BB->getParent();
801 MachineBasicBlock *copy0MBB = F->CreateMachineBasicBlock(LLVM_BB);
802 MachineBasicBlock *copy1MBB = F->CreateMachineBasicBlock(LLVM_BB);
803 SystemZCC::CondCodes CC = (SystemZCC::CondCodes)MI->getOperand(3).getImm();
804 BuildMI(BB, dl, TII.getBrCond(CC)).addMBB(copy1MBB);
805 F->insert(I, copy0MBB);
806 F->insert(I, copy1MBB);
807 // Update machine-CFG edges by transferring all successors of the current
808 // block to the new block which will contain the Phi node for the select.
809 copy1MBB->transferSuccessors(BB);
810 // Next, add the true and fallthrough blocks as its successors.
811 BB->addSuccessor(copy0MBB);
812 BB->addSuccessor(copy1MBB);
816 // # fallthrough to copy1MBB
819 // Update machine-CFG edges
820 BB->addSuccessor(copy1MBB);
823 // %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ]
826 BuildMI(BB, dl, TII.get(SystemZ::PHI),
827 MI->getOperand(0).getReg())
828 .addReg(MI->getOperand(2).getReg()).addMBB(copy0MBB)
829 .addReg(MI->getOperand(1).getReg()).addMBB(thisMBB);
831 F->DeleteMachineInstr(MI); // The pseudo instruction is gone now.