1 //===-- SystemZISelLowering.cpp - SystemZ DAG Lowering Implementation -----==//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements the SystemZTargetLowering class.
12 //===----------------------------------------------------------------------===//
14 #define DEBUG_TYPE "systemz-lower"
16 #include "SystemZISelLowering.h"
18 #include "SystemZTargetMachine.h"
19 #include "SystemZSubtarget.h"
20 #include "llvm/DerivedTypes.h"
21 #include "llvm/Function.h"
22 #include "llvm/Intrinsics.h"
23 #include "llvm/CallingConv.h"
24 #include "llvm/GlobalVariable.h"
25 #include "llvm/GlobalAlias.h"
26 #include "llvm/CodeGen/CallingConvLower.h"
27 #include "llvm/CodeGen/MachineFrameInfo.h"
28 #include "llvm/CodeGen/MachineFunction.h"
29 #include "llvm/CodeGen/MachineInstrBuilder.h"
30 #include "llvm/CodeGen/MachineRegisterInfo.h"
31 #include "llvm/CodeGen/PseudoSourceValue.h"
32 #include "llvm/CodeGen/SelectionDAGISel.h"
33 #include "llvm/CodeGen/ValueTypes.h"
34 #include "llvm/Support/Debug.h"
35 #include "llvm/Target/TargetOptions.h"
36 #include "llvm/ADT/VectorExtras.h"
39 SystemZTargetLowering::SystemZTargetLowering(SystemZTargetMachine &tm) :
40 TargetLowering(tm), Subtarget(*tm.getSubtargetImpl()), TM(tm) {
42 RegInfo = TM.getRegisterInfo();
44 // Set up the register classes.
45 addRegisterClass(MVT::i32, SystemZ::GR32RegisterClass);
46 addRegisterClass(MVT::i64, SystemZ::GR64RegisterClass);
47 addRegisterClass(MVT::v2i32,SystemZ::GR64PRegisterClass);
48 addRegisterClass(MVT::i128, SystemZ::GR128RegisterClass);
49 addRegisterClass(MVT::v2i64,SystemZ::GR128RegisterClass);
52 addRegisterClass(MVT::f32, SystemZ::FP32RegisterClass);
53 addRegisterClass(MVT::f64, SystemZ::FP64RegisterClass);
56 // Compute derived properties from the register classes
57 computeRegisterProperties();
59 // Set shifts properties
60 setShiftAmountFlavor(Extend);
61 setShiftAmountType(MVT::i64);
63 // Provide all sorts of operation actions
64 setLoadExtAction(ISD::SEXTLOAD, MVT::i1, Promote);
65 setLoadExtAction(ISD::ZEXTLOAD, MVT::i1, Promote);
66 setLoadExtAction(ISD::EXTLOAD, MVT::i1, Promote);
68 setLoadExtAction(ISD::SEXTLOAD, MVT::f32, Promote);
69 setLoadExtAction(ISD::ZEXTLOAD, MVT::f32, Promote);
70 setLoadExtAction(ISD::EXTLOAD, MVT::f32, Promote);
71 setLoadExtAction(ISD::SEXTLOAD, MVT::f64, Promote);
72 setLoadExtAction(ISD::ZEXTLOAD, MVT::f64, Promote);
73 setLoadExtAction(ISD::EXTLOAD, MVT::f64, Promote);
75 setStackPointerRegisterToSaveRestore(SystemZ::R15D);
76 setSchedulingPreference(SchedulingForLatency);
78 setOperationAction(ISD::RET, MVT::Other, Custom);
80 setOperationAction(ISD::BR_JT, MVT::Other, Expand);
81 setOperationAction(ISD::BRCOND, MVT::Other, Expand);
82 setOperationAction(ISD::BR_CC, MVT::i32, Custom);
83 setOperationAction(ISD::BR_CC, MVT::i64, Custom);
84 setOperationAction(ISD::BR_CC, MVT::f32, Custom);
85 setOperationAction(ISD::BR_CC, MVT::f64, Custom);
86 setOperationAction(ISD::ConstantPool, MVT::i32, Custom);
87 setOperationAction(ISD::ConstantPool, MVT::i64, Custom);
88 setOperationAction(ISD::GlobalAddress, MVT::i64, Custom);
89 setOperationAction(ISD::JumpTable, MVT::i64, Custom);
90 setOperationAction(ISD::DYNAMIC_STACKALLOC, MVT::i64, Expand);
92 setOperationAction(ISD::SDIV, MVT::i32, Expand);
93 setOperationAction(ISD::UDIV, MVT::i32, Expand);
94 setOperationAction(ISD::SDIV, MVT::i64, Expand);
95 setOperationAction(ISD::UDIV, MVT::i64, Expand);
96 setOperationAction(ISD::SREM, MVT::i32, Expand);
97 setOperationAction(ISD::UREM, MVT::i32, Expand);
98 setOperationAction(ISD::SREM, MVT::i64, Expand);
99 setOperationAction(ISD::UREM, MVT::i64, Expand);
101 // FIXME: Can we lower these 2 efficiently?
102 setOperationAction(ISD::SETCC, MVT::i32, Expand);
103 setOperationAction(ISD::SETCC, MVT::i64, Expand);
104 setOperationAction(ISD::SELECT, MVT::i32, Expand);
105 setOperationAction(ISD::SELECT, MVT::i64, Expand);
106 setOperationAction(ISD::SELECT_CC, MVT::i32, Custom);
107 setOperationAction(ISD::SELECT_CC, MVT::i64, Custom);
108 setOperationAction(ISD::SELECT_CC, MVT::f32, Custom);
109 setOperationAction(ISD::SELECT_CC, MVT::f64, Custom);
111 // Funny enough: we don't have 64-bit signed versions of these stuff, but have
113 setOperationAction(ISD::MULHS, MVT::i64, Expand);
114 setOperationAction(ISD::SMUL_LOHI, MVT::i64, Expand);
117 SDValue SystemZTargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) {
118 switch (Op.getOpcode()) {
119 case ISD::FORMAL_ARGUMENTS: return LowerFORMAL_ARGUMENTS(Op, DAG);
120 case ISD::RET: return LowerRET(Op, DAG);
121 case ISD::CALL: return LowerCALL(Op, DAG);
122 case ISD::BR_CC: return LowerBR_CC(Op, DAG);
123 case ISD::SELECT_CC: return LowerSELECT_CC(Op, DAG);
124 case ISD::GlobalAddress: return LowerGlobalAddress(Op, DAG);
125 case ISD::JumpTable: return LowerJumpTable(Op, DAG);
126 case ISD::ConstantPool: return LowerConstantPool(Op, DAG);
128 assert(0 && "unimplemented operand");
133 //===----------------------------------------------------------------------===//
134 // Calling Convention Implementation
135 //===----------------------------------------------------------------------===//
137 #include "SystemZGenCallingConv.inc"
139 SDValue SystemZTargetLowering::LowerFORMAL_ARGUMENTS(SDValue Op,
141 unsigned CC = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
144 assert(0 && "Unsupported calling convention");
146 case CallingConv::Fast:
147 return LowerCCCArguments(Op, DAG);
151 SDValue SystemZTargetLowering::LowerCALL(SDValue Op, SelectionDAG &DAG) {
152 CallSDNode *TheCall = cast<CallSDNode>(Op.getNode());
153 unsigned CallingConv = TheCall->getCallingConv();
154 switch (CallingConv) {
156 assert(0 && "Unsupported calling convention");
157 case CallingConv::Fast:
159 return LowerCCCCallTo(Op, DAG, CallingConv);
163 /// LowerCCCArguments - transform physical registers into virtual registers and
164 /// generate load operations for arguments places on the stack.
165 // FIXME: struct return stuff
167 SDValue SystemZTargetLowering::LowerCCCArguments(SDValue Op,
169 MachineFunction &MF = DAG.getMachineFunction();
170 MachineFrameInfo *MFI = MF.getFrameInfo();
171 MachineRegisterInfo &RegInfo = MF.getRegInfo();
172 SDValue Root = Op.getOperand(0);
173 bool isVarArg = cast<ConstantSDNode>(Op.getOperand(2))->getZExtValue() != 0;
174 unsigned CC = MF.getFunction()->getCallingConv();
175 DebugLoc dl = Op.getDebugLoc();
177 // Assign locations to all of the incoming arguments.
178 SmallVector<CCValAssign, 16> ArgLocs;
179 CCState CCInfo(CC, isVarArg, getTargetMachine(), ArgLocs);
180 CCInfo.AnalyzeFormalArguments(Op.getNode(), CC_SystemZ);
182 assert(!isVarArg && "Varargs not supported yet");
184 SmallVector<SDValue, 16> ArgValues;
185 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
186 CCValAssign &VA = ArgLocs[i];
188 // Arguments passed in registers
189 MVT RegVT = VA.getLocVT();
190 TargetRegisterClass *RC;
191 switch (RegVT.getSimpleVT()) {
193 cerr << "LowerFORMAL_ARGUMENTS Unhandled argument type: "
194 << RegVT.getSimpleVT()
198 RC = SystemZ::GR64RegisterClass;
201 RC = SystemZ::FP32RegisterClass;
204 RC = SystemZ::FP64RegisterClass;
208 unsigned VReg = RegInfo.createVirtualRegister(RC);
209 RegInfo.addLiveIn(VA.getLocReg(), VReg);
210 SDValue ArgValue = DAG.getCopyFromReg(Root, dl, VReg, RegVT);
212 // If this is an 8/16/32-bit value, it is really passed promoted to 64
213 // bits. Insert an assert[sz]ext to capture this, then truncate to the
215 if (VA.getLocInfo() == CCValAssign::SExt)
216 ArgValue = DAG.getNode(ISD::AssertSext, dl, RegVT, ArgValue,
217 DAG.getValueType(VA.getValVT()));
218 else if (VA.getLocInfo() == CCValAssign::ZExt)
219 ArgValue = DAG.getNode(ISD::AssertZext, dl, RegVT, ArgValue,
220 DAG.getValueType(VA.getValVT()));
222 if (VA.getLocInfo() != CCValAssign::Full)
223 ArgValue = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), ArgValue);
225 ArgValues.push_back(ArgValue);
228 assert(VA.isMemLoc());
230 // Create the nodes corresponding to a load from this parameter slot.
231 // Create the frame index object for this incoming parameter...
232 int FI = MFI->CreateFixedObject(VA.getValVT().getSizeInBits()/8,
233 VA.getLocMemOffset());
235 // Create the SelectionDAG nodes corresponding to a load
236 //from this parameter
237 SDValue FIN = DAG.getFrameIndex(FI, getPointerTy());
238 ArgValues.push_back(DAG.getLoad(VA.getValVT(), dl, Root, FIN,
239 PseudoSourceValue::getFixedStack(FI), 0));
243 ArgValues.push_back(Root);
245 // Return the new list of results.
246 return DAG.getNode(ISD::MERGE_VALUES, dl, Op.getNode()->getVTList(),
247 &ArgValues[0], ArgValues.size()).getValue(Op.getResNo());
250 /// LowerCCCCallTo - functions arguments are copied from virtual regs to
251 /// (physical regs)/(stack frame), CALLSEQ_START and CALLSEQ_END are emitted.
253 SDValue SystemZTargetLowering::LowerCCCCallTo(SDValue Op, SelectionDAG &DAG,
255 CallSDNode *TheCall = cast<CallSDNode>(Op.getNode());
256 SDValue Chain = TheCall->getChain();
257 SDValue Callee = TheCall->getCallee();
258 bool isVarArg = TheCall->isVarArg();
259 DebugLoc dl = Op.getDebugLoc();
260 MachineFunction &MF = DAG.getMachineFunction();
262 // Offset to first argument stack slot.
263 const unsigned FirstArgOffset = 160;
265 // Analyze operands of the call, assigning locations to each operand.
266 SmallVector<CCValAssign, 16> ArgLocs;
267 CCState CCInfo(CC, isVarArg, getTargetMachine(), ArgLocs);
269 CCInfo.AnalyzeCallOperands(TheCall, CC_SystemZ);
271 // Get a count of how many bytes are to be pushed on the stack.
272 unsigned NumBytes = CCInfo.getNextStackOffset();
274 Chain = DAG.getCALLSEQ_START(Chain ,DAG.getConstant(NumBytes,
275 getPointerTy(), true));
277 SmallVector<std::pair<unsigned, SDValue>, 4> RegsToPass;
278 SmallVector<SDValue, 12> MemOpChains;
281 // Walk the register/memloc assignments, inserting copies/loads.
282 for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
283 CCValAssign &VA = ArgLocs[i];
285 // Arguments start after the 5 first operands of ISD::CALL
286 SDValue Arg = TheCall->getArg(i);
288 // Promote the value if needed.
289 switch (VA.getLocInfo()) {
290 default: assert(0 && "Unknown loc info!");
291 case CCValAssign::Full: break;
292 case CCValAssign::SExt:
293 Arg = DAG.getNode(ISD::SIGN_EXTEND, dl, VA.getLocVT(), Arg);
295 case CCValAssign::ZExt:
296 Arg = DAG.getNode(ISD::ZERO_EXTEND, dl, VA.getLocVT(), Arg);
298 case CCValAssign::AExt:
299 Arg = DAG.getNode(ISD::ANY_EXTEND, dl, VA.getLocVT(), Arg);
303 // Arguments that can be passed on register must be kept at RegsToPass
306 RegsToPass.push_back(std::make_pair(VA.getLocReg(), Arg));
308 assert(VA.isMemLoc());
310 if (StackPtr.getNode() == 0)
312 DAG.getCopyFromReg(Chain, dl,
313 (RegInfo->hasFP(MF) ?
314 SystemZ::R11D : SystemZ::R15D),
317 unsigned Offset = FirstArgOffset + VA.getLocMemOffset();
318 SDValue PtrOff = DAG.getNode(ISD::ADD, dl, getPointerTy(),
320 DAG.getIntPtrConstant(Offset));
322 MemOpChains.push_back(DAG.getStore(Chain, dl, Arg, PtrOff,
323 PseudoSourceValue::getStack(), Offset));
327 // Transform all store nodes into one single node because all store nodes are
328 // independent of each other.
329 if (!MemOpChains.empty())
330 Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other,
331 &MemOpChains[0], MemOpChains.size());
333 // Build a sequence of copy-to-reg nodes chained together with token chain and
334 // flag operands which copy the outgoing args into registers. The InFlag in
335 // necessary since all emited instructions must be stuck together.
337 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) {
338 Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first,
339 RegsToPass[i].second, InFlag);
340 InFlag = Chain.getValue(1);
343 // If the callee is a GlobalAddress node (quite common, every direct call is)
344 // turn it into a TargetGlobalAddress node so that legalize doesn't hack it.
345 // Likewise ExternalSymbol -> TargetExternalSymbol.
346 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee))
347 Callee = DAG.getTargetGlobalAddress(G->getGlobal(), getPointerTy());
348 else if (ExternalSymbolSDNode *E = dyn_cast<ExternalSymbolSDNode>(Callee))
349 Callee = DAG.getTargetExternalSymbol(E->getSymbol(), getPointerTy());
351 // Returns a chain & a flag for retval copy to use.
352 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Flag);
353 SmallVector<SDValue, 8> Ops;
354 Ops.push_back(Chain);
355 Ops.push_back(Callee);
357 // Add argument registers to the end of the list so that they are
358 // known live into the call.
359 for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i)
360 Ops.push_back(DAG.getRegister(RegsToPass[i].first,
361 RegsToPass[i].second.getValueType()));
363 if (InFlag.getNode())
364 Ops.push_back(InFlag);
366 Chain = DAG.getNode(SystemZISD::CALL, dl, NodeTys, &Ops[0], Ops.size());
367 InFlag = Chain.getValue(1);
369 // Create the CALLSEQ_END node.
370 Chain = DAG.getCALLSEQ_END(Chain,
371 DAG.getConstant(NumBytes, getPointerTy(), true),
372 DAG.getConstant(0, getPointerTy(), true),
374 InFlag = Chain.getValue(1);
376 // Handle result values, copying them out of physregs into vregs that we
378 return SDValue(LowerCallResult(Chain, InFlag, TheCall, CC, DAG),
382 /// LowerCallResult - Lower the result values of an ISD::CALL into the
383 /// appropriate copies out of appropriate physical registers. This assumes that
384 /// Chain/InFlag are the input chain/flag to use, and that TheCall is the call
385 /// being lowered. Returns a SDNode with the same number of values as the
388 SystemZTargetLowering::LowerCallResult(SDValue Chain, SDValue InFlag,
390 unsigned CallingConv,
392 bool isVarArg = TheCall->isVarArg();
393 DebugLoc dl = TheCall->getDebugLoc();
395 // Assign locations to each value returned by this call.
396 SmallVector<CCValAssign, 16> RVLocs;
397 CCState CCInfo(CallingConv, isVarArg, getTargetMachine(), RVLocs);
399 CCInfo.AnalyzeCallResult(TheCall, RetCC_SystemZ);
400 SmallVector<SDValue, 8> ResultVals;
402 // Copy all of the result registers out of their specified physreg.
403 for (unsigned i = 0; i != RVLocs.size(); ++i) {
404 CCValAssign &VA = RVLocs[i];
406 Chain = DAG.getCopyFromReg(Chain, dl, VA.getLocReg(),
407 VA.getLocVT(), InFlag).getValue(1);
408 SDValue RetValue = Chain.getValue(0);
409 InFlag = Chain.getValue(2);
411 // If this is an 8/16/32-bit value, it is really passed promoted to 64
412 // bits. Insert an assert[sz]ext to capture this, then truncate to the
414 if (VA.getLocInfo() == CCValAssign::SExt)
415 RetValue = DAG.getNode(ISD::AssertSext, dl, VA.getLocVT(), RetValue,
416 DAG.getValueType(VA.getValVT()));
417 else if (VA.getLocInfo() == CCValAssign::ZExt)
418 RetValue = DAG.getNode(ISD::AssertZext, dl, VA.getLocVT(), RetValue,
419 DAG.getValueType(VA.getValVT()));
421 if (VA.getLocInfo() != CCValAssign::Full)
422 RetValue = DAG.getNode(ISD::TRUNCATE, dl, VA.getValVT(), RetValue);
424 ResultVals.push_back(RetValue);
427 ResultVals.push_back(Chain);
429 // Merge everything together with a MERGE_VALUES node.
430 return DAG.getNode(ISD::MERGE_VALUES, dl, TheCall->getVTList(),
431 &ResultVals[0], ResultVals.size()).getNode();
435 SDValue SystemZTargetLowering::LowerRET(SDValue Op, SelectionDAG &DAG) {
436 // CCValAssign - represent the assignment of the return value to a location
437 SmallVector<CCValAssign, 16> RVLocs;
438 unsigned CC = DAG.getMachineFunction().getFunction()->getCallingConv();
439 bool isVarArg = DAG.getMachineFunction().getFunction()->isVarArg();
440 DebugLoc dl = Op.getDebugLoc();
442 // CCState - Info about the registers and stack slot.
443 CCState CCInfo(CC, isVarArg, getTargetMachine(), RVLocs);
445 // Analize return values of ISD::RET
446 CCInfo.AnalyzeReturn(Op.getNode(), RetCC_SystemZ);
448 // If this is the first return lowered for this function, add the regs to the
449 // liveout set for the function.
450 if (DAG.getMachineFunction().getRegInfo().liveout_empty()) {
451 for (unsigned i = 0; i != RVLocs.size(); ++i)
452 if (RVLocs[i].isRegLoc())
453 DAG.getMachineFunction().getRegInfo().addLiveOut(RVLocs[i].getLocReg());
456 // The chain is always operand #0
457 SDValue Chain = Op.getOperand(0);
460 // Copy the result values into the output registers.
461 for (unsigned i = 0; i != RVLocs.size(); ++i) {
462 CCValAssign &VA = RVLocs[i];
463 SDValue ResValue = Op.getOperand(i*2+1);
464 assert(VA.isRegLoc() && "Can only return in registers!");
466 // If this is an 8/16/32-bit value, it is really should be passed promoted
468 if (VA.getLocInfo() == CCValAssign::SExt)
469 ResValue = DAG.getNode(ISD::SIGN_EXTEND, dl, VA.getLocVT(), ResValue);
470 else if (VA.getLocInfo() == CCValAssign::ZExt)
471 ResValue = DAG.getNode(ISD::ZERO_EXTEND, dl, VA.getLocVT(), ResValue);
472 else if (VA.getLocInfo() == CCValAssign::AExt)
473 ResValue = DAG.getNode(ISD::ANY_EXTEND, dl, VA.getLocVT(), ResValue);
475 // ISD::RET => ret chain, (regnum1,val1), ...
476 // So i*2+1 index only the regnums
477 Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), ResValue, Flag);
479 // Guarantee that all emitted copies are stuck together,
480 // avoiding something bad.
481 Flag = Chain.getValue(1);
485 return DAG.getNode(SystemZISD::RET_FLAG, dl, MVT::Other, Chain, Flag);
488 return DAG.getNode(SystemZISD::RET_FLAG, dl, MVT::Other, Chain);
491 SDValue SystemZTargetLowering::EmitCmp(SDValue LHS, SDValue RHS,
492 ISD::CondCode CC, SDValue &SystemZCC,
494 // FIXME: Emit a test if RHS is zero
496 bool isUnsigned = false;
497 SystemZCC::CondCodes TCC;
499 default: assert(0 && "Invalid integer condition!");
505 TCC = SystemZCC::NLH;
521 if (LHS.getValueType().isFloatingPoint()) {
525 isUnsigned = true; // FALLTHROUGH
531 if (LHS.getValueType().isFloatingPoint()) {
535 isUnsigned = true; // FALLTHROUGH
541 if (LHS.getValueType().isFloatingPoint()) {
542 TCC = SystemZCC::NLE;
545 isUnsigned = true; // FALLTHROUGH
551 if (LHS.getValueType().isFloatingPoint()) {
552 TCC = SystemZCC::NHE;
555 isUnsigned = true; // FALLTHROUGH
562 SystemZCC = DAG.getConstant(TCC, MVT::i32);
564 DebugLoc dl = LHS.getDebugLoc();
565 return DAG.getNode((isUnsigned ? SystemZISD::UCMP : SystemZISD::CMP),
566 dl, MVT::Flag, LHS, RHS);
570 SDValue SystemZTargetLowering::LowerBR_CC(SDValue Op, SelectionDAG &DAG) {
571 SDValue Chain = Op.getOperand(0);
572 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(1))->get();
573 SDValue LHS = Op.getOperand(2);
574 SDValue RHS = Op.getOperand(3);
575 SDValue Dest = Op.getOperand(4);
576 DebugLoc dl = Op.getDebugLoc();
579 SDValue Flag = EmitCmp(LHS, RHS, CC, SystemZCC, DAG);
580 return DAG.getNode(SystemZISD::BRCOND, dl, Op.getValueType(),
581 Chain, Dest, SystemZCC, Flag);
584 SDValue SystemZTargetLowering::LowerSELECT_CC(SDValue Op, SelectionDAG &DAG) {
585 SDValue LHS = Op.getOperand(0);
586 SDValue RHS = Op.getOperand(1);
587 SDValue TrueV = Op.getOperand(2);
588 SDValue FalseV = Op.getOperand(3);
589 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(4))->get();
590 DebugLoc dl = Op.getDebugLoc();
593 SDValue Flag = EmitCmp(LHS, RHS, CC, SystemZCC, DAG);
595 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::Flag);
596 SmallVector<SDValue, 4> Ops;
597 Ops.push_back(TrueV);
598 Ops.push_back(FalseV);
599 Ops.push_back(SystemZCC);
602 return DAG.getNode(SystemZISD::SELECT, dl, VTs, &Ops[0], Ops.size());
605 SDValue SystemZTargetLowering::LowerGlobalAddress(SDValue Op,
607 DebugLoc dl = Op.getDebugLoc();
608 GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
609 int64_t Offset = cast<GlobalAddressSDNode>(Op)->getOffset();
611 bool IsPic = getTargetMachine().getRelocationModel() == Reloc::PIC_;
612 bool ExtraLoadRequired =
613 Subtarget.GVRequiresExtraLoad(GV, getTargetMachine(), false);
616 if (!IsPic && !ExtraLoadRequired) {
617 Result = DAG.getTargetGlobalAddress(GV, getPointerTy(), Offset);
620 unsigned char OpFlags = 0;
621 if (ExtraLoadRequired)
622 OpFlags = SystemZII::MO_GOTENT;
624 Result = DAG.getTargetGlobalAddress(GV, getPointerTy(), 0, OpFlags);
627 Result = DAG.getNode(SystemZISD::PCRelativeWrapper, dl,
628 getPointerTy(), Result);
630 if (ExtraLoadRequired)
631 Result = DAG.getLoad(getPointerTy(), dl, DAG.getEntryNode(), Result,
632 PseudoSourceValue::getGOT(), 0);
634 // If there was a non-zero offset that we didn't fold, create an explicit
637 Result = DAG.getNode(ISD::ADD, dl, getPointerTy(), Result,
638 DAG.getConstant(Offset, getPointerTy()));
644 SDValue SystemZTargetLowering::LowerJumpTable(SDValue Op,
646 DebugLoc dl = Op.getDebugLoc();
647 JumpTableSDNode *JT = cast<JumpTableSDNode>(Op);
648 SDValue Result = DAG.getTargetJumpTable(JT->getIndex(), getPointerTy());
650 return DAG.getNode(SystemZISD::PCRelativeWrapper, dl, getPointerTy(), Result);
655 // FIXME: This is just dirty hack. We need to lower cpool properly
656 SDValue SystemZTargetLowering::LowerConstantPool(SDValue Op,
658 DebugLoc dl = Op.getDebugLoc();
659 ConstantPoolSDNode *CP = cast<ConstantPoolSDNode>(Op);
661 SDValue Result = DAG.getTargetConstantPool(CP->getConstVal(), getPointerTy(),
665 return DAG.getNode(SystemZISD::PCRelativeWrapper, dl, getPointerTy(), Result);
668 const char *SystemZTargetLowering::getTargetNodeName(unsigned Opcode) const {
670 case SystemZISD::RET_FLAG: return "SystemZISD::RET_FLAG";
671 case SystemZISD::CALL: return "SystemZISD::CALL";
672 case SystemZISD::BRCOND: return "SystemZISD::BRCOND";
673 case SystemZISD::CMP: return "SystemZISD::CMP";
674 case SystemZISD::UCMP: return "SystemZISD::UCMP";
675 case SystemZISD::SELECT: return "SystemZISD::SELECT";
676 case SystemZISD::PCRelativeWrapper: return "SystemZISD::PCRelativeWrapper";
677 default: return NULL;
681 //===----------------------------------------------------------------------===//
682 // Other Lowering Code
683 //===----------------------------------------------------------------------===//
686 SystemZTargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
687 MachineBasicBlock *BB) const {
688 const SystemZInstrInfo &TII = *TM.getInstrInfo();
689 DebugLoc dl = MI->getDebugLoc();
690 assert((MI->getOpcode() == SystemZ::Select32 ||
691 MI->getOpcode() == SystemZ::Select64) &&
692 "Unexpected instr type to insert");
694 // To "insert" a SELECT instruction, we actually have to insert the diamond
695 // control-flow pattern. The incoming instruction knows the destination vreg
696 // to set, the condition code register to branch on, the true/false values to
697 // select between, and a branch opcode to use.
698 const BasicBlock *LLVM_BB = BB->getBasicBlock();
699 MachineFunction::iterator I = BB;
707 // fallthrough --> copy0MBB
708 MachineBasicBlock *thisMBB = BB;
709 MachineFunction *F = BB->getParent();
710 MachineBasicBlock *copy0MBB = F->CreateMachineBasicBlock(LLVM_BB);
711 MachineBasicBlock *copy1MBB = F->CreateMachineBasicBlock(LLVM_BB);
712 SystemZCC::CondCodes CC = (SystemZCC::CondCodes)MI->getOperand(3).getImm();
713 BuildMI(BB, dl, TII.getBrCond(CC)).addMBB(copy1MBB);
714 F->insert(I, copy0MBB);
715 F->insert(I, copy1MBB);
716 // Update machine-CFG edges by transferring all successors of the current
717 // block to the new block which will contain the Phi node for the select.
718 copy1MBB->transferSuccessors(BB);
719 // Next, add the true and fallthrough blocks as its successors.
720 BB->addSuccessor(copy0MBB);
721 BB->addSuccessor(copy1MBB);
725 // # fallthrough to copy1MBB
728 // Update machine-CFG edges
729 BB->addSuccessor(copy1MBB);
732 // %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, thisMBB ]
735 BuildMI(BB, dl, TII.get(SystemZ::PHI),
736 MI->getOperand(0).getReg())
737 .addReg(MI->getOperand(2).getReg()).addMBB(copy0MBB)
738 .addReg(MI->getOperand(1).getReg()).addMBB(thisMBB);
740 F->DeleteMachineInstr(MI); // The pseudo instruction is gone now.