1 //===-- SystemZISelLowering.cpp - SystemZ DAG lowering implementation -----===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements the SystemZTargetLowering class.
12 //===----------------------------------------------------------------------===//
14 #define DEBUG_TYPE "systemz-lower"
16 #include "SystemZISelLowering.h"
17 #include "SystemZCallingConv.h"
18 #include "SystemZConstantPoolValue.h"
19 #include "SystemZMachineFunctionInfo.h"
20 #include "SystemZTargetMachine.h"
21 #include "llvm/CodeGen/CallingConvLower.h"
22 #include "llvm/CodeGen/MachineInstrBuilder.h"
23 #include "llvm/CodeGen/MachineRegisterInfo.h"
24 #include "llvm/CodeGen/TargetLoweringObjectFileImpl.h"
31 // Represents a sequence for extracting a 0/1 value from an IPM result:
32 // (((X ^ XORValue) + AddValue) >> Bit)
33 struct IPMConversion {
34 IPMConversion(unsigned xorValue, int64_t addValue, unsigned bit)
35 : XORValue(xorValue), AddValue(addValue), Bit(bit) {}
43 // Classify VT as either 32 or 64 bit.
44 static bool is32Bit(EVT VT) {
45 switch (VT.getSimpleVT().SimpleTy) {
51 llvm_unreachable("Unsupported type");
55 // Return a version of MachineOperand that can be safely used before the
57 static MachineOperand earlyUseOperand(MachineOperand Op) {
63 SystemZTargetLowering::SystemZTargetLowering(SystemZTargetMachine &tm)
64 : TargetLowering(tm, new TargetLoweringObjectFileELF()),
65 Subtarget(*tm.getSubtargetImpl()), TM(tm) {
66 MVT PtrVT = getPointerTy();
68 // Set up the register classes.
69 if (Subtarget.hasHighWord())
70 addRegisterClass(MVT::i32, &SystemZ::GRX32BitRegClass);
72 addRegisterClass(MVT::i32, &SystemZ::GR32BitRegClass);
73 addRegisterClass(MVT::i64, &SystemZ::GR64BitRegClass);
74 addRegisterClass(MVT::f32, &SystemZ::FP32BitRegClass);
75 addRegisterClass(MVT::f64, &SystemZ::FP64BitRegClass);
76 addRegisterClass(MVT::f128, &SystemZ::FP128BitRegClass);
78 // Compute derived properties from the register classes
79 computeRegisterProperties();
81 // Set up special registers.
82 setExceptionPointerRegister(SystemZ::R6D);
83 setExceptionSelectorRegister(SystemZ::R7D);
84 setStackPointerRegisterToSaveRestore(SystemZ::R15D);
86 // TODO: It may be better to default to latency-oriented scheduling, however
87 // LLVM's current latency-oriented scheduler can't handle physreg definitions
88 // such as SystemZ has with CC, so set this to the register-pressure
89 // scheduler, because it can.
90 setSchedulingPreference(Sched::RegPressure);
92 setBooleanContents(ZeroOrOneBooleanContent);
93 setBooleanVectorContents(ZeroOrOneBooleanContent); // FIXME: Is this correct?
95 // Instructions are strings of 2-byte aligned 2-byte values.
96 setMinFunctionAlignment(2);
98 // Handle operations that are handled in a similar way for all types.
99 for (unsigned I = MVT::FIRST_INTEGER_VALUETYPE;
100 I <= MVT::LAST_FP_VALUETYPE;
102 MVT VT = MVT::SimpleValueType(I);
103 if (isTypeLegal(VT)) {
104 // Lower SET_CC into an IPM-based sequence.
105 setOperationAction(ISD::SETCC, VT, Custom);
107 // Expand SELECT(C, A, B) into SELECT_CC(X, 0, A, B, NE).
108 setOperationAction(ISD::SELECT, VT, Expand);
110 // Lower SELECT_CC and BR_CC into separate comparisons and branches.
111 setOperationAction(ISD::SELECT_CC, VT, Custom);
112 setOperationAction(ISD::BR_CC, VT, Custom);
116 // Expand jump table branches as address arithmetic followed by an
118 setOperationAction(ISD::BR_JT, MVT::Other, Expand);
120 // Expand BRCOND into a BR_CC (see above).
121 setOperationAction(ISD::BRCOND, MVT::Other, Expand);
123 // Handle integer types.
124 for (unsigned I = MVT::FIRST_INTEGER_VALUETYPE;
125 I <= MVT::LAST_INTEGER_VALUETYPE;
127 MVT VT = MVT::SimpleValueType(I);
128 if (isTypeLegal(VT)) {
129 // Expand individual DIV and REMs into DIVREMs.
130 setOperationAction(ISD::SDIV, VT, Expand);
131 setOperationAction(ISD::UDIV, VT, Expand);
132 setOperationAction(ISD::SREM, VT, Expand);
133 setOperationAction(ISD::UREM, VT, Expand);
134 setOperationAction(ISD::SDIVREM, VT, Custom);
135 setOperationAction(ISD::UDIVREM, VT, Custom);
137 // Lower ATOMIC_LOAD and ATOMIC_STORE into normal volatile loads and
138 // stores, putting a serialization instruction after the stores.
139 setOperationAction(ISD::ATOMIC_LOAD, VT, Custom);
140 setOperationAction(ISD::ATOMIC_STORE, VT, Custom);
142 // No special instructions for these.
143 setOperationAction(ISD::CTPOP, VT, Expand);
144 setOperationAction(ISD::CTTZ, VT, Expand);
145 setOperationAction(ISD::CTTZ_ZERO_UNDEF, VT, Expand);
146 setOperationAction(ISD::CTLZ_ZERO_UNDEF, VT, Expand);
147 setOperationAction(ISD::ROTR, VT, Expand);
149 // Use *MUL_LOHI where possible instead of MULH*.
150 setOperationAction(ISD::MULHS, VT, Expand);
151 setOperationAction(ISD::MULHU, VT, Expand);
152 setOperationAction(ISD::SMUL_LOHI, VT, Custom);
153 setOperationAction(ISD::UMUL_LOHI, VT, Custom);
155 // We have instructions for signed but not unsigned FP conversion.
156 setOperationAction(ISD::FP_TO_UINT, VT, Expand);
160 // Type legalization will convert 8- and 16-bit atomic operations into
161 // forms that operate on i32s (but still keeping the original memory VT).
162 // Lower them into full i32 operations.
163 setOperationAction(ISD::ATOMIC_SWAP, MVT::i32, Custom);
164 setOperationAction(ISD::ATOMIC_LOAD_ADD, MVT::i32, Custom);
165 setOperationAction(ISD::ATOMIC_LOAD_SUB, MVT::i32, Custom);
166 setOperationAction(ISD::ATOMIC_LOAD_AND, MVT::i32, Custom);
167 setOperationAction(ISD::ATOMIC_LOAD_OR, MVT::i32, Custom);
168 setOperationAction(ISD::ATOMIC_LOAD_XOR, MVT::i32, Custom);
169 setOperationAction(ISD::ATOMIC_LOAD_NAND, MVT::i32, Custom);
170 setOperationAction(ISD::ATOMIC_LOAD_MIN, MVT::i32, Custom);
171 setOperationAction(ISD::ATOMIC_LOAD_MAX, MVT::i32, Custom);
172 setOperationAction(ISD::ATOMIC_LOAD_UMIN, MVT::i32, Custom);
173 setOperationAction(ISD::ATOMIC_LOAD_UMAX, MVT::i32, Custom);
174 setOperationAction(ISD::ATOMIC_CMP_SWAP, MVT::i32, Custom);
176 // We have instructions for signed but not unsigned FP conversion.
177 // Handle unsigned 32-bit types as signed 64-bit types.
178 setOperationAction(ISD::UINT_TO_FP, MVT::i32, Promote);
179 setOperationAction(ISD::UINT_TO_FP, MVT::i64, Expand);
181 // We have native support for a 64-bit CTLZ, via FLOGR.
182 setOperationAction(ISD::CTLZ, MVT::i32, Promote);
183 setOperationAction(ISD::CTLZ, MVT::i64, Legal);
185 // Give LowerOperation the chance to replace 64-bit ORs with subregs.
186 setOperationAction(ISD::OR, MVT::i64, Custom);
188 // FIXME: Can we support these natively?
189 setOperationAction(ISD::SRL_PARTS, MVT::i64, Expand);
190 setOperationAction(ISD::SHL_PARTS, MVT::i64, Expand);
191 setOperationAction(ISD::SRA_PARTS, MVT::i64, Expand);
193 // We have native instructions for i8, i16 and i32 extensions, but not i1.
194 setLoadExtAction(ISD::SEXTLOAD, MVT::i1, Promote);
195 setLoadExtAction(ISD::ZEXTLOAD, MVT::i1, Promote);
196 setLoadExtAction(ISD::EXTLOAD, MVT::i1, Promote);
197 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand);
199 // Handle the various types of symbolic address.
200 setOperationAction(ISD::ConstantPool, PtrVT, Custom);
201 setOperationAction(ISD::GlobalAddress, PtrVT, Custom);
202 setOperationAction(ISD::GlobalTLSAddress, PtrVT, Custom);
203 setOperationAction(ISD::BlockAddress, PtrVT, Custom);
204 setOperationAction(ISD::JumpTable, PtrVT, Custom);
206 // We need to handle dynamic allocations specially because of the
207 // 160-byte area at the bottom of the stack.
208 setOperationAction(ISD::DYNAMIC_STACKALLOC, PtrVT, Custom);
210 // Use custom expanders so that we can force the function to use
212 setOperationAction(ISD::STACKSAVE, MVT::Other, Custom);
213 setOperationAction(ISD::STACKRESTORE, MVT::Other, Custom);
215 // Handle prefetches with PFD or PFDRL.
216 setOperationAction(ISD::PREFETCH, MVT::Other, Custom);
218 // Handle floating-point types.
219 for (unsigned I = MVT::FIRST_FP_VALUETYPE;
220 I <= MVT::LAST_FP_VALUETYPE;
222 MVT VT = MVT::SimpleValueType(I);
223 if (isTypeLegal(VT)) {
224 // We can use FI for FRINT.
225 setOperationAction(ISD::FRINT, VT, Legal);
227 // We can use the extended form of FI for other rounding operations.
228 if (Subtarget.hasFPExtension()) {
229 setOperationAction(ISD::FNEARBYINT, VT, Legal);
230 setOperationAction(ISD::FFLOOR, VT, Legal);
231 setOperationAction(ISD::FCEIL, VT, Legal);
232 setOperationAction(ISD::FTRUNC, VT, Legal);
233 setOperationAction(ISD::FROUND, VT, Legal);
236 // No special instructions for these.
237 setOperationAction(ISD::FSIN, VT, Expand);
238 setOperationAction(ISD::FCOS, VT, Expand);
239 setOperationAction(ISD::FREM, VT, Expand);
243 // We have fused multiply-addition for f32 and f64 but not f128.
244 setOperationAction(ISD::FMA, MVT::f32, Legal);
245 setOperationAction(ISD::FMA, MVT::f64, Legal);
246 setOperationAction(ISD::FMA, MVT::f128, Expand);
248 // Needed so that we don't try to implement f128 constant loads using
249 // a load-and-extend of a f80 constant (in cases where the constant
250 // would fit in an f80).
251 setLoadExtAction(ISD::EXTLOAD, MVT::f80, Expand);
253 // Floating-point truncation and stores need to be done separately.
254 setTruncStoreAction(MVT::f64, MVT::f32, Expand);
255 setTruncStoreAction(MVT::f128, MVT::f32, Expand);
256 setTruncStoreAction(MVT::f128, MVT::f64, Expand);
258 // We have 64-bit FPR<->GPR moves, but need special handling for
260 setOperationAction(ISD::BITCAST, MVT::i32, Custom);
261 setOperationAction(ISD::BITCAST, MVT::f32, Custom);
263 // VASTART and VACOPY need to deal with the SystemZ-specific varargs
264 // structure, but VAEND is a no-op.
265 setOperationAction(ISD::VASTART, MVT::Other, Custom);
266 setOperationAction(ISD::VACOPY, MVT::Other, Custom);
267 setOperationAction(ISD::VAEND, MVT::Other, Expand);
269 // We want to use MVC in preference to even a single load/store pair.
270 MaxStoresPerMemcpy = 0;
271 MaxStoresPerMemcpyOptSize = 0;
273 // The main memset sequence is a byte store followed by an MVC.
274 // Two STC or MV..I stores win over that, but the kind of fused stores
275 // generated by target-independent code don't when the byte value is
276 // variable. E.g. "STC <reg>;MHI <reg>,257;STH <reg>" is not better
277 // than "STC;MVC". Handle the choice in target-specific code instead.
278 MaxStoresPerMemset = 0;
279 MaxStoresPerMemsetOptSize = 0;
282 EVT SystemZTargetLowering::getSetCCResultType(LLVMContext &, EVT VT) const {
285 return VT.changeVectorElementTypeToInteger();
288 bool SystemZTargetLowering::isFMAFasterThanFMulAndFAdd(EVT VT) const {
289 VT = VT.getScalarType();
294 switch (VT.getSimpleVT().SimpleTy) {
307 bool SystemZTargetLowering::isFPImmLegal(const APFloat &Imm, EVT VT) const {
308 // We can load zero using LZ?R and negative zero using LZ?R;LC?BR.
309 return Imm.isZero() || Imm.isNegZero();
312 bool SystemZTargetLowering::allowsUnalignedMemoryAccesses(EVT VT,
314 // Unaligned accesses should never be slower than the expanded version.
315 // We check specifically for aligned accesses in the few cases where
316 // they are required.
322 bool SystemZTargetLowering::isLegalAddressingMode(const AddrMode &AM,
324 // Punt on globals for now, although they can be used in limited
325 // RELATIVE LONG cases.
329 // Require a 20-bit signed offset.
330 if (!isInt<20>(AM.BaseOffs))
333 // Indexing is OK but no scale factor can be applied.
334 return AM.Scale == 0 || AM.Scale == 1;
337 bool SystemZTargetLowering::isTruncateFree(Type *FromType, Type *ToType) const {
338 if (!FromType->isIntegerTy() || !ToType->isIntegerTy())
340 unsigned FromBits = FromType->getPrimitiveSizeInBits();
341 unsigned ToBits = ToType->getPrimitiveSizeInBits();
342 return FromBits > ToBits;
345 bool SystemZTargetLowering::isTruncateFree(EVT FromVT, EVT ToVT) const {
346 if (!FromVT.isInteger() || !ToVT.isInteger())
348 unsigned FromBits = FromVT.getSizeInBits();
349 unsigned ToBits = ToVT.getSizeInBits();
350 return FromBits > ToBits;
353 //===----------------------------------------------------------------------===//
354 // Inline asm support
355 //===----------------------------------------------------------------------===//
357 TargetLowering::ConstraintType
358 SystemZTargetLowering::getConstraintType(const std::string &Constraint) const {
359 if (Constraint.size() == 1) {
360 switch (Constraint[0]) {
361 case 'a': // Address register
362 case 'd': // Data register (equivalent to 'r')
363 case 'f': // Floating-point register
364 case 'h': // High-part register
365 case 'r': // General-purpose register
366 return C_RegisterClass;
368 case 'Q': // Memory with base and unsigned 12-bit displacement
369 case 'R': // Likewise, plus an index
370 case 'S': // Memory with base and signed 20-bit displacement
371 case 'T': // Likewise, plus an index
372 case 'm': // Equivalent to 'T'.
375 case 'I': // Unsigned 8-bit constant
376 case 'J': // Unsigned 12-bit constant
377 case 'K': // Signed 16-bit constant
378 case 'L': // Signed 20-bit displacement (on all targets we support)
379 case 'M': // 0x7fffffff
386 return TargetLowering::getConstraintType(Constraint);
389 TargetLowering::ConstraintWeight SystemZTargetLowering::
390 getSingleConstraintMatchWeight(AsmOperandInfo &info,
391 const char *constraint) const {
392 ConstraintWeight weight = CW_Invalid;
393 Value *CallOperandVal = info.CallOperandVal;
394 // If we don't have a value, we can't do a match,
395 // but allow it at the lowest weight.
396 if (CallOperandVal == NULL)
398 Type *type = CallOperandVal->getType();
399 // Look at the constraint type.
400 switch (*constraint) {
402 weight = TargetLowering::getSingleConstraintMatchWeight(info, constraint);
405 case 'a': // Address register
406 case 'd': // Data register (equivalent to 'r')
407 case 'h': // High-part register
408 case 'r': // General-purpose register
409 if (CallOperandVal->getType()->isIntegerTy())
410 weight = CW_Register;
413 case 'f': // Floating-point register
414 if (type->isFloatingPointTy())
415 weight = CW_Register;
418 case 'I': // Unsigned 8-bit constant
419 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal))
420 if (isUInt<8>(C->getZExtValue()))
421 weight = CW_Constant;
424 case 'J': // Unsigned 12-bit constant
425 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal))
426 if (isUInt<12>(C->getZExtValue()))
427 weight = CW_Constant;
430 case 'K': // Signed 16-bit constant
431 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal))
432 if (isInt<16>(C->getSExtValue()))
433 weight = CW_Constant;
436 case 'L': // Signed 20-bit displacement (on all targets we support)
437 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal))
438 if (isInt<20>(C->getSExtValue()))
439 weight = CW_Constant;
442 case 'M': // 0x7fffffff
443 if (ConstantInt *C = dyn_cast<ConstantInt>(CallOperandVal))
444 if (C->getZExtValue() == 0x7fffffff)
445 weight = CW_Constant;
451 // Parse a "{tNNN}" register constraint for which the register type "t"
452 // has already been verified. MC is the class associated with "t" and
453 // Map maps 0-based register numbers to LLVM register numbers.
454 static std::pair<unsigned, const TargetRegisterClass *>
455 parseRegisterNumber(const std::string &Constraint,
456 const TargetRegisterClass *RC, const unsigned *Map) {
457 assert(*(Constraint.end()-1) == '}' && "Missing '}'");
458 if (isdigit(Constraint[2])) {
459 std::string Suffix(Constraint.data() + 2, Constraint.size() - 2);
460 unsigned Index = atoi(Suffix.c_str());
461 if (Index < 16 && Map[Index])
462 return std::make_pair(Map[Index], RC);
464 return std::make_pair(0u, static_cast<TargetRegisterClass*>(0));
467 std::pair<unsigned, const TargetRegisterClass *> SystemZTargetLowering::
468 getRegForInlineAsmConstraint(const std::string &Constraint, MVT VT) const {
469 if (Constraint.size() == 1) {
470 // GCC Constraint Letters
471 switch (Constraint[0]) {
473 case 'd': // Data register (equivalent to 'r')
474 case 'r': // General-purpose register
476 return std::make_pair(0U, &SystemZ::GR64BitRegClass);
477 else if (VT == MVT::i128)
478 return std::make_pair(0U, &SystemZ::GR128BitRegClass);
479 return std::make_pair(0U, &SystemZ::GR32BitRegClass);
481 case 'a': // Address register
483 return std::make_pair(0U, &SystemZ::ADDR64BitRegClass);
484 else if (VT == MVT::i128)
485 return std::make_pair(0U, &SystemZ::ADDR128BitRegClass);
486 return std::make_pair(0U, &SystemZ::ADDR32BitRegClass);
488 case 'h': // High-part register (an LLVM extension)
489 return std::make_pair(0U, &SystemZ::GRH32BitRegClass);
491 case 'f': // Floating-point register
493 return std::make_pair(0U, &SystemZ::FP64BitRegClass);
494 else if (VT == MVT::f128)
495 return std::make_pair(0U, &SystemZ::FP128BitRegClass);
496 return std::make_pair(0U, &SystemZ::FP32BitRegClass);
499 if (Constraint[0] == '{') {
500 // We need to override the default register parsing for GPRs and FPRs
501 // because the interpretation depends on VT. The internal names of
502 // the registers are also different from the external names
503 // (F0D and F0S instead of F0, etc.).
504 if (Constraint[1] == 'r') {
506 return parseRegisterNumber(Constraint, &SystemZ::GR32BitRegClass,
507 SystemZMC::GR32Regs);
509 return parseRegisterNumber(Constraint, &SystemZ::GR128BitRegClass,
510 SystemZMC::GR128Regs);
511 return parseRegisterNumber(Constraint, &SystemZ::GR64BitRegClass,
512 SystemZMC::GR64Regs);
514 if (Constraint[1] == 'f') {
516 return parseRegisterNumber(Constraint, &SystemZ::FP32BitRegClass,
517 SystemZMC::FP32Regs);
519 return parseRegisterNumber(Constraint, &SystemZ::FP128BitRegClass,
520 SystemZMC::FP128Regs);
521 return parseRegisterNumber(Constraint, &SystemZ::FP64BitRegClass,
522 SystemZMC::FP64Regs);
525 return TargetLowering::getRegForInlineAsmConstraint(Constraint, VT);
528 void SystemZTargetLowering::
529 LowerAsmOperandForConstraint(SDValue Op, std::string &Constraint,
530 std::vector<SDValue> &Ops,
531 SelectionDAG &DAG) const {
532 // Only support length 1 constraints for now.
533 if (Constraint.length() == 1) {
534 switch (Constraint[0]) {
535 case 'I': // Unsigned 8-bit constant
536 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op))
537 if (isUInt<8>(C->getZExtValue()))
538 Ops.push_back(DAG.getTargetConstant(C->getZExtValue(),
542 case 'J': // Unsigned 12-bit constant
543 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op))
544 if (isUInt<12>(C->getZExtValue()))
545 Ops.push_back(DAG.getTargetConstant(C->getZExtValue(),
549 case 'K': // Signed 16-bit constant
550 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op))
551 if (isInt<16>(C->getSExtValue()))
552 Ops.push_back(DAG.getTargetConstant(C->getSExtValue(),
556 case 'L': // Signed 20-bit displacement (on all targets we support)
557 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op))
558 if (isInt<20>(C->getSExtValue()))
559 Ops.push_back(DAG.getTargetConstant(C->getSExtValue(),
563 case 'M': // 0x7fffffff
564 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(Op))
565 if (C->getZExtValue() == 0x7fffffff)
566 Ops.push_back(DAG.getTargetConstant(C->getZExtValue(),
571 TargetLowering::LowerAsmOperandForConstraint(Op, Constraint, Ops, DAG);
574 //===----------------------------------------------------------------------===//
575 // Calling conventions
576 //===----------------------------------------------------------------------===//
578 #include "SystemZGenCallingConv.inc"
580 bool SystemZTargetLowering::allowTruncateForTailCall(Type *FromType,
581 Type *ToType) const {
582 return isTruncateFree(FromType, ToType);
585 bool SystemZTargetLowering::mayBeEmittedAsTailCall(CallInst *CI) const {
586 if (!CI->isTailCall())
591 // Value is a value that has been passed to us in the location described by VA
592 // (and so has type VA.getLocVT()). Convert Value to VA.getValVT(), chaining
593 // any loads onto Chain.
594 static SDValue convertLocVTToValVT(SelectionDAG &DAG, SDLoc DL,
595 CCValAssign &VA, SDValue Chain,
597 // If the argument has been promoted from a smaller type, insert an
598 // assertion to capture this.
599 if (VA.getLocInfo() == CCValAssign::SExt)
600 Value = DAG.getNode(ISD::AssertSext, DL, VA.getLocVT(), Value,
601 DAG.getValueType(VA.getValVT()));
602 else if (VA.getLocInfo() == CCValAssign::ZExt)
603 Value = DAG.getNode(ISD::AssertZext, DL, VA.getLocVT(), Value,
604 DAG.getValueType(VA.getValVT()));
607 Value = DAG.getNode(ISD::TRUNCATE, DL, VA.getValVT(), Value);
608 else if (VA.getLocInfo() == CCValAssign::Indirect)
609 Value = DAG.getLoad(VA.getValVT(), DL, Chain, Value,
610 MachinePointerInfo(), false, false, false, 0);
612 assert(VA.getLocInfo() == CCValAssign::Full && "Unsupported getLocInfo");
616 // Value is a value of type VA.getValVT() that we need to copy into
617 // the location described by VA. Return a copy of Value converted to
618 // VA.getValVT(). The caller is responsible for handling indirect values.
619 static SDValue convertValVTToLocVT(SelectionDAG &DAG, SDLoc DL,
620 CCValAssign &VA, SDValue Value) {
621 switch (VA.getLocInfo()) {
622 case CCValAssign::SExt:
623 return DAG.getNode(ISD::SIGN_EXTEND, DL, VA.getLocVT(), Value);
624 case CCValAssign::ZExt:
625 return DAG.getNode(ISD::ZERO_EXTEND, DL, VA.getLocVT(), Value);
626 case CCValAssign::AExt:
627 return DAG.getNode(ISD::ANY_EXTEND, DL, VA.getLocVT(), Value);
628 case CCValAssign::Full:
631 llvm_unreachable("Unhandled getLocInfo()");
635 SDValue SystemZTargetLowering::
636 LowerFormalArguments(SDValue Chain, CallingConv::ID CallConv, bool IsVarArg,
637 const SmallVectorImpl<ISD::InputArg> &Ins,
638 SDLoc DL, SelectionDAG &DAG,
639 SmallVectorImpl<SDValue> &InVals) const {
640 MachineFunction &MF = DAG.getMachineFunction();
641 MachineFrameInfo *MFI = MF.getFrameInfo();
642 MachineRegisterInfo &MRI = MF.getRegInfo();
643 SystemZMachineFunctionInfo *FuncInfo =
644 MF.getInfo<SystemZMachineFunctionInfo>();
645 const SystemZFrameLowering *TFL =
646 static_cast<const SystemZFrameLowering *>(TM.getFrameLowering());
648 // Assign locations to all of the incoming arguments.
649 SmallVector<CCValAssign, 16> ArgLocs;
650 CCState CCInfo(CallConv, IsVarArg, MF, TM, ArgLocs, *DAG.getContext());
651 CCInfo.AnalyzeFormalArguments(Ins, CC_SystemZ);
653 unsigned NumFixedGPRs = 0;
654 unsigned NumFixedFPRs = 0;
655 for (unsigned I = 0, E = ArgLocs.size(); I != E; ++I) {
657 CCValAssign &VA = ArgLocs[I];
658 EVT LocVT = VA.getLocVT();
660 // Arguments passed in registers
661 const TargetRegisterClass *RC;
662 switch (LocVT.getSimpleVT().SimpleTy) {
664 // Integers smaller than i64 should be promoted to i64.
665 llvm_unreachable("Unexpected argument type");
668 RC = &SystemZ::GR32BitRegClass;
672 RC = &SystemZ::GR64BitRegClass;
676 RC = &SystemZ::FP32BitRegClass;
680 RC = &SystemZ::FP64BitRegClass;
684 unsigned VReg = MRI.createVirtualRegister(RC);
685 MRI.addLiveIn(VA.getLocReg(), VReg);
686 ArgValue = DAG.getCopyFromReg(Chain, DL, VReg, LocVT);
688 assert(VA.isMemLoc() && "Argument not register or memory");
690 // Create the frame index object for this incoming parameter.
691 int FI = MFI->CreateFixedObject(LocVT.getSizeInBits() / 8,
692 VA.getLocMemOffset(), true);
694 // Create the SelectionDAG nodes corresponding to a load
695 // from this parameter. Unpromoted ints and floats are
696 // passed as right-justified 8-byte values.
697 EVT PtrVT = getPointerTy();
698 SDValue FIN = DAG.getFrameIndex(FI, PtrVT);
699 if (VA.getLocVT() == MVT::i32 || VA.getLocVT() == MVT::f32)
700 FIN = DAG.getNode(ISD::ADD, DL, PtrVT, FIN, DAG.getIntPtrConstant(4));
701 ArgValue = DAG.getLoad(LocVT, DL, Chain, FIN,
702 MachinePointerInfo::getFixedStack(FI),
703 false, false, false, 0);
706 // Convert the value of the argument register into the value that's
708 InVals.push_back(convertLocVTToValVT(DAG, DL, VA, Chain, ArgValue));
712 // Save the number of non-varargs registers for later use by va_start, etc.
713 FuncInfo->setVarArgsFirstGPR(NumFixedGPRs);
714 FuncInfo->setVarArgsFirstFPR(NumFixedFPRs);
716 // Likewise the address (in the form of a frame index) of where the
717 // first stack vararg would be. The 1-byte size here is arbitrary.
718 int64_t StackSize = CCInfo.getNextStackOffset();
719 FuncInfo->setVarArgsFrameIndex(MFI->CreateFixedObject(1, StackSize, true));
721 // ...and a similar frame index for the caller-allocated save area
722 // that will be used to store the incoming registers.
723 int64_t RegSaveOffset = TFL->getOffsetOfLocalArea();
724 unsigned RegSaveIndex = MFI->CreateFixedObject(1, RegSaveOffset, true);
725 FuncInfo->setRegSaveFrameIndex(RegSaveIndex);
727 // Store the FPR varargs in the reserved frame slots. (We store the
728 // GPRs as part of the prologue.)
729 if (NumFixedFPRs < SystemZ::NumArgFPRs) {
730 SDValue MemOps[SystemZ::NumArgFPRs];
731 for (unsigned I = NumFixedFPRs; I < SystemZ::NumArgFPRs; ++I) {
732 unsigned Offset = TFL->getRegSpillOffset(SystemZ::ArgFPRs[I]);
733 int FI = MFI->CreateFixedObject(8, RegSaveOffset + Offset, true);
734 SDValue FIN = DAG.getFrameIndex(FI, getPointerTy());
735 unsigned VReg = MF.addLiveIn(SystemZ::ArgFPRs[I],
736 &SystemZ::FP64BitRegClass);
737 SDValue ArgValue = DAG.getCopyFromReg(Chain, DL, VReg, MVT::f64);
738 MemOps[I] = DAG.getStore(ArgValue.getValue(1), DL, ArgValue, FIN,
739 MachinePointerInfo::getFixedStack(FI),
743 // Join the stores, which are independent of one another.
744 Chain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other,
745 &MemOps[NumFixedFPRs],
746 SystemZ::NumArgFPRs - NumFixedFPRs);
753 static bool canUseSiblingCall(CCState ArgCCInfo,
754 SmallVectorImpl<CCValAssign> &ArgLocs) {
755 // Punt if there are any indirect or stack arguments, or if the call
756 // needs the call-saved argument register R6.
757 for (unsigned I = 0, E = ArgLocs.size(); I != E; ++I) {
758 CCValAssign &VA = ArgLocs[I];
759 if (VA.getLocInfo() == CCValAssign::Indirect)
763 unsigned Reg = VA.getLocReg();
764 if (Reg == SystemZ::R6H || Reg == SystemZ::R6L || Reg == SystemZ::R6D)
771 SystemZTargetLowering::LowerCall(CallLoweringInfo &CLI,
772 SmallVectorImpl<SDValue> &InVals) const {
773 SelectionDAG &DAG = CLI.DAG;
775 SmallVectorImpl<ISD::OutputArg> &Outs = CLI.Outs;
776 SmallVectorImpl<SDValue> &OutVals = CLI.OutVals;
777 SmallVectorImpl<ISD::InputArg> &Ins = CLI.Ins;
778 SDValue Chain = CLI.Chain;
779 SDValue Callee = CLI.Callee;
780 bool &IsTailCall = CLI.IsTailCall;
781 CallingConv::ID CallConv = CLI.CallConv;
782 bool IsVarArg = CLI.IsVarArg;
783 MachineFunction &MF = DAG.getMachineFunction();
784 EVT PtrVT = getPointerTy();
786 // Analyze the operands of the call, assigning locations to each operand.
787 SmallVector<CCValAssign, 16> ArgLocs;
788 CCState ArgCCInfo(CallConv, IsVarArg, MF, TM, ArgLocs, *DAG.getContext());
789 ArgCCInfo.AnalyzeCallOperands(Outs, CC_SystemZ);
791 // We don't support GuaranteedTailCallOpt, only automatically-detected
793 if (IsTailCall && !canUseSiblingCall(ArgCCInfo, ArgLocs))
796 // Get a count of how many bytes are to be pushed on the stack.
797 unsigned NumBytes = ArgCCInfo.getNextStackOffset();
799 // Mark the start of the call.
801 Chain = DAG.getCALLSEQ_START(Chain, DAG.getConstant(NumBytes, PtrVT, true),
804 // Copy argument values to their designated locations.
805 SmallVector<std::pair<unsigned, SDValue>, 9> RegsToPass;
806 SmallVector<SDValue, 8> MemOpChains;
808 for (unsigned I = 0, E = ArgLocs.size(); I != E; ++I) {
809 CCValAssign &VA = ArgLocs[I];
810 SDValue ArgValue = OutVals[I];
812 if (VA.getLocInfo() == CCValAssign::Indirect) {
813 // Store the argument in a stack slot and pass its address.
814 SDValue SpillSlot = DAG.CreateStackTemporary(VA.getValVT());
815 int FI = cast<FrameIndexSDNode>(SpillSlot)->getIndex();
816 MemOpChains.push_back(DAG.getStore(Chain, DL, ArgValue, SpillSlot,
817 MachinePointerInfo::getFixedStack(FI),
819 ArgValue = SpillSlot;
821 ArgValue = convertValVTToLocVT(DAG, DL, VA, ArgValue);
824 // Queue up the argument copies and emit them at the end.
825 RegsToPass.push_back(std::make_pair(VA.getLocReg(), ArgValue));
827 assert(VA.isMemLoc() && "Argument not register or memory");
829 // Work out the address of the stack slot. Unpromoted ints and
830 // floats are passed as right-justified 8-byte values.
831 if (!StackPtr.getNode())
832 StackPtr = DAG.getCopyFromReg(Chain, DL, SystemZ::R15D, PtrVT);
833 unsigned Offset = SystemZMC::CallFrameSize + VA.getLocMemOffset();
834 if (VA.getLocVT() == MVT::i32 || VA.getLocVT() == MVT::f32)
836 SDValue Address = DAG.getNode(ISD::ADD, DL, PtrVT, StackPtr,
837 DAG.getIntPtrConstant(Offset));
840 MemOpChains.push_back(DAG.getStore(Chain, DL, ArgValue, Address,
841 MachinePointerInfo(),
846 // Join the stores, which are independent of one another.
847 if (!MemOpChains.empty())
848 Chain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other,
849 &MemOpChains[0], MemOpChains.size());
851 // Accept direct calls by converting symbolic call addresses to the
852 // associated Target* opcodes. Force %r1 to be used for indirect
855 if (GlobalAddressSDNode *G = dyn_cast<GlobalAddressSDNode>(Callee)) {
856 Callee = DAG.getTargetGlobalAddress(G->getGlobal(), DL, PtrVT);
857 Callee = DAG.getNode(SystemZISD::PCREL_WRAPPER, DL, PtrVT, Callee);
858 } else if (ExternalSymbolSDNode *E = dyn_cast<ExternalSymbolSDNode>(Callee)) {
859 Callee = DAG.getTargetExternalSymbol(E->getSymbol(), PtrVT);
860 Callee = DAG.getNode(SystemZISD::PCREL_WRAPPER, DL, PtrVT, Callee);
861 } else if (IsTailCall) {
862 Chain = DAG.getCopyToReg(Chain, DL, SystemZ::R1D, Callee, Glue);
863 Glue = Chain.getValue(1);
864 Callee = DAG.getRegister(SystemZ::R1D, Callee.getValueType());
867 // Build a sequence of copy-to-reg nodes, chained and glued together.
868 for (unsigned I = 0, E = RegsToPass.size(); I != E; ++I) {
869 Chain = DAG.getCopyToReg(Chain, DL, RegsToPass[I].first,
870 RegsToPass[I].second, Glue);
871 Glue = Chain.getValue(1);
874 // The first call operand is the chain and the second is the target address.
875 SmallVector<SDValue, 8> Ops;
876 Ops.push_back(Chain);
877 Ops.push_back(Callee);
879 // Add argument registers to the end of the list so that they are
880 // known live into the call.
881 for (unsigned I = 0, E = RegsToPass.size(); I != E; ++I)
882 Ops.push_back(DAG.getRegister(RegsToPass[I].first,
883 RegsToPass[I].second.getValueType()));
885 // Glue the call to the argument copies, if any.
890 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
892 return DAG.getNode(SystemZISD::SIBCALL, DL, NodeTys, &Ops[0], Ops.size());
893 Chain = DAG.getNode(SystemZISD::CALL, DL, NodeTys, &Ops[0], Ops.size());
894 Glue = Chain.getValue(1);
896 // Mark the end of the call, which is glued to the call itself.
897 Chain = DAG.getCALLSEQ_END(Chain,
898 DAG.getConstant(NumBytes, PtrVT, true),
899 DAG.getConstant(0, PtrVT, true),
901 Glue = Chain.getValue(1);
903 // Assign locations to each value returned by this call.
904 SmallVector<CCValAssign, 16> RetLocs;
905 CCState RetCCInfo(CallConv, IsVarArg, MF, TM, RetLocs, *DAG.getContext());
906 RetCCInfo.AnalyzeCallResult(Ins, RetCC_SystemZ);
908 // Copy all of the result registers out of their specified physreg.
909 for (unsigned I = 0, E = RetLocs.size(); I != E; ++I) {
910 CCValAssign &VA = RetLocs[I];
912 // Copy the value out, gluing the copy to the end of the call sequence.
913 SDValue RetValue = DAG.getCopyFromReg(Chain, DL, VA.getLocReg(),
914 VA.getLocVT(), Glue);
915 Chain = RetValue.getValue(1);
916 Glue = RetValue.getValue(2);
918 // Convert the value of the return register into the value that's
920 InVals.push_back(convertLocVTToValVT(DAG, DL, VA, Chain, RetValue));
927 SystemZTargetLowering::LowerReturn(SDValue Chain,
928 CallingConv::ID CallConv, bool IsVarArg,
929 const SmallVectorImpl<ISD::OutputArg> &Outs,
930 const SmallVectorImpl<SDValue> &OutVals,
931 SDLoc DL, SelectionDAG &DAG) const {
932 MachineFunction &MF = DAG.getMachineFunction();
934 // Assign locations to each returned value.
935 SmallVector<CCValAssign, 16> RetLocs;
936 CCState RetCCInfo(CallConv, IsVarArg, MF, TM, RetLocs, *DAG.getContext());
937 RetCCInfo.AnalyzeReturn(Outs, RetCC_SystemZ);
939 // Quick exit for void returns
941 return DAG.getNode(SystemZISD::RET_FLAG, DL, MVT::Other, Chain);
943 // Copy the result values into the output registers.
945 SmallVector<SDValue, 4> RetOps;
946 RetOps.push_back(Chain);
947 for (unsigned I = 0, E = RetLocs.size(); I != E; ++I) {
948 CCValAssign &VA = RetLocs[I];
949 SDValue RetValue = OutVals[I];
951 // Make the return register live on exit.
952 assert(VA.isRegLoc() && "Can only return in registers!");
954 // Promote the value as required.
955 RetValue = convertValVTToLocVT(DAG, DL, VA, RetValue);
957 // Chain and glue the copies together.
958 unsigned Reg = VA.getLocReg();
959 Chain = DAG.getCopyToReg(Chain, DL, Reg, RetValue, Glue);
960 Glue = Chain.getValue(1);
961 RetOps.push_back(DAG.getRegister(Reg, VA.getLocVT()));
964 // Update chain and glue.
967 RetOps.push_back(Glue);
969 return DAG.getNode(SystemZISD::RET_FLAG, DL, MVT::Other,
970 RetOps.data(), RetOps.size());
973 SDValue SystemZTargetLowering::
974 prepareVolatileOrAtomicLoad(SDValue Chain, SDLoc DL, SelectionDAG &DAG) const {
975 return DAG.getNode(SystemZISD::SERIALIZE, DL, MVT::Other, Chain);
978 // CC is a comparison that will be implemented using an integer or
979 // floating-point comparison. Return the condition code mask for
980 // a branch on true. In the integer case, CCMASK_CMP_UO is set for
981 // unsigned comparisons and clear for signed ones. In the floating-point
982 // case, CCMASK_CMP_UO has its normal mask meaning (unordered).
983 static unsigned CCMaskForCondCode(ISD::CondCode CC) {
985 case ISD::SET##X: return SystemZ::CCMASK_CMP_##X; \
986 case ISD::SETO##X: return SystemZ::CCMASK_CMP_##X; \
987 case ISD::SETU##X: return SystemZ::CCMASK_CMP_UO | SystemZ::CCMASK_CMP_##X
991 llvm_unreachable("Invalid integer condition!");
1000 case ISD::SETO: return SystemZ::CCMASK_CMP_O;
1001 case ISD::SETUO: return SystemZ::CCMASK_CMP_UO;
1006 // Return a sequence for getting a 1 from an IPM result when CC has a
1007 // value in CCMask and a 0 when CC has a value in CCValid & ~CCMask.
1008 // The handling of CC values outside CCValid doesn't matter.
1009 static IPMConversion getIPMConversion(unsigned CCValid, unsigned CCMask) {
1010 // Deal with cases where the result can be taken directly from a bit
1011 // of the IPM result.
1012 if (CCMask == (CCValid & (SystemZ::CCMASK_1 | SystemZ::CCMASK_3)))
1013 return IPMConversion(0, 0, SystemZ::IPM_CC);
1014 if (CCMask == (CCValid & (SystemZ::CCMASK_2 | SystemZ::CCMASK_3)))
1015 return IPMConversion(0, 0, SystemZ::IPM_CC + 1);
1017 // Deal with cases where we can add a value to force the sign bit
1018 // to contain the right value. Putting the bit in 31 means we can
1019 // use SRL rather than RISBG(L), and also makes it easier to get a
1020 // 0/-1 value, so it has priority over the other tests below.
1022 // These sequences rely on the fact that the upper two bits of the
1023 // IPM result are zero.
1024 uint64_t TopBit = uint64_t(1) << 31;
1025 if (CCMask == (CCValid & SystemZ::CCMASK_0))
1026 return IPMConversion(0, -(1 << SystemZ::IPM_CC), 31);
1027 if (CCMask == (CCValid & (SystemZ::CCMASK_0 | SystemZ::CCMASK_1)))
1028 return IPMConversion(0, -(2 << SystemZ::IPM_CC), 31);
1029 if (CCMask == (CCValid & (SystemZ::CCMASK_0
1031 | SystemZ::CCMASK_2)))
1032 return IPMConversion(0, -(3 << SystemZ::IPM_CC), 31);
1033 if (CCMask == (CCValid & SystemZ::CCMASK_3))
1034 return IPMConversion(0, TopBit - (3 << SystemZ::IPM_CC), 31);
1035 if (CCMask == (CCValid & (SystemZ::CCMASK_1
1037 | SystemZ::CCMASK_3)))
1038 return IPMConversion(0, TopBit - (1 << SystemZ::IPM_CC), 31);
1040 // Next try inverting the value and testing a bit. 0/1 could be
1041 // handled this way too, but we dealt with that case above.
1042 if (CCMask == (CCValid & (SystemZ::CCMASK_0 | SystemZ::CCMASK_2)))
1043 return IPMConversion(-1, 0, SystemZ::IPM_CC);
1045 // Handle cases where adding a value forces a non-sign bit to contain
1047 if (CCMask == (CCValid & (SystemZ::CCMASK_1 | SystemZ::CCMASK_2)))
1048 return IPMConversion(0, 1 << SystemZ::IPM_CC, SystemZ::IPM_CC + 1);
1049 if (CCMask == (CCValid & (SystemZ::CCMASK_0 | SystemZ::CCMASK_3)))
1050 return IPMConversion(0, -(1 << SystemZ::IPM_CC), SystemZ::IPM_CC + 1);
1052 // The remaing cases are 1, 2, 0/1/3 and 0/2/3. All these are
1053 // can be done by inverting the low CC bit and applying one of the
1054 // sign-based extractions above.
1055 if (CCMask == (CCValid & SystemZ::CCMASK_1))
1056 return IPMConversion(1 << SystemZ::IPM_CC, -(1 << SystemZ::IPM_CC), 31);
1057 if (CCMask == (CCValid & SystemZ::CCMASK_2))
1058 return IPMConversion(1 << SystemZ::IPM_CC,
1059 TopBit - (3 << SystemZ::IPM_CC), 31);
1060 if (CCMask == (CCValid & (SystemZ::CCMASK_0
1062 | SystemZ::CCMASK_3)))
1063 return IPMConversion(1 << SystemZ::IPM_CC, -(3 << SystemZ::IPM_CC), 31);
1064 if (CCMask == (CCValid & (SystemZ::CCMASK_0
1066 | SystemZ::CCMASK_3)))
1067 return IPMConversion(1 << SystemZ::IPM_CC,
1068 TopBit - (1 << SystemZ::IPM_CC), 31);
1070 llvm_unreachable("Unexpected CC combination");
1073 // If a comparison described by IsUnsigned, CCMask, CmpOp0 and CmpOp1
1074 // can be converted to a comparison against zero, adjust the operands
1076 static void adjustZeroCmp(SelectionDAG &DAG, bool &IsUnsigned,
1077 SDValue &CmpOp0, SDValue &CmpOp1,
1082 ConstantSDNode *ConstOp1 = dyn_cast<ConstantSDNode>(CmpOp1.getNode());
1086 int64_t Value = ConstOp1->getSExtValue();
1087 if ((Value == -1 && CCMask == SystemZ::CCMASK_CMP_GT) ||
1088 (Value == -1 && CCMask == SystemZ::CCMASK_CMP_LE) ||
1089 (Value == 1 && CCMask == SystemZ::CCMASK_CMP_LT) ||
1090 (Value == 1 && CCMask == SystemZ::CCMASK_CMP_GE)) {
1091 CCMask ^= SystemZ::CCMASK_CMP_EQ;
1092 CmpOp1 = DAG.getConstant(0, CmpOp1.getValueType());
1096 // If a comparison described by IsUnsigned, CCMask, CmpOp0 and CmpOp1
1097 // is suitable for CLI(Y), CHHSI or CLHHSI, adjust the operands as necessary.
1098 static void adjustSubwordCmp(SelectionDAG &DAG, bool &IsUnsigned,
1099 SDValue &CmpOp0, SDValue &CmpOp1,
1101 // For us to make any changes, it must a comparison between a single-use
1102 // load and a constant.
1103 if (!CmpOp0.hasOneUse() ||
1104 CmpOp0.getOpcode() != ISD::LOAD ||
1105 CmpOp1.getOpcode() != ISD::Constant)
1108 // We must have an 8- or 16-bit load.
1109 LoadSDNode *Load = cast<LoadSDNode>(CmpOp0);
1110 unsigned NumBits = Load->getMemoryVT().getStoreSizeInBits();
1111 if (NumBits != 8 && NumBits != 16)
1114 // The load must be an extending one and the constant must be within the
1115 // range of the unextended value.
1116 ConstantSDNode *Constant = cast<ConstantSDNode>(CmpOp1);
1117 uint64_t Value = Constant->getZExtValue();
1118 uint64_t Mask = (1 << NumBits) - 1;
1119 if (Load->getExtensionType() == ISD::SEXTLOAD) {
1120 int64_t SignedValue = Constant->getSExtValue();
1121 if (uint64_t(SignedValue) + (1ULL << (NumBits - 1)) > Mask)
1123 // Unsigned comparison between two sign-extended values is equivalent
1124 // to unsigned comparison between two zero-extended values.
1127 else if (CCMask == SystemZ::CCMASK_CMP_EQ ||
1128 CCMask == SystemZ::CCMASK_CMP_NE)
1129 // Any choice of IsUnsigned is OK for equality comparisons.
1130 // We could use either CHHSI or CLHHSI for 16-bit comparisons,
1131 // but since we use CLHHSI for zero extensions, it seems better
1132 // to be consistent and do the same here.
1133 Value &= Mask, IsUnsigned = true;
1134 else if (NumBits == 8) {
1135 // Try to treat the comparison as unsigned, so that we can use CLI.
1136 // Adjust CCMask and Value as necessary.
1137 if (Value == 0 && CCMask == SystemZ::CCMASK_CMP_LT)
1138 // Test whether the high bit of the byte is set.
1139 Value = 127, CCMask = SystemZ::CCMASK_CMP_GT, IsUnsigned = true;
1140 else if (Value == 0 && CCMask == SystemZ::CCMASK_CMP_GE)
1141 // Test whether the high bit of the byte is clear.
1142 Value = 128, CCMask = SystemZ::CCMASK_CMP_LT, IsUnsigned = true;
1144 // No instruction exists for this combination.
1147 } else if (Load->getExtensionType() == ISD::ZEXTLOAD) {
1150 // Signed comparison between two zero-extended values is equivalent
1151 // to unsigned comparison.
1156 // Make sure that the first operand is an i32 of the right extension type.
1157 ISD::LoadExtType ExtType = IsUnsigned ? ISD::ZEXTLOAD : ISD::SEXTLOAD;
1158 if (CmpOp0.getValueType() != MVT::i32 ||
1159 Load->getExtensionType() != ExtType)
1160 CmpOp0 = DAG.getExtLoad(ExtType, SDLoc(Load), MVT::i32,
1161 Load->getChain(), Load->getBasePtr(),
1162 Load->getPointerInfo(), Load->getMemoryVT(),
1163 Load->isVolatile(), Load->isNonTemporal(),
1164 Load->getAlignment());
1166 // Make sure that the second operand is an i32 with the right value.
1167 if (CmpOp1.getValueType() != MVT::i32 ||
1168 Value != Constant->getZExtValue())
1169 CmpOp1 = DAG.getConstant(Value, MVT::i32);
1172 // Return true if Op is either an unextended load, or a load suitable
1173 // for integer register-memory comparisons of type ICmpType.
1174 static bool isNaturalMemoryOperand(SDValue Op, unsigned ICmpType) {
1175 LoadSDNode *Load = dyn_cast<LoadSDNode>(Op.getNode());
1177 // There are no instructions to compare a register with a memory byte.
1178 if (Load->getMemoryVT() == MVT::i8)
1180 // Otherwise decide on extension type.
1181 switch (Load->getExtensionType()) {
1182 case ISD::NON_EXTLOAD:
1185 return ICmpType != SystemZICMP::UnsignedOnly;
1187 return ICmpType != SystemZICMP::SignedOnly;
1195 // Return true if it is better to swap comparison operands Op0 and Op1.
1196 // ICmpType is the type of an integer comparison.
1197 static bool shouldSwapCmpOperands(SDValue Op0, SDValue Op1,
1198 unsigned ICmpType) {
1199 // Leave f128 comparisons alone, since they have no memory forms.
1200 if (Op0.getValueType() == MVT::f128)
1203 // Always keep a floating-point constant second, since comparisons with
1204 // zero can use LOAD TEST and comparisons with other constants make a
1205 // natural memory operand.
1206 if (isa<ConstantFPSDNode>(Op1))
1209 // Never swap comparisons with zero since there are many ways to optimize
1211 ConstantSDNode *COp1 = dyn_cast<ConstantSDNode>(Op1);
1212 if (COp1 && COp1->getZExtValue() == 0)
1215 // Also keep natural memory operands second if the loaded value is
1216 // only used here. Several comparisons have memory forms.
1217 if (isNaturalMemoryOperand(Op1, ICmpType) && Op1.hasOneUse())
1220 // Look for cases where Cmp0 is a single-use load and Cmp1 isn't.
1221 // In that case we generally prefer the memory to be second.
1222 if (isNaturalMemoryOperand(Op0, ICmpType) && Op0.hasOneUse()) {
1223 // The only exceptions are when the second operand is a constant and
1224 // we can use things like CHHSI.
1227 // The unsigned memory-immediate instructions can handle 16-bit
1228 // unsigned integers.
1229 if (ICmpType != SystemZICMP::SignedOnly &&
1230 isUInt<16>(COp1->getZExtValue()))
1232 // The signed memory-immediate instructions can handle 16-bit
1234 if (ICmpType != SystemZICMP::UnsignedOnly &&
1235 isInt<16>(COp1->getSExtValue()))
1240 // Try to promote the use of CGFR and CLGFR.
1241 unsigned Opcode0 = Op0.getOpcode();
1242 if (ICmpType != SystemZICMP::UnsignedOnly && Opcode0 == ISD::SIGN_EXTEND)
1244 if (ICmpType != SystemZICMP::SignedOnly && Opcode0 == ISD::ZERO_EXTEND)
1246 if (ICmpType != SystemZICMP::SignedOnly &&
1247 Opcode0 == ISD::AND &&
1248 Op0.getOperand(1).getOpcode() == ISD::Constant &&
1249 cast<ConstantSDNode>(Op0.getOperand(1))->getZExtValue() == 0xffffffff)
1255 // Return true if shift operation N has an in-range constant shift value.
1256 // Store it in ShiftVal if so.
1257 static bool isSimpleShift(SDValue N, unsigned &ShiftVal) {
1258 ConstantSDNode *Shift = dyn_cast<ConstantSDNode>(N.getOperand(1));
1262 uint64_t Amount = Shift->getZExtValue();
1263 if (Amount >= N.getValueType().getSizeInBits())
1270 // Check whether an AND with Mask is suitable for a TEST UNDER MASK
1271 // instruction and whether the CC value is descriptive enough to handle
1272 // a comparison of type Opcode between the AND result and CmpVal.
1273 // CCMask says which comparison result is being tested and BitSize is
1274 // the number of bits in the operands. If TEST UNDER MASK can be used,
1275 // return the corresponding CC mask, otherwise return 0.
1276 static unsigned getTestUnderMaskCond(unsigned BitSize, unsigned CCMask,
1277 uint64_t Mask, uint64_t CmpVal,
1278 unsigned ICmpType) {
1279 assert(Mask != 0 && "ANDs with zero should have been removed by now");
1281 // Check whether the mask is suitable for TMHH, TMHL, TMLH or TMLL.
1282 if (!SystemZ::isImmLL(Mask) && !SystemZ::isImmLH(Mask) &&
1283 !SystemZ::isImmHL(Mask) && !SystemZ::isImmHH(Mask))
1286 // Work out the masks for the lowest and highest bits.
1287 unsigned HighShift = 63 - countLeadingZeros(Mask);
1288 uint64_t High = uint64_t(1) << HighShift;
1289 uint64_t Low = uint64_t(1) << countTrailingZeros(Mask);
1291 // Signed ordered comparisons are effectively unsigned if the sign
1293 bool EffectivelyUnsigned = (ICmpType != SystemZICMP::SignedOnly);
1295 // Check for equality comparisons with 0, or the equivalent.
1297 if (CCMask == SystemZ::CCMASK_CMP_EQ)
1298 return SystemZ::CCMASK_TM_ALL_0;
1299 if (CCMask == SystemZ::CCMASK_CMP_NE)
1300 return SystemZ::CCMASK_TM_SOME_1;
1302 if (EffectivelyUnsigned && CmpVal <= Low) {
1303 if (CCMask == SystemZ::CCMASK_CMP_LT)
1304 return SystemZ::CCMASK_TM_ALL_0;
1305 if (CCMask == SystemZ::CCMASK_CMP_GE)
1306 return SystemZ::CCMASK_TM_SOME_1;
1308 if (EffectivelyUnsigned && CmpVal < Low) {
1309 if (CCMask == SystemZ::CCMASK_CMP_LE)
1310 return SystemZ::CCMASK_TM_ALL_0;
1311 if (CCMask == SystemZ::CCMASK_CMP_GT)
1312 return SystemZ::CCMASK_TM_SOME_1;
1315 // Check for equality comparisons with the mask, or the equivalent.
1316 if (CmpVal == Mask) {
1317 if (CCMask == SystemZ::CCMASK_CMP_EQ)
1318 return SystemZ::CCMASK_TM_ALL_1;
1319 if (CCMask == SystemZ::CCMASK_CMP_NE)
1320 return SystemZ::CCMASK_TM_SOME_0;
1322 if (EffectivelyUnsigned && CmpVal >= Mask - Low && CmpVal < Mask) {
1323 if (CCMask == SystemZ::CCMASK_CMP_GT)
1324 return SystemZ::CCMASK_TM_ALL_1;
1325 if (CCMask == SystemZ::CCMASK_CMP_LE)
1326 return SystemZ::CCMASK_TM_SOME_0;
1328 if (EffectivelyUnsigned && CmpVal > Mask - Low && CmpVal <= Mask) {
1329 if (CCMask == SystemZ::CCMASK_CMP_GE)
1330 return SystemZ::CCMASK_TM_ALL_1;
1331 if (CCMask == SystemZ::CCMASK_CMP_LT)
1332 return SystemZ::CCMASK_TM_SOME_0;
1335 // Check for ordered comparisons with the top bit.
1336 if (EffectivelyUnsigned && CmpVal >= Mask - High && CmpVal < High) {
1337 if (CCMask == SystemZ::CCMASK_CMP_LE)
1338 return SystemZ::CCMASK_TM_MSB_0;
1339 if (CCMask == SystemZ::CCMASK_CMP_GT)
1340 return SystemZ::CCMASK_TM_MSB_1;
1342 if (EffectivelyUnsigned && CmpVal > Mask - High && CmpVal <= High) {
1343 if (CCMask == SystemZ::CCMASK_CMP_LT)
1344 return SystemZ::CCMASK_TM_MSB_0;
1345 if (CCMask == SystemZ::CCMASK_CMP_GE)
1346 return SystemZ::CCMASK_TM_MSB_1;
1349 // If there are just two bits, we can do equality checks for Low and High
1351 if (Mask == Low + High) {
1352 if (CCMask == SystemZ::CCMASK_CMP_EQ && CmpVal == Low)
1353 return SystemZ::CCMASK_TM_MIXED_MSB_0;
1354 if (CCMask == SystemZ::CCMASK_CMP_NE && CmpVal == Low)
1355 return SystemZ::CCMASK_TM_MIXED_MSB_0 ^ SystemZ::CCMASK_ANY;
1356 if (CCMask == SystemZ::CCMASK_CMP_EQ && CmpVal == High)
1357 return SystemZ::CCMASK_TM_MIXED_MSB_1;
1358 if (CCMask == SystemZ::CCMASK_CMP_NE && CmpVal == High)
1359 return SystemZ::CCMASK_TM_MIXED_MSB_1 ^ SystemZ::CCMASK_ANY;
1362 // Looks like we've exhausted our options.
1366 // See whether the comparison (Opcode CmpOp0, CmpOp1, ICmpType) can be
1367 // implemented as a TEST UNDER MASK instruction when the condition being
1368 // tested is as described by CCValid and CCMask. Update the arguments
1369 // with the TM version if so.
1370 static void adjustForTestUnderMask(SelectionDAG &DAG, unsigned &Opcode,
1371 SDValue &CmpOp0, SDValue &CmpOp1,
1372 unsigned &CCValid, unsigned &CCMask,
1373 unsigned &ICmpType) {
1374 // Check that we have a comparison with a constant.
1375 ConstantSDNode *ConstCmpOp1 = dyn_cast<ConstantSDNode>(CmpOp1);
1378 uint64_t CmpVal = ConstCmpOp1->getZExtValue();
1380 // Check whether the nonconstant input is an AND with a constant mask.
1381 if (CmpOp0.getOpcode() != ISD::AND)
1383 SDValue AndOp0 = CmpOp0.getOperand(0);
1384 SDValue AndOp1 = CmpOp0.getOperand(1);
1385 ConstantSDNode *Mask = dyn_cast<ConstantSDNode>(AndOp1.getNode());
1388 uint64_t MaskVal = Mask->getZExtValue();
1390 // Check whether the combination of mask, comparison value and comparison
1391 // type are suitable.
1392 unsigned BitSize = CmpOp0.getValueType().getSizeInBits();
1393 unsigned NewCCMask, ShiftVal;
1394 if (ICmpType != SystemZICMP::SignedOnly &&
1395 AndOp0.getOpcode() == ISD::SHL &&
1396 isSimpleShift(AndOp0, ShiftVal) &&
1397 (NewCCMask = getTestUnderMaskCond(BitSize, CCMask, MaskVal >> ShiftVal,
1399 SystemZICMP::Any))) {
1400 AndOp0 = AndOp0.getOperand(0);
1401 AndOp1 = DAG.getConstant(MaskVal >> ShiftVal, AndOp0.getValueType());
1402 } else if (ICmpType != SystemZICMP::SignedOnly &&
1403 AndOp0.getOpcode() == ISD::SRL &&
1404 isSimpleShift(AndOp0, ShiftVal) &&
1405 (NewCCMask = getTestUnderMaskCond(BitSize, CCMask,
1406 MaskVal << ShiftVal,
1408 SystemZICMP::UnsignedOnly))) {
1409 AndOp0 = AndOp0.getOperand(0);
1410 AndOp1 = DAG.getConstant(MaskVal << ShiftVal, AndOp0.getValueType());
1412 NewCCMask = getTestUnderMaskCond(BitSize, CCMask, MaskVal, CmpVal,
1418 // Go ahead and make the change.
1419 Opcode = SystemZISD::TM;
1422 ICmpType = (bool(NewCCMask & SystemZ::CCMASK_TM_MIXED_MSB_0) !=
1423 bool(NewCCMask & SystemZ::CCMASK_TM_MIXED_MSB_1));
1424 CCValid = SystemZ::CCMASK_TM;
1428 // Return a target node that compares CmpOp0 with CmpOp1 and stores a
1429 // 2-bit result in CC. Set CCValid to the CCMASK_* of all possible
1430 // 2-bit results and CCMask to the subset of those results that are
1431 // associated with Cond.
1432 static SDValue emitCmp(const SystemZTargetMachine &TM, SelectionDAG &DAG,
1433 SDLoc DL, SDValue CmpOp0, SDValue CmpOp1,
1434 ISD::CondCode Cond, unsigned &CCValid,
1436 bool IsUnsigned = false;
1437 CCMask = CCMaskForCondCode(Cond);
1438 unsigned Opcode, ICmpType = 0;
1439 if (CmpOp0.getValueType().isFloatingPoint()) {
1440 CCValid = SystemZ::CCMASK_FCMP;
1441 Opcode = SystemZISD::FCMP;
1443 IsUnsigned = CCMask & SystemZ::CCMASK_CMP_UO;
1444 CCValid = SystemZ::CCMASK_ICMP;
1446 adjustZeroCmp(DAG, IsUnsigned, CmpOp0, CmpOp1, CCMask);
1447 adjustSubwordCmp(DAG, IsUnsigned, CmpOp0, CmpOp1, CCMask);
1448 Opcode = SystemZISD::ICMP;
1449 // Choose the type of comparison. Equality and inequality tests can
1450 // use either signed or unsigned comparisons. The choice also doesn't
1451 // matter if both sign bits are known to be clear. In those cases we
1452 // want to give the main isel code the freedom to choose whichever
1454 if (CCMask == SystemZ::CCMASK_CMP_EQ ||
1455 CCMask == SystemZ::CCMASK_CMP_NE ||
1456 (DAG.SignBitIsZero(CmpOp0) && DAG.SignBitIsZero(CmpOp1)))
1457 ICmpType = SystemZICMP::Any;
1458 else if (IsUnsigned)
1459 ICmpType = SystemZICMP::UnsignedOnly;
1461 ICmpType = SystemZICMP::SignedOnly;
1464 if (shouldSwapCmpOperands(CmpOp0, CmpOp1, ICmpType)) {
1465 std::swap(CmpOp0, CmpOp1);
1466 CCMask = ((CCMask & SystemZ::CCMASK_CMP_EQ) |
1467 (CCMask & SystemZ::CCMASK_CMP_GT ? SystemZ::CCMASK_CMP_LT : 0) |
1468 (CCMask & SystemZ::CCMASK_CMP_LT ? SystemZ::CCMASK_CMP_GT : 0) |
1469 (CCMask & SystemZ::CCMASK_CMP_UO));
1472 adjustForTestUnderMask(DAG, Opcode, CmpOp0, CmpOp1, CCValid, CCMask,
1474 if (Opcode == SystemZISD::ICMP || Opcode == SystemZISD::TM)
1475 return DAG.getNode(Opcode, DL, MVT::Glue, CmpOp0, CmpOp1,
1476 DAG.getConstant(ICmpType, MVT::i32));
1477 return DAG.getNode(Opcode, DL, MVT::Glue, CmpOp0, CmpOp1);
1480 // Implement a 32-bit *MUL_LOHI operation by extending both operands to
1481 // 64 bits. Extend is the extension type to use. Store the high part
1482 // in Hi and the low part in Lo.
1483 static void lowerMUL_LOHI32(SelectionDAG &DAG, SDLoc DL,
1484 unsigned Extend, SDValue Op0, SDValue Op1,
1485 SDValue &Hi, SDValue &Lo) {
1486 Op0 = DAG.getNode(Extend, DL, MVT::i64, Op0);
1487 Op1 = DAG.getNode(Extend, DL, MVT::i64, Op1);
1488 SDValue Mul = DAG.getNode(ISD::MUL, DL, MVT::i64, Op0, Op1);
1489 Hi = DAG.getNode(ISD::SRL, DL, MVT::i64, Mul, DAG.getConstant(32, MVT::i64));
1490 Hi = DAG.getNode(ISD::TRUNCATE, DL, MVT::i32, Hi);
1491 Lo = DAG.getNode(ISD::TRUNCATE, DL, MVT::i32, Mul);
1494 // Lower a binary operation that produces two VT results, one in each
1495 // half of a GR128 pair. Op0 and Op1 are the VT operands to the operation,
1496 // Extend extends Op0 to a GR128, and Opcode performs the GR128 operation
1497 // on the extended Op0 and (unextended) Op1. Store the even register result
1498 // in Even and the odd register result in Odd.
1499 static void lowerGR128Binary(SelectionDAG &DAG, SDLoc DL, EVT VT,
1500 unsigned Extend, unsigned Opcode,
1501 SDValue Op0, SDValue Op1,
1502 SDValue &Even, SDValue &Odd) {
1503 SDNode *In128 = DAG.getMachineNode(Extend, DL, MVT::Untyped, Op0);
1504 SDValue Result = DAG.getNode(Opcode, DL, MVT::Untyped,
1505 SDValue(In128, 0), Op1);
1506 bool Is32Bit = is32Bit(VT);
1507 Even = DAG.getTargetExtractSubreg(SystemZ::even128(Is32Bit), DL, VT, Result);
1508 Odd = DAG.getTargetExtractSubreg(SystemZ::odd128(Is32Bit), DL, VT, Result);
1511 // Return an i32 value that is 1 if the CC value produced by Glue is
1512 // in the mask CCMask and 0 otherwise. CC is known to have a value
1513 // in CCValid, so other values can be ignored.
1514 static SDValue emitSETCC(SelectionDAG &DAG, SDLoc DL, SDValue Glue,
1515 unsigned CCValid, unsigned CCMask) {
1516 IPMConversion Conversion = getIPMConversion(CCValid, CCMask);
1517 SDValue Result = DAG.getNode(SystemZISD::IPM, DL, MVT::i32, Glue);
1519 if (Conversion.XORValue)
1520 Result = DAG.getNode(ISD::XOR, DL, MVT::i32, Result,
1521 DAG.getConstant(Conversion.XORValue, MVT::i32));
1523 if (Conversion.AddValue)
1524 Result = DAG.getNode(ISD::ADD, DL, MVT::i32, Result,
1525 DAG.getConstant(Conversion.AddValue, MVT::i32));
1527 // The SHR/AND sequence should get optimized to an RISBG.
1528 Result = DAG.getNode(ISD::SRL, DL, MVT::i32, Result,
1529 DAG.getConstant(Conversion.Bit, MVT::i32));
1530 if (Conversion.Bit != 31)
1531 Result = DAG.getNode(ISD::AND, DL, MVT::i32, Result,
1532 DAG.getConstant(1, MVT::i32));
1536 SDValue SystemZTargetLowering::lowerSETCC(SDValue Op,
1537 SelectionDAG &DAG) const {
1538 SDValue CmpOp0 = Op.getOperand(0);
1539 SDValue CmpOp1 = Op.getOperand(1);
1540 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(2))->get();
1543 unsigned CCValid, CCMask;
1544 SDValue Glue = emitCmp(TM, DAG, DL, CmpOp0, CmpOp1, CC, CCValid, CCMask);
1545 return emitSETCC(DAG, DL, Glue, CCValid, CCMask);
1548 SDValue SystemZTargetLowering::lowerBR_CC(SDValue Op, SelectionDAG &DAG) const {
1549 SDValue Chain = Op.getOperand(0);
1550 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(1))->get();
1551 SDValue CmpOp0 = Op.getOperand(2);
1552 SDValue CmpOp1 = Op.getOperand(3);
1553 SDValue Dest = Op.getOperand(4);
1556 unsigned CCValid, CCMask;
1557 SDValue Glue = emitCmp(TM, DAG, DL, CmpOp0, CmpOp1, CC, CCValid, CCMask);
1558 return DAG.getNode(SystemZISD::BR_CCMASK, DL, Op.getValueType(),
1559 Chain, DAG.getConstant(CCValid, MVT::i32),
1560 DAG.getConstant(CCMask, MVT::i32), Dest, Glue);
1563 SDValue SystemZTargetLowering::lowerSELECT_CC(SDValue Op,
1564 SelectionDAG &DAG) const {
1565 SDValue CmpOp0 = Op.getOperand(0);
1566 SDValue CmpOp1 = Op.getOperand(1);
1567 SDValue TrueOp = Op.getOperand(2);
1568 SDValue FalseOp = Op.getOperand(3);
1569 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(4))->get();
1572 unsigned CCValid, CCMask;
1573 SDValue Glue = emitCmp(TM, DAG, DL, CmpOp0, CmpOp1, CC, CCValid, CCMask);
1575 // Special case for handling -1/0 results. The shifts we use here
1576 // should get optimized with the IPM conversion sequence.
1577 ConstantSDNode *TrueC = dyn_cast<ConstantSDNode>(TrueOp);
1578 ConstantSDNode *FalseC = dyn_cast<ConstantSDNode>(FalseOp);
1579 if (TrueC && FalseC) {
1580 int64_t TrueVal = TrueC->getSExtValue();
1581 int64_t FalseVal = FalseC->getSExtValue();
1582 if ((TrueVal == -1 && FalseVal == 0) || (TrueVal == 0 && FalseVal == -1)) {
1583 // Invert the condition if we want -1 on false.
1586 SDValue Result = emitSETCC(DAG, DL, Glue, CCValid, CCMask);
1587 EVT VT = Op.getValueType();
1588 // Extend the result to VT. Upper bits are ignored.
1590 Result = DAG.getNode(ISD::ANY_EXTEND, DL, VT, Result);
1591 // Sign-extend from the low bit.
1592 SDValue ShAmt = DAG.getConstant(VT.getSizeInBits() - 1, MVT::i32);
1593 SDValue Shl = DAG.getNode(ISD::SHL, DL, VT, Result, ShAmt);
1594 return DAG.getNode(ISD::SRA, DL, VT, Shl, ShAmt);
1598 SmallVector<SDValue, 5> Ops;
1599 Ops.push_back(TrueOp);
1600 Ops.push_back(FalseOp);
1601 Ops.push_back(DAG.getConstant(CCValid, MVT::i32));
1602 Ops.push_back(DAG.getConstant(CCMask, MVT::i32));
1603 Ops.push_back(Glue);
1605 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::Glue);
1606 return DAG.getNode(SystemZISD::SELECT_CCMASK, DL, VTs, &Ops[0], Ops.size());
1609 SDValue SystemZTargetLowering::lowerGlobalAddress(GlobalAddressSDNode *Node,
1610 SelectionDAG &DAG) const {
1612 const GlobalValue *GV = Node->getGlobal();
1613 int64_t Offset = Node->getOffset();
1614 EVT PtrVT = getPointerTy();
1615 Reloc::Model RM = TM.getRelocationModel();
1616 CodeModel::Model CM = TM.getCodeModel();
1619 if (Subtarget.isPC32DBLSymbol(GV, RM, CM)) {
1620 // Assign anchors at 1<<12 byte boundaries.
1621 uint64_t Anchor = Offset & ~uint64_t(0xfff);
1622 Result = DAG.getTargetGlobalAddress(GV, DL, PtrVT, Anchor);
1623 Result = DAG.getNode(SystemZISD::PCREL_WRAPPER, DL, PtrVT, Result);
1625 // The offset can be folded into the address if it is aligned to a halfword.
1627 if (Offset != 0 && (Offset & 1) == 0) {
1628 SDValue Full = DAG.getTargetGlobalAddress(GV, DL, PtrVT, Anchor + Offset);
1629 Result = DAG.getNode(SystemZISD::PCREL_OFFSET, DL, PtrVT, Full, Result);
1633 Result = DAG.getTargetGlobalAddress(GV, DL, PtrVT, 0, SystemZII::MO_GOT);
1634 Result = DAG.getNode(SystemZISD::PCREL_WRAPPER, DL, PtrVT, Result);
1635 Result = DAG.getLoad(PtrVT, DL, DAG.getEntryNode(), Result,
1636 MachinePointerInfo::getGOT(), false, false, false, 0);
1639 // If there was a non-zero offset that we didn't fold, create an explicit
1642 Result = DAG.getNode(ISD::ADD, DL, PtrVT, Result,
1643 DAG.getConstant(Offset, PtrVT));
1648 SDValue SystemZTargetLowering::lowerGlobalTLSAddress(GlobalAddressSDNode *Node,
1649 SelectionDAG &DAG) const {
1651 const GlobalValue *GV = Node->getGlobal();
1652 EVT PtrVT = getPointerTy();
1653 TLSModel::Model model = TM.getTLSModel(GV);
1655 if (model != TLSModel::LocalExec)
1656 llvm_unreachable("only local-exec TLS mode supported");
1658 // The high part of the thread pointer is in access register 0.
1659 SDValue TPHi = DAG.getNode(SystemZISD::EXTRACT_ACCESS, DL, MVT::i32,
1660 DAG.getConstant(0, MVT::i32));
1661 TPHi = DAG.getNode(ISD::ANY_EXTEND, DL, PtrVT, TPHi);
1663 // The low part of the thread pointer is in access register 1.
1664 SDValue TPLo = DAG.getNode(SystemZISD::EXTRACT_ACCESS, DL, MVT::i32,
1665 DAG.getConstant(1, MVT::i32));
1666 TPLo = DAG.getNode(ISD::ZERO_EXTEND, DL, PtrVT, TPLo);
1668 // Merge them into a single 64-bit address.
1669 SDValue TPHiShifted = DAG.getNode(ISD::SHL, DL, PtrVT, TPHi,
1670 DAG.getConstant(32, PtrVT));
1671 SDValue TP = DAG.getNode(ISD::OR, DL, PtrVT, TPHiShifted, TPLo);
1673 // Get the offset of GA from the thread pointer.
1674 SystemZConstantPoolValue *CPV =
1675 SystemZConstantPoolValue::Create(GV, SystemZCP::NTPOFF);
1677 // Force the offset into the constant pool and load it from there.
1678 SDValue CPAddr = DAG.getConstantPool(CPV, PtrVT, 8);
1679 SDValue Offset = DAG.getLoad(PtrVT, DL, DAG.getEntryNode(),
1680 CPAddr, MachinePointerInfo::getConstantPool(),
1681 false, false, false, 0);
1683 // Add the base and offset together.
1684 return DAG.getNode(ISD::ADD, DL, PtrVT, TP, Offset);
1687 SDValue SystemZTargetLowering::lowerBlockAddress(BlockAddressSDNode *Node,
1688 SelectionDAG &DAG) const {
1690 const BlockAddress *BA = Node->getBlockAddress();
1691 int64_t Offset = Node->getOffset();
1692 EVT PtrVT = getPointerTy();
1694 SDValue Result = DAG.getTargetBlockAddress(BA, PtrVT, Offset);
1695 Result = DAG.getNode(SystemZISD::PCREL_WRAPPER, DL, PtrVT, Result);
1699 SDValue SystemZTargetLowering::lowerJumpTable(JumpTableSDNode *JT,
1700 SelectionDAG &DAG) const {
1702 EVT PtrVT = getPointerTy();
1703 SDValue Result = DAG.getTargetJumpTable(JT->getIndex(), PtrVT);
1705 // Use LARL to load the address of the table.
1706 return DAG.getNode(SystemZISD::PCREL_WRAPPER, DL, PtrVT, Result);
1709 SDValue SystemZTargetLowering::lowerConstantPool(ConstantPoolSDNode *CP,
1710 SelectionDAG &DAG) const {
1712 EVT PtrVT = getPointerTy();
1715 if (CP->isMachineConstantPoolEntry())
1716 Result = DAG.getTargetConstantPool(CP->getMachineCPVal(), PtrVT,
1717 CP->getAlignment());
1719 Result = DAG.getTargetConstantPool(CP->getConstVal(), PtrVT,
1720 CP->getAlignment(), CP->getOffset());
1722 // Use LARL to load the address of the constant pool entry.
1723 return DAG.getNode(SystemZISD::PCREL_WRAPPER, DL, PtrVT, Result);
1726 SDValue SystemZTargetLowering::lowerBITCAST(SDValue Op,
1727 SelectionDAG &DAG) const {
1729 SDValue In = Op.getOperand(0);
1730 EVT InVT = In.getValueType();
1731 EVT ResVT = Op.getValueType();
1733 if (InVT == MVT::i32 && ResVT == MVT::f32) {
1735 if (Subtarget.hasHighWord()) {
1736 SDNode *U64 = DAG.getMachineNode(TargetOpcode::IMPLICIT_DEF, DL,
1738 In64 = DAG.getTargetInsertSubreg(SystemZ::subreg_h32, DL,
1739 MVT::i64, SDValue(U64, 0), In);
1741 In64 = DAG.getNode(ISD::ANY_EXTEND, DL, MVT::i64, In);
1742 In64 = DAG.getNode(ISD::SHL, DL, MVT::i64, In64,
1743 DAG.getConstant(32, MVT::i64));
1745 SDValue Out64 = DAG.getNode(ISD::BITCAST, DL, MVT::f64, In64);
1746 return DAG.getTargetExtractSubreg(SystemZ::subreg_h32,
1747 DL, MVT::f32, Out64);
1749 if (InVT == MVT::f32 && ResVT == MVT::i32) {
1750 SDNode *U64 = DAG.getMachineNode(TargetOpcode::IMPLICIT_DEF, DL, MVT::f64);
1751 SDValue In64 = DAG.getTargetInsertSubreg(SystemZ::subreg_h32, DL,
1752 MVT::f64, SDValue(U64, 0), In);
1753 SDValue Out64 = DAG.getNode(ISD::BITCAST, DL, MVT::i64, In64);
1754 if (Subtarget.hasHighWord())
1755 return DAG.getTargetExtractSubreg(SystemZ::subreg_h32, DL,
1757 SDValue Shift = DAG.getNode(ISD::SRL, DL, MVT::i64, Out64,
1758 DAG.getConstant(32, MVT::i64));
1759 return DAG.getNode(ISD::TRUNCATE, DL, MVT::i32, Shift);
1761 llvm_unreachable("Unexpected bitcast combination");
1764 SDValue SystemZTargetLowering::lowerVASTART(SDValue Op,
1765 SelectionDAG &DAG) const {
1766 MachineFunction &MF = DAG.getMachineFunction();
1767 SystemZMachineFunctionInfo *FuncInfo =
1768 MF.getInfo<SystemZMachineFunctionInfo>();
1769 EVT PtrVT = getPointerTy();
1771 SDValue Chain = Op.getOperand(0);
1772 SDValue Addr = Op.getOperand(1);
1773 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
1776 // The initial values of each field.
1777 const unsigned NumFields = 4;
1778 SDValue Fields[NumFields] = {
1779 DAG.getConstant(FuncInfo->getVarArgsFirstGPR(), PtrVT),
1780 DAG.getConstant(FuncInfo->getVarArgsFirstFPR(), PtrVT),
1781 DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(), PtrVT),
1782 DAG.getFrameIndex(FuncInfo->getRegSaveFrameIndex(), PtrVT)
1785 // Store each field into its respective slot.
1786 SDValue MemOps[NumFields];
1787 unsigned Offset = 0;
1788 for (unsigned I = 0; I < NumFields; ++I) {
1789 SDValue FieldAddr = Addr;
1791 FieldAddr = DAG.getNode(ISD::ADD, DL, PtrVT, FieldAddr,
1792 DAG.getIntPtrConstant(Offset));
1793 MemOps[I] = DAG.getStore(Chain, DL, Fields[I], FieldAddr,
1794 MachinePointerInfo(SV, Offset),
1798 return DAG.getNode(ISD::TokenFactor, DL, MVT::Other, MemOps, NumFields);
1801 SDValue SystemZTargetLowering::lowerVACOPY(SDValue Op,
1802 SelectionDAG &DAG) const {
1803 SDValue Chain = Op.getOperand(0);
1804 SDValue DstPtr = Op.getOperand(1);
1805 SDValue SrcPtr = Op.getOperand(2);
1806 const Value *DstSV = cast<SrcValueSDNode>(Op.getOperand(3))->getValue();
1807 const Value *SrcSV = cast<SrcValueSDNode>(Op.getOperand(4))->getValue();
1810 return DAG.getMemcpy(Chain, DL, DstPtr, SrcPtr, DAG.getIntPtrConstant(32),
1811 /*Align*/8, /*isVolatile*/false, /*AlwaysInline*/false,
1812 MachinePointerInfo(DstSV), MachinePointerInfo(SrcSV));
1815 SDValue SystemZTargetLowering::
1816 lowerDYNAMIC_STACKALLOC(SDValue Op, SelectionDAG &DAG) const {
1817 SDValue Chain = Op.getOperand(0);
1818 SDValue Size = Op.getOperand(1);
1821 unsigned SPReg = getStackPointerRegisterToSaveRestore();
1823 // Get a reference to the stack pointer.
1824 SDValue OldSP = DAG.getCopyFromReg(Chain, DL, SPReg, MVT::i64);
1826 // Get the new stack pointer value.
1827 SDValue NewSP = DAG.getNode(ISD::SUB, DL, MVT::i64, OldSP, Size);
1829 // Copy the new stack pointer back.
1830 Chain = DAG.getCopyToReg(Chain, DL, SPReg, NewSP);
1832 // The allocated data lives above the 160 bytes allocated for the standard
1833 // frame, plus any outgoing stack arguments. We don't know how much that
1834 // amounts to yet, so emit a special ADJDYNALLOC placeholder.
1835 SDValue ArgAdjust = DAG.getNode(SystemZISD::ADJDYNALLOC, DL, MVT::i64);
1836 SDValue Result = DAG.getNode(ISD::ADD, DL, MVT::i64, NewSP, ArgAdjust);
1838 SDValue Ops[2] = { Result, Chain };
1839 return DAG.getMergeValues(Ops, 2, DL);
1842 SDValue SystemZTargetLowering::lowerSMUL_LOHI(SDValue Op,
1843 SelectionDAG &DAG) const {
1844 EVT VT = Op.getValueType();
1848 // Just do a normal 64-bit multiplication and extract the results.
1849 // We define this so that it can be used for constant division.
1850 lowerMUL_LOHI32(DAG, DL, ISD::SIGN_EXTEND, Op.getOperand(0),
1851 Op.getOperand(1), Ops[1], Ops[0]);
1853 // Do a full 128-bit multiplication based on UMUL_LOHI64:
1855 // (ll * rl) + ((lh * rl) << 64) + ((ll * rh) << 64)
1857 // but using the fact that the upper halves are either all zeros
1860 // (ll * rl) - ((lh & rl) << 64) - ((ll & rh) << 64)
1862 // and grouping the right terms together since they are quicker than the
1865 // (ll * rl) - (((lh & rl) + (ll & rh)) << 64)
1866 SDValue C63 = DAG.getConstant(63, MVT::i64);
1867 SDValue LL = Op.getOperand(0);
1868 SDValue RL = Op.getOperand(1);
1869 SDValue LH = DAG.getNode(ISD::SRA, DL, VT, LL, C63);
1870 SDValue RH = DAG.getNode(ISD::SRA, DL, VT, RL, C63);
1871 // UMUL_LOHI64 returns the low result in the odd register and the high
1872 // result in the even register. SMUL_LOHI is defined to return the
1873 // low half first, so the results are in reverse order.
1874 lowerGR128Binary(DAG, DL, VT, SystemZ::AEXT128_64, SystemZISD::UMUL_LOHI64,
1875 LL, RL, Ops[1], Ops[0]);
1876 SDValue NegLLTimesRH = DAG.getNode(ISD::AND, DL, VT, LL, RH);
1877 SDValue NegLHTimesRL = DAG.getNode(ISD::AND, DL, VT, LH, RL);
1878 SDValue NegSum = DAG.getNode(ISD::ADD, DL, VT, NegLLTimesRH, NegLHTimesRL);
1879 Ops[1] = DAG.getNode(ISD::SUB, DL, VT, Ops[1], NegSum);
1881 return DAG.getMergeValues(Ops, 2, DL);
1884 SDValue SystemZTargetLowering::lowerUMUL_LOHI(SDValue Op,
1885 SelectionDAG &DAG) const {
1886 EVT VT = Op.getValueType();
1890 // Just do a normal 64-bit multiplication and extract the results.
1891 // We define this so that it can be used for constant division.
1892 lowerMUL_LOHI32(DAG, DL, ISD::ZERO_EXTEND, Op.getOperand(0),
1893 Op.getOperand(1), Ops[1], Ops[0]);
1895 // UMUL_LOHI64 returns the low result in the odd register and the high
1896 // result in the even register. UMUL_LOHI is defined to return the
1897 // low half first, so the results are in reverse order.
1898 lowerGR128Binary(DAG, DL, VT, SystemZ::AEXT128_64, SystemZISD::UMUL_LOHI64,
1899 Op.getOperand(0), Op.getOperand(1), Ops[1], Ops[0]);
1900 return DAG.getMergeValues(Ops, 2, DL);
1903 SDValue SystemZTargetLowering::lowerSDIVREM(SDValue Op,
1904 SelectionDAG &DAG) const {
1905 SDValue Op0 = Op.getOperand(0);
1906 SDValue Op1 = Op.getOperand(1);
1907 EVT VT = Op.getValueType();
1911 // We use DSGF for 32-bit division.
1913 Op0 = DAG.getNode(ISD::SIGN_EXTEND, DL, MVT::i64, Op0);
1914 Opcode = SystemZISD::SDIVREM32;
1915 } else if (DAG.ComputeNumSignBits(Op1) > 32) {
1916 Op1 = DAG.getNode(ISD::TRUNCATE, DL, MVT::i32, Op1);
1917 Opcode = SystemZISD::SDIVREM32;
1919 Opcode = SystemZISD::SDIVREM64;
1921 // DSG(F) takes a 64-bit dividend, so the even register in the GR128
1922 // input is "don't care". The instruction returns the remainder in
1923 // the even register and the quotient in the odd register.
1925 lowerGR128Binary(DAG, DL, VT, SystemZ::AEXT128_64, Opcode,
1926 Op0, Op1, Ops[1], Ops[0]);
1927 return DAG.getMergeValues(Ops, 2, DL);
1930 SDValue SystemZTargetLowering::lowerUDIVREM(SDValue Op,
1931 SelectionDAG &DAG) const {
1932 EVT VT = Op.getValueType();
1935 // DL(G) uses a double-width dividend, so we need to clear the even
1936 // register in the GR128 input. The instruction returns the remainder
1937 // in the even register and the quotient in the odd register.
1940 lowerGR128Binary(DAG, DL, VT, SystemZ::ZEXT128_32, SystemZISD::UDIVREM32,
1941 Op.getOperand(0), Op.getOperand(1), Ops[1], Ops[0]);
1943 lowerGR128Binary(DAG, DL, VT, SystemZ::ZEXT128_64, SystemZISD::UDIVREM64,
1944 Op.getOperand(0), Op.getOperand(1), Ops[1], Ops[0]);
1945 return DAG.getMergeValues(Ops, 2, DL);
1948 SDValue SystemZTargetLowering::lowerOR(SDValue Op, SelectionDAG &DAG) const {
1949 assert(Op.getValueType() == MVT::i64 && "Should be 64-bit operation");
1951 // Get the known-zero masks for each operand.
1952 SDValue Ops[] = { Op.getOperand(0), Op.getOperand(1) };
1953 APInt KnownZero[2], KnownOne[2];
1954 DAG.ComputeMaskedBits(Ops[0], KnownZero[0], KnownOne[0]);
1955 DAG.ComputeMaskedBits(Ops[1], KnownZero[1], KnownOne[1]);
1957 // See if the upper 32 bits of one operand and the lower 32 bits of the
1958 // other are known zero. They are the low and high operands respectively.
1959 uint64_t Masks[] = { KnownZero[0].getZExtValue(),
1960 KnownZero[1].getZExtValue() };
1962 if ((Masks[0] >> 32) == 0xffffffff && uint32_t(Masks[1]) == 0xffffffff)
1964 else if ((Masks[1] >> 32) == 0xffffffff && uint32_t(Masks[0]) == 0xffffffff)
1969 SDValue LowOp = Ops[Low];
1970 SDValue HighOp = Ops[High];
1972 // If the high part is a constant, we're better off using IILH.
1973 if (HighOp.getOpcode() == ISD::Constant)
1976 // If the low part is a constant that is outside the range of LHI,
1977 // then we're better off using IILF.
1978 if (LowOp.getOpcode() == ISD::Constant) {
1979 int64_t Value = int32_t(cast<ConstantSDNode>(LowOp)->getZExtValue());
1980 if (!isInt<16>(Value))
1984 // Check whether the high part is an AND that doesn't change the
1985 // high 32 bits and just masks out low bits. We can skip it if so.
1986 if (HighOp.getOpcode() == ISD::AND &&
1987 HighOp.getOperand(1).getOpcode() == ISD::Constant) {
1988 SDValue HighOp0 = HighOp.getOperand(0);
1989 uint64_t Mask = cast<ConstantSDNode>(HighOp.getOperand(1))->getZExtValue();
1990 if (DAG.MaskedValueIsZero(HighOp0, APInt(64, ~(Mask | 0xffffffff))))
1994 // Take advantage of the fact that all GR32 operations only change the
1995 // low 32 bits by truncating Low to an i32 and inserting it directly
1996 // using a subreg. The interesting cases are those where the truncation
1999 SDValue Low32 = DAG.getNode(ISD::TRUNCATE, DL, MVT::i32, LowOp);
2000 return DAG.getTargetInsertSubreg(SystemZ::subreg_l32, DL,
2001 MVT::i64, HighOp, Low32);
2004 // Op is an atomic load. Lower it into a normal volatile load.
2005 SDValue SystemZTargetLowering::lowerATOMIC_LOAD(SDValue Op,
2006 SelectionDAG &DAG) const {
2007 AtomicSDNode *Node = cast<AtomicSDNode>(Op.getNode());
2008 return DAG.getExtLoad(ISD::EXTLOAD, SDLoc(Op), Op.getValueType(),
2009 Node->getChain(), Node->getBasePtr(),
2010 Node->getMemoryVT(), Node->getMemOperand());
2013 // Op is an atomic store. Lower it into a normal volatile store followed
2014 // by a serialization.
2015 SDValue SystemZTargetLowering::lowerATOMIC_STORE(SDValue Op,
2016 SelectionDAG &DAG) const {
2017 AtomicSDNode *Node = cast<AtomicSDNode>(Op.getNode());
2018 SDValue Chain = DAG.getTruncStore(Node->getChain(), SDLoc(Op), Node->getVal(),
2019 Node->getBasePtr(), Node->getMemoryVT(),
2020 Node->getMemOperand());
2021 return SDValue(DAG.getMachineNode(SystemZ::Serialize, SDLoc(Op), MVT::Other,
2025 // Op is an 8-, 16-bit or 32-bit ATOMIC_LOAD_* operation. Lower the first
2026 // two into the fullword ATOMIC_LOADW_* operation given by Opcode.
2027 SDValue SystemZTargetLowering::lowerATOMIC_LOAD_OP(SDValue Op,
2029 unsigned Opcode) const {
2030 AtomicSDNode *Node = cast<AtomicSDNode>(Op.getNode());
2032 // 32-bit operations need no code outside the main loop.
2033 EVT NarrowVT = Node->getMemoryVT();
2034 EVT WideVT = MVT::i32;
2035 if (NarrowVT == WideVT)
2038 int64_t BitSize = NarrowVT.getSizeInBits();
2039 SDValue ChainIn = Node->getChain();
2040 SDValue Addr = Node->getBasePtr();
2041 SDValue Src2 = Node->getVal();
2042 MachineMemOperand *MMO = Node->getMemOperand();
2044 EVT PtrVT = Addr.getValueType();
2046 // Convert atomic subtracts of constants into additions.
2047 if (Opcode == SystemZISD::ATOMIC_LOADW_SUB)
2048 if (ConstantSDNode *Const = dyn_cast<ConstantSDNode>(Src2)) {
2049 Opcode = SystemZISD::ATOMIC_LOADW_ADD;
2050 Src2 = DAG.getConstant(-Const->getSExtValue(), Src2.getValueType());
2053 // Get the address of the containing word.
2054 SDValue AlignedAddr = DAG.getNode(ISD::AND, DL, PtrVT, Addr,
2055 DAG.getConstant(-4, PtrVT));
2057 // Get the number of bits that the word must be rotated left in order
2058 // to bring the field to the top bits of a GR32.
2059 SDValue BitShift = DAG.getNode(ISD::SHL, DL, PtrVT, Addr,
2060 DAG.getConstant(3, PtrVT));
2061 BitShift = DAG.getNode(ISD::TRUNCATE, DL, WideVT, BitShift);
2063 // Get the complementing shift amount, for rotating a field in the top
2064 // bits back to its proper position.
2065 SDValue NegBitShift = DAG.getNode(ISD::SUB, DL, WideVT,
2066 DAG.getConstant(0, WideVT), BitShift);
2068 // Extend the source operand to 32 bits and prepare it for the inner loop.
2069 // ATOMIC_SWAPW uses RISBG to rotate the field left, but all other
2070 // operations require the source to be shifted in advance. (This shift
2071 // can be folded if the source is constant.) For AND and NAND, the lower
2072 // bits must be set, while for other opcodes they should be left clear.
2073 if (Opcode != SystemZISD::ATOMIC_SWAPW)
2074 Src2 = DAG.getNode(ISD::SHL, DL, WideVT, Src2,
2075 DAG.getConstant(32 - BitSize, WideVT));
2076 if (Opcode == SystemZISD::ATOMIC_LOADW_AND ||
2077 Opcode == SystemZISD::ATOMIC_LOADW_NAND)
2078 Src2 = DAG.getNode(ISD::OR, DL, WideVT, Src2,
2079 DAG.getConstant(uint32_t(-1) >> BitSize, WideVT));
2081 // Construct the ATOMIC_LOADW_* node.
2082 SDVTList VTList = DAG.getVTList(WideVT, MVT::Other);
2083 SDValue Ops[] = { ChainIn, AlignedAddr, Src2, BitShift, NegBitShift,
2084 DAG.getConstant(BitSize, WideVT) };
2085 SDValue AtomicOp = DAG.getMemIntrinsicNode(Opcode, DL, VTList, Ops,
2086 array_lengthof(Ops),
2089 // Rotate the result of the final CS so that the field is in the lower
2090 // bits of a GR32, then truncate it.
2091 SDValue ResultShift = DAG.getNode(ISD::ADD, DL, WideVT, BitShift,
2092 DAG.getConstant(BitSize, WideVT));
2093 SDValue Result = DAG.getNode(ISD::ROTL, DL, WideVT, AtomicOp, ResultShift);
2095 SDValue RetOps[2] = { Result, AtomicOp.getValue(1) };
2096 return DAG.getMergeValues(RetOps, 2, DL);
2099 // Node is an 8- or 16-bit ATOMIC_CMP_SWAP operation. Lower the first two
2100 // into a fullword ATOMIC_CMP_SWAPW operation.
2101 SDValue SystemZTargetLowering::lowerATOMIC_CMP_SWAP(SDValue Op,
2102 SelectionDAG &DAG) const {
2103 AtomicSDNode *Node = cast<AtomicSDNode>(Op.getNode());
2105 // We have native support for 32-bit compare and swap.
2106 EVT NarrowVT = Node->getMemoryVT();
2107 EVT WideVT = MVT::i32;
2108 if (NarrowVT == WideVT)
2111 int64_t BitSize = NarrowVT.getSizeInBits();
2112 SDValue ChainIn = Node->getOperand(0);
2113 SDValue Addr = Node->getOperand(1);
2114 SDValue CmpVal = Node->getOperand(2);
2115 SDValue SwapVal = Node->getOperand(3);
2116 MachineMemOperand *MMO = Node->getMemOperand();
2118 EVT PtrVT = Addr.getValueType();
2120 // Get the address of the containing word.
2121 SDValue AlignedAddr = DAG.getNode(ISD::AND, DL, PtrVT, Addr,
2122 DAG.getConstant(-4, PtrVT));
2124 // Get the number of bits that the word must be rotated left in order
2125 // to bring the field to the top bits of a GR32.
2126 SDValue BitShift = DAG.getNode(ISD::SHL, DL, PtrVT, Addr,
2127 DAG.getConstant(3, PtrVT));
2128 BitShift = DAG.getNode(ISD::TRUNCATE, DL, WideVT, BitShift);
2130 // Get the complementing shift amount, for rotating a field in the top
2131 // bits back to its proper position.
2132 SDValue NegBitShift = DAG.getNode(ISD::SUB, DL, WideVT,
2133 DAG.getConstant(0, WideVT), BitShift);
2135 // Construct the ATOMIC_CMP_SWAPW node.
2136 SDVTList VTList = DAG.getVTList(WideVT, MVT::Other);
2137 SDValue Ops[] = { ChainIn, AlignedAddr, CmpVal, SwapVal, BitShift,
2138 NegBitShift, DAG.getConstant(BitSize, WideVT) };
2139 SDValue AtomicOp = DAG.getMemIntrinsicNode(SystemZISD::ATOMIC_CMP_SWAPW, DL,
2140 VTList, Ops, array_lengthof(Ops),
2145 SDValue SystemZTargetLowering::lowerSTACKSAVE(SDValue Op,
2146 SelectionDAG &DAG) const {
2147 MachineFunction &MF = DAG.getMachineFunction();
2148 MF.getInfo<SystemZMachineFunctionInfo>()->setManipulatesSP(true);
2149 return DAG.getCopyFromReg(Op.getOperand(0), SDLoc(Op),
2150 SystemZ::R15D, Op.getValueType());
2153 SDValue SystemZTargetLowering::lowerSTACKRESTORE(SDValue Op,
2154 SelectionDAG &DAG) const {
2155 MachineFunction &MF = DAG.getMachineFunction();
2156 MF.getInfo<SystemZMachineFunctionInfo>()->setManipulatesSP(true);
2157 return DAG.getCopyToReg(Op.getOperand(0), SDLoc(Op),
2158 SystemZ::R15D, Op.getOperand(1));
2161 SDValue SystemZTargetLowering::lowerPREFETCH(SDValue Op,
2162 SelectionDAG &DAG) const {
2163 bool IsData = cast<ConstantSDNode>(Op.getOperand(4))->getZExtValue();
2165 // Just preserve the chain.
2166 return Op.getOperand(0);
2168 bool IsWrite = cast<ConstantSDNode>(Op.getOperand(2))->getZExtValue();
2169 unsigned Code = IsWrite ? SystemZ::PFD_WRITE : SystemZ::PFD_READ;
2170 MemIntrinsicSDNode *Node = cast<MemIntrinsicSDNode>(Op.getNode());
2173 DAG.getConstant(Code, MVT::i32),
2176 return DAG.getMemIntrinsicNode(SystemZISD::PREFETCH, SDLoc(Op),
2177 Node->getVTList(), Ops, array_lengthof(Ops),
2178 Node->getMemoryVT(), Node->getMemOperand());
2181 SDValue SystemZTargetLowering::LowerOperation(SDValue Op,
2182 SelectionDAG &DAG) const {
2183 switch (Op.getOpcode()) {
2185 return lowerBR_CC(Op, DAG);
2186 case ISD::SELECT_CC:
2187 return lowerSELECT_CC(Op, DAG);
2189 return lowerSETCC(Op, DAG);
2190 case ISD::GlobalAddress:
2191 return lowerGlobalAddress(cast<GlobalAddressSDNode>(Op), DAG);
2192 case ISD::GlobalTLSAddress:
2193 return lowerGlobalTLSAddress(cast<GlobalAddressSDNode>(Op), DAG);
2194 case ISD::BlockAddress:
2195 return lowerBlockAddress(cast<BlockAddressSDNode>(Op), DAG);
2196 case ISD::JumpTable:
2197 return lowerJumpTable(cast<JumpTableSDNode>(Op), DAG);
2198 case ISD::ConstantPool:
2199 return lowerConstantPool(cast<ConstantPoolSDNode>(Op), DAG);
2201 return lowerBITCAST(Op, DAG);
2203 return lowerVASTART(Op, DAG);
2205 return lowerVACOPY(Op, DAG);
2206 case ISD::DYNAMIC_STACKALLOC:
2207 return lowerDYNAMIC_STACKALLOC(Op, DAG);
2208 case ISD::SMUL_LOHI:
2209 return lowerSMUL_LOHI(Op, DAG);
2210 case ISD::UMUL_LOHI:
2211 return lowerUMUL_LOHI(Op, DAG);
2213 return lowerSDIVREM(Op, DAG);
2215 return lowerUDIVREM(Op, DAG);
2217 return lowerOR(Op, DAG);
2218 case ISD::ATOMIC_SWAP:
2219 return lowerATOMIC_LOAD_OP(Op, DAG, SystemZISD::ATOMIC_SWAPW);
2220 case ISD::ATOMIC_STORE:
2221 return lowerATOMIC_STORE(Op, DAG);
2222 case ISD::ATOMIC_LOAD:
2223 return lowerATOMIC_LOAD(Op, DAG);
2224 case ISD::ATOMIC_LOAD_ADD:
2225 return lowerATOMIC_LOAD_OP(Op, DAG, SystemZISD::ATOMIC_LOADW_ADD);
2226 case ISD::ATOMIC_LOAD_SUB:
2227 return lowerATOMIC_LOAD_OP(Op, DAG, SystemZISD::ATOMIC_LOADW_SUB);
2228 case ISD::ATOMIC_LOAD_AND:
2229 return lowerATOMIC_LOAD_OP(Op, DAG, SystemZISD::ATOMIC_LOADW_AND);
2230 case ISD::ATOMIC_LOAD_OR:
2231 return lowerATOMIC_LOAD_OP(Op, DAG, SystemZISD::ATOMIC_LOADW_OR);
2232 case ISD::ATOMIC_LOAD_XOR:
2233 return lowerATOMIC_LOAD_OP(Op, DAG, SystemZISD::ATOMIC_LOADW_XOR);
2234 case ISD::ATOMIC_LOAD_NAND:
2235 return lowerATOMIC_LOAD_OP(Op, DAG, SystemZISD::ATOMIC_LOADW_NAND);
2236 case ISD::ATOMIC_LOAD_MIN:
2237 return lowerATOMIC_LOAD_OP(Op, DAG, SystemZISD::ATOMIC_LOADW_MIN);
2238 case ISD::ATOMIC_LOAD_MAX:
2239 return lowerATOMIC_LOAD_OP(Op, DAG, SystemZISD::ATOMIC_LOADW_MAX);
2240 case ISD::ATOMIC_LOAD_UMIN:
2241 return lowerATOMIC_LOAD_OP(Op, DAG, SystemZISD::ATOMIC_LOADW_UMIN);
2242 case ISD::ATOMIC_LOAD_UMAX:
2243 return lowerATOMIC_LOAD_OP(Op, DAG, SystemZISD::ATOMIC_LOADW_UMAX);
2244 case ISD::ATOMIC_CMP_SWAP:
2245 return lowerATOMIC_CMP_SWAP(Op, DAG);
2246 case ISD::STACKSAVE:
2247 return lowerSTACKSAVE(Op, DAG);
2248 case ISD::STACKRESTORE:
2249 return lowerSTACKRESTORE(Op, DAG);
2251 return lowerPREFETCH(Op, DAG);
2253 llvm_unreachable("Unexpected node to lower");
2257 const char *SystemZTargetLowering::getTargetNodeName(unsigned Opcode) const {
2258 #define OPCODE(NAME) case SystemZISD::NAME: return "SystemZISD::" #NAME
2263 OPCODE(PCREL_WRAPPER);
2264 OPCODE(PCREL_OFFSET);
2269 OPCODE(SELECT_CCMASK);
2270 OPCODE(ADJDYNALLOC);
2271 OPCODE(EXTRACT_ACCESS);
2272 OPCODE(UMUL_LOHI64);
2288 OPCODE(SEARCH_STRING);
2291 OPCODE(ATOMIC_SWAPW);
2292 OPCODE(ATOMIC_LOADW_ADD);
2293 OPCODE(ATOMIC_LOADW_SUB);
2294 OPCODE(ATOMIC_LOADW_AND);
2295 OPCODE(ATOMIC_LOADW_OR);
2296 OPCODE(ATOMIC_LOADW_XOR);
2297 OPCODE(ATOMIC_LOADW_NAND);
2298 OPCODE(ATOMIC_LOADW_MIN);
2299 OPCODE(ATOMIC_LOADW_MAX);
2300 OPCODE(ATOMIC_LOADW_UMIN);
2301 OPCODE(ATOMIC_LOADW_UMAX);
2302 OPCODE(ATOMIC_CMP_SWAPW);
2309 //===----------------------------------------------------------------------===//
2311 //===----------------------------------------------------------------------===//
2313 // Create a new basic block after MBB.
2314 static MachineBasicBlock *emitBlockAfter(MachineBasicBlock *MBB) {
2315 MachineFunction &MF = *MBB->getParent();
2316 MachineBasicBlock *NewMBB = MF.CreateMachineBasicBlock(MBB->getBasicBlock());
2317 MF.insert(llvm::next(MachineFunction::iterator(MBB)), NewMBB);
2321 // Split MBB after MI and return the new block (the one that contains
2322 // instructions after MI).
2323 static MachineBasicBlock *splitBlockAfter(MachineInstr *MI,
2324 MachineBasicBlock *MBB) {
2325 MachineBasicBlock *NewMBB = emitBlockAfter(MBB);
2326 NewMBB->splice(NewMBB->begin(), MBB,
2327 llvm::next(MachineBasicBlock::iterator(MI)),
2329 NewMBB->transferSuccessorsAndUpdatePHIs(MBB);
2333 // Split MBB before MI and return the new block (the one that contains MI).
2334 static MachineBasicBlock *splitBlockBefore(MachineInstr *MI,
2335 MachineBasicBlock *MBB) {
2336 MachineBasicBlock *NewMBB = emitBlockAfter(MBB);
2337 NewMBB->splice(NewMBB->begin(), MBB, MI, MBB->end());
2338 NewMBB->transferSuccessorsAndUpdatePHIs(MBB);
2342 // Force base value Base into a register before MI. Return the register.
2343 static unsigned forceReg(MachineInstr *MI, MachineOperand &Base,
2344 const SystemZInstrInfo *TII) {
2346 return Base.getReg();
2348 MachineBasicBlock *MBB = MI->getParent();
2349 MachineFunction &MF = *MBB->getParent();
2350 MachineRegisterInfo &MRI = MF.getRegInfo();
2352 unsigned Reg = MRI.createVirtualRegister(&SystemZ::ADDR64BitRegClass);
2353 BuildMI(*MBB, MI, MI->getDebugLoc(), TII->get(SystemZ::LA), Reg)
2354 .addOperand(Base).addImm(0).addReg(0);
2358 // Implement EmitInstrWithCustomInserter for pseudo Select* instruction MI.
2360 SystemZTargetLowering::emitSelect(MachineInstr *MI,
2361 MachineBasicBlock *MBB) const {
2362 const SystemZInstrInfo *TII = TM.getInstrInfo();
2364 unsigned DestReg = MI->getOperand(0).getReg();
2365 unsigned TrueReg = MI->getOperand(1).getReg();
2366 unsigned FalseReg = MI->getOperand(2).getReg();
2367 unsigned CCValid = MI->getOperand(3).getImm();
2368 unsigned CCMask = MI->getOperand(4).getImm();
2369 DebugLoc DL = MI->getDebugLoc();
2371 MachineBasicBlock *StartMBB = MBB;
2372 MachineBasicBlock *JoinMBB = splitBlockBefore(MI, MBB);
2373 MachineBasicBlock *FalseMBB = emitBlockAfter(StartMBB);
2376 // BRC CCMask, JoinMBB
2377 // # fallthrough to FalseMBB
2379 BuildMI(MBB, DL, TII->get(SystemZ::BRC))
2380 .addImm(CCValid).addImm(CCMask).addMBB(JoinMBB);
2381 MBB->addSuccessor(JoinMBB);
2382 MBB->addSuccessor(FalseMBB);
2385 // # fallthrough to JoinMBB
2387 MBB->addSuccessor(JoinMBB);
2390 // %Result = phi [ %FalseReg, FalseMBB ], [ %TrueReg, StartMBB ]
2393 BuildMI(*MBB, MI, DL, TII->get(SystemZ::PHI), DestReg)
2394 .addReg(TrueReg).addMBB(StartMBB)
2395 .addReg(FalseReg).addMBB(FalseMBB);
2397 MI->eraseFromParent();
2401 // Implement EmitInstrWithCustomInserter for pseudo CondStore* instruction MI.
2402 // StoreOpcode is the store to use and Invert says whether the store should
2403 // happen when the condition is false rather than true. If a STORE ON
2404 // CONDITION is available, STOCOpcode is its opcode, otherwise it is 0.
2406 SystemZTargetLowering::emitCondStore(MachineInstr *MI,
2407 MachineBasicBlock *MBB,
2408 unsigned StoreOpcode, unsigned STOCOpcode,
2409 bool Invert) const {
2410 const SystemZInstrInfo *TII = TM.getInstrInfo();
2412 unsigned SrcReg = MI->getOperand(0).getReg();
2413 MachineOperand Base = MI->getOperand(1);
2414 int64_t Disp = MI->getOperand(2).getImm();
2415 unsigned IndexReg = MI->getOperand(3).getReg();
2416 unsigned CCValid = MI->getOperand(4).getImm();
2417 unsigned CCMask = MI->getOperand(5).getImm();
2418 DebugLoc DL = MI->getDebugLoc();
2420 StoreOpcode = TII->getOpcodeForOffset(StoreOpcode, Disp);
2422 // Use STOCOpcode if possible. We could use different store patterns in
2423 // order to avoid matching the index register, but the performance trade-offs
2424 // might be more complicated in that case.
2425 if (STOCOpcode && !IndexReg && TM.getSubtargetImpl()->hasLoadStoreOnCond()) {
2428 BuildMI(*MBB, MI, DL, TII->get(STOCOpcode))
2429 .addReg(SrcReg).addOperand(Base).addImm(Disp)
2430 .addImm(CCValid).addImm(CCMask);
2431 MI->eraseFromParent();
2435 // Get the condition needed to branch around the store.
2439 MachineBasicBlock *StartMBB = MBB;
2440 MachineBasicBlock *JoinMBB = splitBlockBefore(MI, MBB);
2441 MachineBasicBlock *FalseMBB = emitBlockAfter(StartMBB);
2444 // BRC CCMask, JoinMBB
2445 // # fallthrough to FalseMBB
2447 BuildMI(MBB, DL, TII->get(SystemZ::BRC))
2448 .addImm(CCValid).addImm(CCMask).addMBB(JoinMBB);
2449 MBB->addSuccessor(JoinMBB);
2450 MBB->addSuccessor(FalseMBB);
2453 // store %SrcReg, %Disp(%Index,%Base)
2454 // # fallthrough to JoinMBB
2456 BuildMI(MBB, DL, TII->get(StoreOpcode))
2457 .addReg(SrcReg).addOperand(Base).addImm(Disp).addReg(IndexReg);
2458 MBB->addSuccessor(JoinMBB);
2460 MI->eraseFromParent();
2464 // Implement EmitInstrWithCustomInserter for pseudo ATOMIC_LOAD{,W}_*
2465 // or ATOMIC_SWAP{,W} instruction MI. BinOpcode is the instruction that
2466 // performs the binary operation elided by "*", or 0 for ATOMIC_SWAP{,W}.
2467 // BitSize is the width of the field in bits, or 0 if this is a partword
2468 // ATOMIC_LOADW_* or ATOMIC_SWAPW instruction, in which case the bitsize
2469 // is one of the operands. Invert says whether the field should be
2470 // inverted after performing BinOpcode (e.g. for NAND).
2472 SystemZTargetLowering::emitAtomicLoadBinary(MachineInstr *MI,
2473 MachineBasicBlock *MBB,
2476 bool Invert) const {
2477 const SystemZInstrInfo *TII = TM.getInstrInfo();
2478 MachineFunction &MF = *MBB->getParent();
2479 MachineRegisterInfo &MRI = MF.getRegInfo();
2480 bool IsSubWord = (BitSize < 32);
2482 // Extract the operands. Base can be a register or a frame index.
2483 // Src2 can be a register or immediate.
2484 unsigned Dest = MI->getOperand(0).getReg();
2485 MachineOperand Base = earlyUseOperand(MI->getOperand(1));
2486 int64_t Disp = MI->getOperand(2).getImm();
2487 MachineOperand Src2 = earlyUseOperand(MI->getOperand(3));
2488 unsigned BitShift = (IsSubWord ? MI->getOperand(4).getReg() : 0);
2489 unsigned NegBitShift = (IsSubWord ? MI->getOperand(5).getReg() : 0);
2490 DebugLoc DL = MI->getDebugLoc();
2492 BitSize = MI->getOperand(6).getImm();
2494 // Subword operations use 32-bit registers.
2495 const TargetRegisterClass *RC = (BitSize <= 32 ?
2496 &SystemZ::GR32BitRegClass :
2497 &SystemZ::GR64BitRegClass);
2498 unsigned LOpcode = BitSize <= 32 ? SystemZ::L : SystemZ::LG;
2499 unsigned CSOpcode = BitSize <= 32 ? SystemZ::CS : SystemZ::CSG;
2501 // Get the right opcodes for the displacement.
2502 LOpcode = TII->getOpcodeForOffset(LOpcode, Disp);
2503 CSOpcode = TII->getOpcodeForOffset(CSOpcode, Disp);
2504 assert(LOpcode && CSOpcode && "Displacement out of range");
2506 // Create virtual registers for temporary results.
2507 unsigned OrigVal = MRI.createVirtualRegister(RC);
2508 unsigned OldVal = MRI.createVirtualRegister(RC);
2509 unsigned NewVal = (BinOpcode || IsSubWord ?
2510 MRI.createVirtualRegister(RC) : Src2.getReg());
2511 unsigned RotatedOldVal = (IsSubWord ? MRI.createVirtualRegister(RC) : OldVal);
2512 unsigned RotatedNewVal = (IsSubWord ? MRI.createVirtualRegister(RC) : NewVal);
2514 // Insert a basic block for the main loop.
2515 MachineBasicBlock *StartMBB = MBB;
2516 MachineBasicBlock *DoneMBB = splitBlockBefore(MI, MBB);
2517 MachineBasicBlock *LoopMBB = emitBlockAfter(StartMBB);
2521 // %OrigVal = L Disp(%Base)
2522 // # fall through to LoopMMB
2524 BuildMI(MBB, DL, TII->get(LOpcode), OrigVal)
2525 .addOperand(Base).addImm(Disp).addReg(0);
2526 MBB->addSuccessor(LoopMBB);
2529 // %OldVal = phi [ %OrigVal, StartMBB ], [ %Dest, LoopMBB ]
2530 // %RotatedOldVal = RLL %OldVal, 0(%BitShift)
2531 // %RotatedNewVal = OP %RotatedOldVal, %Src2
2532 // %NewVal = RLL %RotatedNewVal, 0(%NegBitShift)
2533 // %Dest = CS %OldVal, %NewVal, Disp(%Base)
2535 // # fall through to DoneMMB
2537 BuildMI(MBB, DL, TII->get(SystemZ::PHI), OldVal)
2538 .addReg(OrigVal).addMBB(StartMBB)
2539 .addReg(Dest).addMBB(LoopMBB);
2541 BuildMI(MBB, DL, TII->get(SystemZ::RLL), RotatedOldVal)
2542 .addReg(OldVal).addReg(BitShift).addImm(0);
2544 // Perform the operation normally and then invert every bit of the field.
2545 unsigned Tmp = MRI.createVirtualRegister(RC);
2546 BuildMI(MBB, DL, TII->get(BinOpcode), Tmp)
2547 .addReg(RotatedOldVal).addOperand(Src2);
2549 // XILF with the upper BitSize bits set.
2550 BuildMI(MBB, DL, TII->get(SystemZ::XILF), RotatedNewVal)
2551 .addReg(Tmp).addImm(uint32_t(~0 << (32 - BitSize)));
2552 else if (BitSize == 32)
2553 // XILF with every bit set.
2554 BuildMI(MBB, DL, TII->get(SystemZ::XILF), RotatedNewVal)
2555 .addReg(Tmp).addImm(~uint32_t(0));
2557 // Use LCGR and add -1 to the result, which is more compact than
2558 // an XILF, XILH pair.
2559 unsigned Tmp2 = MRI.createVirtualRegister(RC);
2560 BuildMI(MBB, DL, TII->get(SystemZ::LCGR), Tmp2).addReg(Tmp);
2561 BuildMI(MBB, DL, TII->get(SystemZ::AGHI), RotatedNewVal)
2562 .addReg(Tmp2).addImm(-1);
2564 } else if (BinOpcode)
2565 // A simply binary operation.
2566 BuildMI(MBB, DL, TII->get(BinOpcode), RotatedNewVal)
2567 .addReg(RotatedOldVal).addOperand(Src2);
2569 // Use RISBG to rotate Src2 into position and use it to replace the
2570 // field in RotatedOldVal.
2571 BuildMI(MBB, DL, TII->get(SystemZ::RISBG32), RotatedNewVal)
2572 .addReg(RotatedOldVal).addReg(Src2.getReg())
2573 .addImm(32).addImm(31 + BitSize).addImm(32 - BitSize);
2575 BuildMI(MBB, DL, TII->get(SystemZ::RLL), NewVal)
2576 .addReg(RotatedNewVal).addReg(NegBitShift).addImm(0);
2577 BuildMI(MBB, DL, TII->get(CSOpcode), Dest)
2578 .addReg(OldVal).addReg(NewVal).addOperand(Base).addImm(Disp);
2579 BuildMI(MBB, DL, TII->get(SystemZ::BRC))
2580 .addImm(SystemZ::CCMASK_CS).addImm(SystemZ::CCMASK_CS_NE).addMBB(LoopMBB);
2581 MBB->addSuccessor(LoopMBB);
2582 MBB->addSuccessor(DoneMBB);
2584 MI->eraseFromParent();
2588 // Implement EmitInstrWithCustomInserter for pseudo
2589 // ATOMIC_LOAD{,W}_{,U}{MIN,MAX} instruction MI. CompareOpcode is the
2590 // instruction that should be used to compare the current field with the
2591 // minimum or maximum value. KeepOldMask is the BRC condition-code mask
2592 // for when the current field should be kept. BitSize is the width of
2593 // the field in bits, or 0 if this is a partword ATOMIC_LOADW_* instruction.
2595 SystemZTargetLowering::emitAtomicLoadMinMax(MachineInstr *MI,
2596 MachineBasicBlock *MBB,
2597 unsigned CompareOpcode,
2598 unsigned KeepOldMask,
2599 unsigned BitSize) const {
2600 const SystemZInstrInfo *TII = TM.getInstrInfo();
2601 MachineFunction &MF = *MBB->getParent();
2602 MachineRegisterInfo &MRI = MF.getRegInfo();
2603 bool IsSubWord = (BitSize < 32);
2605 // Extract the operands. Base can be a register or a frame index.
2606 unsigned Dest = MI->getOperand(0).getReg();
2607 MachineOperand Base = earlyUseOperand(MI->getOperand(1));
2608 int64_t Disp = MI->getOperand(2).getImm();
2609 unsigned Src2 = MI->getOperand(3).getReg();
2610 unsigned BitShift = (IsSubWord ? MI->getOperand(4).getReg() : 0);
2611 unsigned NegBitShift = (IsSubWord ? MI->getOperand(5).getReg() : 0);
2612 DebugLoc DL = MI->getDebugLoc();
2614 BitSize = MI->getOperand(6).getImm();
2616 // Subword operations use 32-bit registers.
2617 const TargetRegisterClass *RC = (BitSize <= 32 ?
2618 &SystemZ::GR32BitRegClass :
2619 &SystemZ::GR64BitRegClass);
2620 unsigned LOpcode = BitSize <= 32 ? SystemZ::L : SystemZ::LG;
2621 unsigned CSOpcode = BitSize <= 32 ? SystemZ::CS : SystemZ::CSG;
2623 // Get the right opcodes for the displacement.
2624 LOpcode = TII->getOpcodeForOffset(LOpcode, Disp);
2625 CSOpcode = TII->getOpcodeForOffset(CSOpcode, Disp);
2626 assert(LOpcode && CSOpcode && "Displacement out of range");
2628 // Create virtual registers for temporary results.
2629 unsigned OrigVal = MRI.createVirtualRegister(RC);
2630 unsigned OldVal = MRI.createVirtualRegister(RC);
2631 unsigned NewVal = MRI.createVirtualRegister(RC);
2632 unsigned RotatedOldVal = (IsSubWord ? MRI.createVirtualRegister(RC) : OldVal);
2633 unsigned RotatedAltVal = (IsSubWord ? MRI.createVirtualRegister(RC) : Src2);
2634 unsigned RotatedNewVal = (IsSubWord ? MRI.createVirtualRegister(RC) : NewVal);
2636 // Insert 3 basic blocks for the loop.
2637 MachineBasicBlock *StartMBB = MBB;
2638 MachineBasicBlock *DoneMBB = splitBlockBefore(MI, MBB);
2639 MachineBasicBlock *LoopMBB = emitBlockAfter(StartMBB);
2640 MachineBasicBlock *UseAltMBB = emitBlockAfter(LoopMBB);
2641 MachineBasicBlock *UpdateMBB = emitBlockAfter(UseAltMBB);
2645 // %OrigVal = L Disp(%Base)
2646 // # fall through to LoopMMB
2648 BuildMI(MBB, DL, TII->get(LOpcode), OrigVal)
2649 .addOperand(Base).addImm(Disp).addReg(0);
2650 MBB->addSuccessor(LoopMBB);
2653 // %OldVal = phi [ %OrigVal, StartMBB ], [ %Dest, UpdateMBB ]
2654 // %RotatedOldVal = RLL %OldVal, 0(%BitShift)
2655 // CompareOpcode %RotatedOldVal, %Src2
2656 // BRC KeepOldMask, UpdateMBB
2658 BuildMI(MBB, DL, TII->get(SystemZ::PHI), OldVal)
2659 .addReg(OrigVal).addMBB(StartMBB)
2660 .addReg(Dest).addMBB(UpdateMBB);
2662 BuildMI(MBB, DL, TII->get(SystemZ::RLL), RotatedOldVal)
2663 .addReg(OldVal).addReg(BitShift).addImm(0);
2664 BuildMI(MBB, DL, TII->get(CompareOpcode))
2665 .addReg(RotatedOldVal).addReg(Src2);
2666 BuildMI(MBB, DL, TII->get(SystemZ::BRC))
2667 .addImm(SystemZ::CCMASK_ICMP).addImm(KeepOldMask).addMBB(UpdateMBB);
2668 MBB->addSuccessor(UpdateMBB);
2669 MBB->addSuccessor(UseAltMBB);
2672 // %RotatedAltVal = RISBG %RotatedOldVal, %Src2, 32, 31 + BitSize, 0
2673 // # fall through to UpdateMMB
2676 BuildMI(MBB, DL, TII->get(SystemZ::RISBG32), RotatedAltVal)
2677 .addReg(RotatedOldVal).addReg(Src2)
2678 .addImm(32).addImm(31 + BitSize).addImm(0);
2679 MBB->addSuccessor(UpdateMBB);
2682 // %RotatedNewVal = PHI [ %RotatedOldVal, LoopMBB ],
2683 // [ %RotatedAltVal, UseAltMBB ]
2684 // %NewVal = RLL %RotatedNewVal, 0(%NegBitShift)
2685 // %Dest = CS %OldVal, %NewVal, Disp(%Base)
2687 // # fall through to DoneMMB
2689 BuildMI(MBB, DL, TII->get(SystemZ::PHI), RotatedNewVal)
2690 .addReg(RotatedOldVal).addMBB(LoopMBB)
2691 .addReg(RotatedAltVal).addMBB(UseAltMBB);
2693 BuildMI(MBB, DL, TII->get(SystemZ::RLL), NewVal)
2694 .addReg(RotatedNewVal).addReg(NegBitShift).addImm(0);
2695 BuildMI(MBB, DL, TII->get(CSOpcode), Dest)
2696 .addReg(OldVal).addReg(NewVal).addOperand(Base).addImm(Disp);
2697 BuildMI(MBB, DL, TII->get(SystemZ::BRC))
2698 .addImm(SystemZ::CCMASK_CS).addImm(SystemZ::CCMASK_CS_NE).addMBB(LoopMBB);
2699 MBB->addSuccessor(LoopMBB);
2700 MBB->addSuccessor(DoneMBB);
2702 MI->eraseFromParent();
2706 // Implement EmitInstrWithCustomInserter for pseudo ATOMIC_CMP_SWAPW
2709 SystemZTargetLowering::emitAtomicCmpSwapW(MachineInstr *MI,
2710 MachineBasicBlock *MBB) const {
2711 const SystemZInstrInfo *TII = TM.getInstrInfo();
2712 MachineFunction &MF = *MBB->getParent();
2713 MachineRegisterInfo &MRI = MF.getRegInfo();
2715 // Extract the operands. Base can be a register or a frame index.
2716 unsigned Dest = MI->getOperand(0).getReg();
2717 MachineOperand Base = earlyUseOperand(MI->getOperand(1));
2718 int64_t Disp = MI->getOperand(2).getImm();
2719 unsigned OrigCmpVal = MI->getOperand(3).getReg();
2720 unsigned OrigSwapVal = MI->getOperand(4).getReg();
2721 unsigned BitShift = MI->getOperand(5).getReg();
2722 unsigned NegBitShift = MI->getOperand(6).getReg();
2723 int64_t BitSize = MI->getOperand(7).getImm();
2724 DebugLoc DL = MI->getDebugLoc();
2726 const TargetRegisterClass *RC = &SystemZ::GR32BitRegClass;
2728 // Get the right opcodes for the displacement.
2729 unsigned LOpcode = TII->getOpcodeForOffset(SystemZ::L, Disp);
2730 unsigned CSOpcode = TII->getOpcodeForOffset(SystemZ::CS, Disp);
2731 assert(LOpcode && CSOpcode && "Displacement out of range");
2733 // Create virtual registers for temporary results.
2734 unsigned OrigOldVal = MRI.createVirtualRegister(RC);
2735 unsigned OldVal = MRI.createVirtualRegister(RC);
2736 unsigned CmpVal = MRI.createVirtualRegister(RC);
2737 unsigned SwapVal = MRI.createVirtualRegister(RC);
2738 unsigned StoreVal = MRI.createVirtualRegister(RC);
2739 unsigned RetryOldVal = MRI.createVirtualRegister(RC);
2740 unsigned RetryCmpVal = MRI.createVirtualRegister(RC);
2741 unsigned RetrySwapVal = MRI.createVirtualRegister(RC);
2743 // Insert 2 basic blocks for the loop.
2744 MachineBasicBlock *StartMBB = MBB;
2745 MachineBasicBlock *DoneMBB = splitBlockBefore(MI, MBB);
2746 MachineBasicBlock *LoopMBB = emitBlockAfter(StartMBB);
2747 MachineBasicBlock *SetMBB = emitBlockAfter(LoopMBB);
2751 // %OrigOldVal = L Disp(%Base)
2752 // # fall through to LoopMMB
2754 BuildMI(MBB, DL, TII->get(LOpcode), OrigOldVal)
2755 .addOperand(Base).addImm(Disp).addReg(0);
2756 MBB->addSuccessor(LoopMBB);
2759 // %OldVal = phi [ %OrigOldVal, EntryBB ], [ %RetryOldVal, SetMBB ]
2760 // %CmpVal = phi [ %OrigCmpVal, EntryBB ], [ %RetryCmpVal, SetMBB ]
2761 // %SwapVal = phi [ %OrigSwapVal, EntryBB ], [ %RetrySwapVal, SetMBB ]
2762 // %Dest = RLL %OldVal, BitSize(%BitShift)
2763 // ^^ The low BitSize bits contain the field
2765 // %RetryCmpVal = RISBG32 %CmpVal, %Dest, 32, 63-BitSize, 0
2766 // ^^ Replace the upper 32-BitSize bits of the
2767 // comparison value with those that we loaded,
2768 // so that we can use a full word comparison.
2769 // CR %Dest, %RetryCmpVal
2771 // # Fall through to SetMBB
2773 BuildMI(MBB, DL, TII->get(SystemZ::PHI), OldVal)
2774 .addReg(OrigOldVal).addMBB(StartMBB)
2775 .addReg(RetryOldVal).addMBB(SetMBB);
2776 BuildMI(MBB, DL, TII->get(SystemZ::PHI), CmpVal)
2777 .addReg(OrigCmpVal).addMBB(StartMBB)
2778 .addReg(RetryCmpVal).addMBB(SetMBB);
2779 BuildMI(MBB, DL, TII->get(SystemZ::PHI), SwapVal)
2780 .addReg(OrigSwapVal).addMBB(StartMBB)
2781 .addReg(RetrySwapVal).addMBB(SetMBB);
2782 BuildMI(MBB, DL, TII->get(SystemZ::RLL), Dest)
2783 .addReg(OldVal).addReg(BitShift).addImm(BitSize);
2784 BuildMI(MBB, DL, TII->get(SystemZ::RISBG32), RetryCmpVal)
2785 .addReg(CmpVal).addReg(Dest).addImm(32).addImm(63 - BitSize).addImm(0);
2786 BuildMI(MBB, DL, TII->get(SystemZ::CR))
2787 .addReg(Dest).addReg(RetryCmpVal);
2788 BuildMI(MBB, DL, TII->get(SystemZ::BRC))
2789 .addImm(SystemZ::CCMASK_ICMP)
2790 .addImm(SystemZ::CCMASK_CMP_NE).addMBB(DoneMBB);
2791 MBB->addSuccessor(DoneMBB);
2792 MBB->addSuccessor(SetMBB);
2795 // %RetrySwapVal = RISBG32 %SwapVal, %Dest, 32, 63-BitSize, 0
2796 // ^^ Replace the upper 32-BitSize bits of the new
2797 // value with those that we loaded.
2798 // %StoreVal = RLL %RetrySwapVal, -BitSize(%NegBitShift)
2799 // ^^ Rotate the new field to its proper position.
2800 // %RetryOldVal = CS %Dest, %StoreVal, Disp(%Base)
2802 // # fall through to ExitMMB
2804 BuildMI(MBB, DL, TII->get(SystemZ::RISBG32), RetrySwapVal)
2805 .addReg(SwapVal).addReg(Dest).addImm(32).addImm(63 - BitSize).addImm(0);
2806 BuildMI(MBB, DL, TII->get(SystemZ::RLL), StoreVal)
2807 .addReg(RetrySwapVal).addReg(NegBitShift).addImm(-BitSize);
2808 BuildMI(MBB, DL, TII->get(CSOpcode), RetryOldVal)
2809 .addReg(OldVal).addReg(StoreVal).addOperand(Base).addImm(Disp);
2810 BuildMI(MBB, DL, TII->get(SystemZ::BRC))
2811 .addImm(SystemZ::CCMASK_CS).addImm(SystemZ::CCMASK_CS_NE).addMBB(LoopMBB);
2812 MBB->addSuccessor(LoopMBB);
2813 MBB->addSuccessor(DoneMBB);
2815 MI->eraseFromParent();
2819 // Emit an extension from a GR32 or GR64 to a GR128. ClearEven is true
2820 // if the high register of the GR128 value must be cleared or false if
2821 // it's "don't care". SubReg is subreg_l32 when extending a GR32
2822 // and subreg_l64 when extending a GR64.
2824 SystemZTargetLowering::emitExt128(MachineInstr *MI,
2825 MachineBasicBlock *MBB,
2826 bool ClearEven, unsigned SubReg) const {
2827 const SystemZInstrInfo *TII = TM.getInstrInfo();
2828 MachineFunction &MF = *MBB->getParent();
2829 MachineRegisterInfo &MRI = MF.getRegInfo();
2830 DebugLoc DL = MI->getDebugLoc();
2832 unsigned Dest = MI->getOperand(0).getReg();
2833 unsigned Src = MI->getOperand(1).getReg();
2834 unsigned In128 = MRI.createVirtualRegister(&SystemZ::GR128BitRegClass);
2836 BuildMI(*MBB, MI, DL, TII->get(TargetOpcode::IMPLICIT_DEF), In128);
2838 unsigned NewIn128 = MRI.createVirtualRegister(&SystemZ::GR128BitRegClass);
2839 unsigned Zero64 = MRI.createVirtualRegister(&SystemZ::GR64BitRegClass);
2841 BuildMI(*MBB, MI, DL, TII->get(SystemZ::LLILL), Zero64)
2843 BuildMI(*MBB, MI, DL, TII->get(TargetOpcode::INSERT_SUBREG), NewIn128)
2844 .addReg(In128).addReg(Zero64).addImm(SystemZ::subreg_h64);
2847 BuildMI(*MBB, MI, DL, TII->get(TargetOpcode::INSERT_SUBREG), Dest)
2848 .addReg(In128).addReg(Src).addImm(SubReg);
2850 MI->eraseFromParent();
2855 SystemZTargetLowering::emitMemMemWrapper(MachineInstr *MI,
2856 MachineBasicBlock *MBB,
2857 unsigned Opcode) const {
2858 const SystemZInstrInfo *TII = TM.getInstrInfo();
2859 MachineFunction &MF = *MBB->getParent();
2860 MachineRegisterInfo &MRI = MF.getRegInfo();
2861 DebugLoc DL = MI->getDebugLoc();
2863 MachineOperand DestBase = earlyUseOperand(MI->getOperand(0));
2864 uint64_t DestDisp = MI->getOperand(1).getImm();
2865 MachineOperand SrcBase = earlyUseOperand(MI->getOperand(2));
2866 uint64_t SrcDisp = MI->getOperand(3).getImm();
2867 uint64_t Length = MI->getOperand(4).getImm();
2869 // When generating more than one CLC, all but the last will need to
2870 // branch to the end when a difference is found.
2871 MachineBasicBlock *EndMBB = (Length > 256 && Opcode == SystemZ::CLC ?
2872 splitBlockAfter(MI, MBB) : 0);
2874 // Check for the loop form, in which operand 5 is the trip count.
2875 if (MI->getNumExplicitOperands() > 5) {
2876 bool HaveSingleBase = DestBase.isIdenticalTo(SrcBase);
2878 uint64_t StartCountReg = MI->getOperand(5).getReg();
2879 uint64_t StartSrcReg = forceReg(MI, SrcBase, TII);
2880 uint64_t StartDestReg = (HaveSingleBase ? StartSrcReg :
2881 forceReg(MI, DestBase, TII));
2883 const TargetRegisterClass *RC = &SystemZ::ADDR64BitRegClass;
2884 uint64_t ThisSrcReg = MRI.createVirtualRegister(RC);
2885 uint64_t ThisDestReg = (HaveSingleBase ? ThisSrcReg :
2886 MRI.createVirtualRegister(RC));
2887 uint64_t NextSrcReg = MRI.createVirtualRegister(RC);
2888 uint64_t NextDestReg = (HaveSingleBase ? NextSrcReg :
2889 MRI.createVirtualRegister(RC));
2891 RC = &SystemZ::GR64BitRegClass;
2892 uint64_t ThisCountReg = MRI.createVirtualRegister(RC);
2893 uint64_t NextCountReg = MRI.createVirtualRegister(RC);
2895 MachineBasicBlock *StartMBB = MBB;
2896 MachineBasicBlock *DoneMBB = splitBlockBefore(MI, MBB);
2897 MachineBasicBlock *LoopMBB = emitBlockAfter(StartMBB);
2898 MachineBasicBlock *NextMBB = (EndMBB ? emitBlockAfter(LoopMBB) : LoopMBB);
2901 // # fall through to LoopMMB
2902 MBB->addSuccessor(LoopMBB);
2905 // %ThisDestReg = phi [ %StartDestReg, StartMBB ],
2906 // [ %NextDestReg, NextMBB ]
2907 // %ThisSrcReg = phi [ %StartSrcReg, StartMBB ],
2908 // [ %NextSrcReg, NextMBB ]
2909 // %ThisCountReg = phi [ %StartCountReg, StartMBB ],
2910 // [ %NextCountReg, NextMBB ]
2911 // ( PFD 2, 768+DestDisp(%ThisDestReg) )
2912 // Opcode DestDisp(256,%ThisDestReg), SrcDisp(%ThisSrcReg)
2915 // The prefetch is used only for MVC. The JLH is used only for CLC.
2918 BuildMI(MBB, DL, TII->get(SystemZ::PHI), ThisDestReg)
2919 .addReg(StartDestReg).addMBB(StartMBB)
2920 .addReg(NextDestReg).addMBB(NextMBB);
2921 if (!HaveSingleBase)
2922 BuildMI(MBB, DL, TII->get(SystemZ::PHI), ThisSrcReg)
2923 .addReg(StartSrcReg).addMBB(StartMBB)
2924 .addReg(NextSrcReg).addMBB(NextMBB);
2925 BuildMI(MBB, DL, TII->get(SystemZ::PHI), ThisCountReg)
2926 .addReg(StartCountReg).addMBB(StartMBB)
2927 .addReg(NextCountReg).addMBB(NextMBB);
2928 if (Opcode == SystemZ::MVC)
2929 BuildMI(MBB, DL, TII->get(SystemZ::PFD))
2930 .addImm(SystemZ::PFD_WRITE)
2931 .addReg(ThisDestReg).addImm(DestDisp + 768).addReg(0);
2932 BuildMI(MBB, DL, TII->get(Opcode))
2933 .addReg(ThisDestReg).addImm(DestDisp).addImm(256)
2934 .addReg(ThisSrcReg).addImm(SrcDisp);
2936 BuildMI(MBB, DL, TII->get(SystemZ::BRC))
2937 .addImm(SystemZ::CCMASK_ICMP).addImm(SystemZ::CCMASK_CMP_NE)
2939 MBB->addSuccessor(EndMBB);
2940 MBB->addSuccessor(NextMBB);
2944 // %NextDestReg = LA 256(%ThisDestReg)
2945 // %NextSrcReg = LA 256(%ThisSrcReg)
2946 // %NextCountReg = AGHI %ThisCountReg, -1
2947 // CGHI %NextCountReg, 0
2949 // # fall through to DoneMMB
2951 // The AGHI, CGHI and JLH should be converted to BRCTG by later passes.
2954 BuildMI(MBB, DL, TII->get(SystemZ::LA), NextDestReg)
2955 .addReg(ThisDestReg).addImm(256).addReg(0);
2956 if (!HaveSingleBase)
2957 BuildMI(MBB, DL, TII->get(SystemZ::LA), NextSrcReg)
2958 .addReg(ThisSrcReg).addImm(256).addReg(0);
2959 BuildMI(MBB, DL, TII->get(SystemZ::AGHI), NextCountReg)
2960 .addReg(ThisCountReg).addImm(-1);
2961 BuildMI(MBB, DL, TII->get(SystemZ::CGHI))
2962 .addReg(NextCountReg).addImm(0);
2963 BuildMI(MBB, DL, TII->get(SystemZ::BRC))
2964 .addImm(SystemZ::CCMASK_ICMP).addImm(SystemZ::CCMASK_CMP_NE)
2966 MBB->addSuccessor(LoopMBB);
2967 MBB->addSuccessor(DoneMBB);
2969 DestBase = MachineOperand::CreateReg(NextDestReg, false);
2970 SrcBase = MachineOperand::CreateReg(NextSrcReg, false);
2974 // Handle any remaining bytes with straight-line code.
2975 while (Length > 0) {
2976 uint64_t ThisLength = std::min(Length, uint64_t(256));
2977 // The previous iteration might have created out-of-range displacements.
2978 // Apply them using LAY if so.
2979 if (!isUInt<12>(DestDisp)) {
2980 unsigned Reg = MRI.createVirtualRegister(&SystemZ::ADDR64BitRegClass);
2981 BuildMI(*MBB, MI, MI->getDebugLoc(), TII->get(SystemZ::LAY), Reg)
2982 .addOperand(DestBase).addImm(DestDisp).addReg(0);
2983 DestBase = MachineOperand::CreateReg(Reg, false);
2986 if (!isUInt<12>(SrcDisp)) {
2987 unsigned Reg = MRI.createVirtualRegister(&SystemZ::ADDR64BitRegClass);
2988 BuildMI(*MBB, MI, MI->getDebugLoc(), TII->get(SystemZ::LAY), Reg)
2989 .addOperand(SrcBase).addImm(SrcDisp).addReg(0);
2990 SrcBase = MachineOperand::CreateReg(Reg, false);
2993 BuildMI(*MBB, MI, DL, TII->get(Opcode))
2994 .addOperand(DestBase).addImm(DestDisp).addImm(ThisLength)
2995 .addOperand(SrcBase).addImm(SrcDisp);
2996 DestDisp += ThisLength;
2997 SrcDisp += ThisLength;
2998 Length -= ThisLength;
2999 // If there's another CLC to go, branch to the end if a difference
3001 if (EndMBB && Length > 0) {
3002 MachineBasicBlock *NextMBB = splitBlockBefore(MI, MBB);
3003 BuildMI(MBB, DL, TII->get(SystemZ::BRC))
3004 .addImm(SystemZ::CCMASK_ICMP).addImm(SystemZ::CCMASK_CMP_NE)
3006 MBB->addSuccessor(EndMBB);
3007 MBB->addSuccessor(NextMBB);
3012 MBB->addSuccessor(EndMBB);
3014 MBB->addLiveIn(SystemZ::CC);
3017 MI->eraseFromParent();
3021 // Decompose string pseudo-instruction MI into a loop that continually performs
3022 // Opcode until CC != 3.
3024 SystemZTargetLowering::emitStringWrapper(MachineInstr *MI,
3025 MachineBasicBlock *MBB,
3026 unsigned Opcode) const {
3027 const SystemZInstrInfo *TII = TM.getInstrInfo();
3028 MachineFunction &MF = *MBB->getParent();
3029 MachineRegisterInfo &MRI = MF.getRegInfo();
3030 DebugLoc DL = MI->getDebugLoc();
3032 uint64_t End1Reg = MI->getOperand(0).getReg();
3033 uint64_t Start1Reg = MI->getOperand(1).getReg();
3034 uint64_t Start2Reg = MI->getOperand(2).getReg();
3035 uint64_t CharReg = MI->getOperand(3).getReg();
3037 const TargetRegisterClass *RC = &SystemZ::GR64BitRegClass;
3038 uint64_t This1Reg = MRI.createVirtualRegister(RC);
3039 uint64_t This2Reg = MRI.createVirtualRegister(RC);
3040 uint64_t End2Reg = MRI.createVirtualRegister(RC);
3042 MachineBasicBlock *StartMBB = MBB;
3043 MachineBasicBlock *DoneMBB = splitBlockBefore(MI, MBB);
3044 MachineBasicBlock *LoopMBB = emitBlockAfter(StartMBB);
3047 // # fall through to LoopMMB
3048 MBB->addSuccessor(LoopMBB);
3051 // %This1Reg = phi [ %Start1Reg, StartMBB ], [ %End1Reg, LoopMBB ]
3052 // %This2Reg = phi [ %Start2Reg, StartMBB ], [ %End2Reg, LoopMBB ]
3054 // %End1Reg, %End2Reg = CLST %This1Reg, %This2Reg -- uses R0L
3056 // # fall through to DoneMMB
3058 // The load of R0L can be hoisted by post-RA LICM.
3061 BuildMI(MBB, DL, TII->get(SystemZ::PHI), This1Reg)
3062 .addReg(Start1Reg).addMBB(StartMBB)
3063 .addReg(End1Reg).addMBB(LoopMBB);
3064 BuildMI(MBB, DL, TII->get(SystemZ::PHI), This2Reg)
3065 .addReg(Start2Reg).addMBB(StartMBB)
3066 .addReg(End2Reg).addMBB(LoopMBB);
3067 BuildMI(MBB, DL, TII->get(TargetOpcode::COPY), SystemZ::R0L).addReg(CharReg);
3068 BuildMI(MBB, DL, TII->get(Opcode))
3069 .addReg(End1Reg, RegState::Define).addReg(End2Reg, RegState::Define)
3070 .addReg(This1Reg).addReg(This2Reg);
3071 BuildMI(MBB, DL, TII->get(SystemZ::BRC))
3072 .addImm(SystemZ::CCMASK_ANY).addImm(SystemZ::CCMASK_3).addMBB(LoopMBB);
3073 MBB->addSuccessor(LoopMBB);
3074 MBB->addSuccessor(DoneMBB);
3076 DoneMBB->addLiveIn(SystemZ::CC);
3078 MI->eraseFromParent();
3082 MachineBasicBlock *SystemZTargetLowering::
3083 EmitInstrWithCustomInserter(MachineInstr *MI, MachineBasicBlock *MBB) const {
3084 switch (MI->getOpcode()) {
3085 case SystemZ::Select32Mux:
3086 case SystemZ::Select32:
3087 case SystemZ::SelectF32:
3088 case SystemZ::Select64:
3089 case SystemZ::SelectF64:
3090 case SystemZ::SelectF128:
3091 return emitSelect(MI, MBB);
3093 case SystemZ::CondStore8Mux:
3094 return emitCondStore(MI, MBB, SystemZ::STCMux, 0, false);
3095 case SystemZ::CondStore8MuxInv:
3096 return emitCondStore(MI, MBB, SystemZ::STCMux, 0, true);
3097 case SystemZ::CondStore16Mux:
3098 return emitCondStore(MI, MBB, SystemZ::STHMux, 0, false);
3099 case SystemZ::CondStore16MuxInv:
3100 return emitCondStore(MI, MBB, SystemZ::STHMux, 0, true);
3101 case SystemZ::CondStore8:
3102 return emitCondStore(MI, MBB, SystemZ::STC, 0, false);
3103 case SystemZ::CondStore8Inv:
3104 return emitCondStore(MI, MBB, SystemZ::STC, 0, true);
3105 case SystemZ::CondStore16:
3106 return emitCondStore(MI, MBB, SystemZ::STH, 0, false);
3107 case SystemZ::CondStore16Inv:
3108 return emitCondStore(MI, MBB, SystemZ::STH, 0, true);
3109 case SystemZ::CondStore32:
3110 return emitCondStore(MI, MBB, SystemZ::ST, SystemZ::STOC, false);
3111 case SystemZ::CondStore32Inv:
3112 return emitCondStore(MI, MBB, SystemZ::ST, SystemZ::STOC, true);
3113 case SystemZ::CondStore64:
3114 return emitCondStore(MI, MBB, SystemZ::STG, SystemZ::STOCG, false);
3115 case SystemZ::CondStore64Inv:
3116 return emitCondStore(MI, MBB, SystemZ::STG, SystemZ::STOCG, true);
3117 case SystemZ::CondStoreF32:
3118 return emitCondStore(MI, MBB, SystemZ::STE, 0, false);
3119 case SystemZ::CondStoreF32Inv:
3120 return emitCondStore(MI, MBB, SystemZ::STE, 0, true);
3121 case SystemZ::CondStoreF64:
3122 return emitCondStore(MI, MBB, SystemZ::STD, 0, false);
3123 case SystemZ::CondStoreF64Inv:
3124 return emitCondStore(MI, MBB, SystemZ::STD, 0, true);
3126 case SystemZ::AEXT128_64:
3127 return emitExt128(MI, MBB, false, SystemZ::subreg_l64);
3128 case SystemZ::ZEXT128_32:
3129 return emitExt128(MI, MBB, true, SystemZ::subreg_l32);
3130 case SystemZ::ZEXT128_64:
3131 return emitExt128(MI, MBB, true, SystemZ::subreg_l64);
3133 case SystemZ::ATOMIC_SWAPW:
3134 return emitAtomicLoadBinary(MI, MBB, 0, 0);
3135 case SystemZ::ATOMIC_SWAP_32:
3136 return emitAtomicLoadBinary(MI, MBB, 0, 32);
3137 case SystemZ::ATOMIC_SWAP_64:
3138 return emitAtomicLoadBinary(MI, MBB, 0, 64);
3140 case SystemZ::ATOMIC_LOADW_AR:
3141 return emitAtomicLoadBinary(MI, MBB, SystemZ::AR, 0);
3142 case SystemZ::ATOMIC_LOADW_AFI:
3143 return emitAtomicLoadBinary(MI, MBB, SystemZ::AFI, 0);
3144 case SystemZ::ATOMIC_LOAD_AR:
3145 return emitAtomicLoadBinary(MI, MBB, SystemZ::AR, 32);
3146 case SystemZ::ATOMIC_LOAD_AHI:
3147 return emitAtomicLoadBinary(MI, MBB, SystemZ::AHI, 32);
3148 case SystemZ::ATOMIC_LOAD_AFI:
3149 return emitAtomicLoadBinary(MI, MBB, SystemZ::AFI, 32);
3150 case SystemZ::ATOMIC_LOAD_AGR:
3151 return emitAtomicLoadBinary(MI, MBB, SystemZ::AGR, 64);
3152 case SystemZ::ATOMIC_LOAD_AGHI:
3153 return emitAtomicLoadBinary(MI, MBB, SystemZ::AGHI, 64);
3154 case SystemZ::ATOMIC_LOAD_AGFI:
3155 return emitAtomicLoadBinary(MI, MBB, SystemZ::AGFI, 64);
3157 case SystemZ::ATOMIC_LOADW_SR:
3158 return emitAtomicLoadBinary(MI, MBB, SystemZ::SR, 0);
3159 case SystemZ::ATOMIC_LOAD_SR:
3160 return emitAtomicLoadBinary(MI, MBB, SystemZ::SR, 32);
3161 case SystemZ::ATOMIC_LOAD_SGR:
3162 return emitAtomicLoadBinary(MI, MBB, SystemZ::SGR, 64);
3164 case SystemZ::ATOMIC_LOADW_NR:
3165 return emitAtomicLoadBinary(MI, MBB, SystemZ::NR, 0);
3166 case SystemZ::ATOMIC_LOADW_NILH:
3167 return emitAtomicLoadBinary(MI, MBB, SystemZ::NILH, 0);
3168 case SystemZ::ATOMIC_LOAD_NR:
3169 return emitAtomicLoadBinary(MI, MBB, SystemZ::NR, 32);
3170 case SystemZ::ATOMIC_LOAD_NILL:
3171 return emitAtomicLoadBinary(MI, MBB, SystemZ::NILL, 32);
3172 case SystemZ::ATOMIC_LOAD_NILH:
3173 return emitAtomicLoadBinary(MI, MBB, SystemZ::NILH, 32);
3174 case SystemZ::ATOMIC_LOAD_NILF:
3175 return emitAtomicLoadBinary(MI, MBB, SystemZ::NILF, 32);
3176 case SystemZ::ATOMIC_LOAD_NGR:
3177 return emitAtomicLoadBinary(MI, MBB, SystemZ::NGR, 64);
3178 case SystemZ::ATOMIC_LOAD_NILL64:
3179 return emitAtomicLoadBinary(MI, MBB, SystemZ::NILL64, 64);
3180 case SystemZ::ATOMIC_LOAD_NILH64:
3181 return emitAtomicLoadBinary(MI, MBB, SystemZ::NILH64, 64);
3182 case SystemZ::ATOMIC_LOAD_NIHL64:
3183 return emitAtomicLoadBinary(MI, MBB, SystemZ::NIHL64, 64);
3184 case SystemZ::ATOMIC_LOAD_NIHH64:
3185 return emitAtomicLoadBinary(MI, MBB, SystemZ::NIHH64, 64);
3186 case SystemZ::ATOMIC_LOAD_NILF64:
3187 return emitAtomicLoadBinary(MI, MBB, SystemZ::NILF64, 64);
3188 case SystemZ::ATOMIC_LOAD_NIHF64:
3189 return emitAtomicLoadBinary(MI, MBB, SystemZ::NIHF64, 64);
3191 case SystemZ::ATOMIC_LOADW_OR:
3192 return emitAtomicLoadBinary(MI, MBB, SystemZ::OR, 0);
3193 case SystemZ::ATOMIC_LOADW_OILH:
3194 return emitAtomicLoadBinary(MI, MBB, SystemZ::OILH, 0);
3195 case SystemZ::ATOMIC_LOAD_OR:
3196 return emitAtomicLoadBinary(MI, MBB, SystemZ::OR, 32);
3197 case SystemZ::ATOMIC_LOAD_OILL:
3198 return emitAtomicLoadBinary(MI, MBB, SystemZ::OILL, 32);
3199 case SystemZ::ATOMIC_LOAD_OILH:
3200 return emitAtomicLoadBinary(MI, MBB, SystemZ::OILH, 32);
3201 case SystemZ::ATOMIC_LOAD_OILF:
3202 return emitAtomicLoadBinary(MI, MBB, SystemZ::OILF, 32);
3203 case SystemZ::ATOMIC_LOAD_OGR:
3204 return emitAtomicLoadBinary(MI, MBB, SystemZ::OGR, 64);
3205 case SystemZ::ATOMIC_LOAD_OILL64:
3206 return emitAtomicLoadBinary(MI, MBB, SystemZ::OILL64, 64);
3207 case SystemZ::ATOMIC_LOAD_OILH64:
3208 return emitAtomicLoadBinary(MI, MBB, SystemZ::OILH64, 64);
3209 case SystemZ::ATOMIC_LOAD_OIHL64:
3210 return emitAtomicLoadBinary(MI, MBB, SystemZ::OIHL64, 64);
3211 case SystemZ::ATOMIC_LOAD_OIHH64:
3212 return emitAtomicLoadBinary(MI, MBB, SystemZ::OIHH64, 64);
3213 case SystemZ::ATOMIC_LOAD_OILF64:
3214 return emitAtomicLoadBinary(MI, MBB, SystemZ::OILF64, 64);
3215 case SystemZ::ATOMIC_LOAD_OIHF64:
3216 return emitAtomicLoadBinary(MI, MBB, SystemZ::OIHF64, 64);
3218 case SystemZ::ATOMIC_LOADW_XR:
3219 return emitAtomicLoadBinary(MI, MBB, SystemZ::XR, 0);
3220 case SystemZ::ATOMIC_LOADW_XILF:
3221 return emitAtomicLoadBinary(MI, MBB, SystemZ::XILF, 0);
3222 case SystemZ::ATOMIC_LOAD_XR:
3223 return emitAtomicLoadBinary(MI, MBB, SystemZ::XR, 32);
3224 case SystemZ::ATOMIC_LOAD_XILF:
3225 return emitAtomicLoadBinary(MI, MBB, SystemZ::XILF, 32);
3226 case SystemZ::ATOMIC_LOAD_XGR:
3227 return emitAtomicLoadBinary(MI, MBB, SystemZ::XGR, 64);
3228 case SystemZ::ATOMIC_LOAD_XILF64:
3229 return emitAtomicLoadBinary(MI, MBB, SystemZ::XILF64, 64);
3230 case SystemZ::ATOMIC_LOAD_XIHF64:
3231 return emitAtomicLoadBinary(MI, MBB, SystemZ::XIHF64, 64);
3233 case SystemZ::ATOMIC_LOADW_NRi:
3234 return emitAtomicLoadBinary(MI, MBB, SystemZ::NR, 0, true);
3235 case SystemZ::ATOMIC_LOADW_NILHi:
3236 return emitAtomicLoadBinary(MI, MBB, SystemZ::NILH, 0, true);
3237 case SystemZ::ATOMIC_LOAD_NRi:
3238 return emitAtomicLoadBinary(MI, MBB, SystemZ::NR, 32, true);
3239 case SystemZ::ATOMIC_LOAD_NILLi:
3240 return emitAtomicLoadBinary(MI, MBB, SystemZ::NILL, 32, true);
3241 case SystemZ::ATOMIC_LOAD_NILHi:
3242 return emitAtomicLoadBinary(MI, MBB, SystemZ::NILH, 32, true);
3243 case SystemZ::ATOMIC_LOAD_NILFi:
3244 return emitAtomicLoadBinary(MI, MBB, SystemZ::NILF, 32, true);
3245 case SystemZ::ATOMIC_LOAD_NGRi:
3246 return emitAtomicLoadBinary(MI, MBB, SystemZ::NGR, 64, true);
3247 case SystemZ::ATOMIC_LOAD_NILL64i:
3248 return emitAtomicLoadBinary(MI, MBB, SystemZ::NILL64, 64, true);
3249 case SystemZ::ATOMIC_LOAD_NILH64i:
3250 return emitAtomicLoadBinary(MI, MBB, SystemZ::NILH64, 64, true);
3251 case SystemZ::ATOMIC_LOAD_NIHL64i:
3252 return emitAtomicLoadBinary(MI, MBB, SystemZ::NIHL64, 64, true);
3253 case SystemZ::ATOMIC_LOAD_NIHH64i:
3254 return emitAtomicLoadBinary(MI, MBB, SystemZ::NIHH64, 64, true);
3255 case SystemZ::ATOMIC_LOAD_NILF64i:
3256 return emitAtomicLoadBinary(MI, MBB, SystemZ::NILF64, 64, true);
3257 case SystemZ::ATOMIC_LOAD_NIHF64i:
3258 return emitAtomicLoadBinary(MI, MBB, SystemZ::NIHF64, 64, true);
3260 case SystemZ::ATOMIC_LOADW_MIN:
3261 return emitAtomicLoadMinMax(MI, MBB, SystemZ::CR,
3262 SystemZ::CCMASK_CMP_LE, 0);
3263 case SystemZ::ATOMIC_LOAD_MIN_32:
3264 return emitAtomicLoadMinMax(MI, MBB, SystemZ::CR,
3265 SystemZ::CCMASK_CMP_LE, 32);
3266 case SystemZ::ATOMIC_LOAD_MIN_64:
3267 return emitAtomicLoadMinMax(MI, MBB, SystemZ::CGR,
3268 SystemZ::CCMASK_CMP_LE, 64);
3270 case SystemZ::ATOMIC_LOADW_MAX:
3271 return emitAtomicLoadMinMax(MI, MBB, SystemZ::CR,
3272 SystemZ::CCMASK_CMP_GE, 0);
3273 case SystemZ::ATOMIC_LOAD_MAX_32:
3274 return emitAtomicLoadMinMax(MI, MBB, SystemZ::CR,
3275 SystemZ::CCMASK_CMP_GE, 32);
3276 case SystemZ::ATOMIC_LOAD_MAX_64:
3277 return emitAtomicLoadMinMax(MI, MBB, SystemZ::CGR,
3278 SystemZ::CCMASK_CMP_GE, 64);
3280 case SystemZ::ATOMIC_LOADW_UMIN:
3281 return emitAtomicLoadMinMax(MI, MBB, SystemZ::CLR,
3282 SystemZ::CCMASK_CMP_LE, 0);
3283 case SystemZ::ATOMIC_LOAD_UMIN_32:
3284 return emitAtomicLoadMinMax(MI, MBB, SystemZ::CLR,
3285 SystemZ::CCMASK_CMP_LE, 32);
3286 case SystemZ::ATOMIC_LOAD_UMIN_64:
3287 return emitAtomicLoadMinMax(MI, MBB, SystemZ::CLGR,
3288 SystemZ::CCMASK_CMP_LE, 64);
3290 case SystemZ::ATOMIC_LOADW_UMAX:
3291 return emitAtomicLoadMinMax(MI, MBB, SystemZ::CLR,
3292 SystemZ::CCMASK_CMP_GE, 0);
3293 case SystemZ::ATOMIC_LOAD_UMAX_32:
3294 return emitAtomicLoadMinMax(MI, MBB, SystemZ::CLR,
3295 SystemZ::CCMASK_CMP_GE, 32);
3296 case SystemZ::ATOMIC_LOAD_UMAX_64:
3297 return emitAtomicLoadMinMax(MI, MBB, SystemZ::CLGR,
3298 SystemZ::CCMASK_CMP_GE, 64);
3300 case SystemZ::ATOMIC_CMP_SWAPW:
3301 return emitAtomicCmpSwapW(MI, MBB);
3302 case SystemZ::MVCSequence:
3303 case SystemZ::MVCLoop:
3304 return emitMemMemWrapper(MI, MBB, SystemZ::MVC);
3305 case SystemZ::NCSequence:
3306 case SystemZ::NCLoop:
3307 return emitMemMemWrapper(MI, MBB, SystemZ::NC);
3308 case SystemZ::OCSequence:
3309 case SystemZ::OCLoop:
3310 return emitMemMemWrapper(MI, MBB, SystemZ::OC);
3311 case SystemZ::XCSequence:
3312 case SystemZ::XCLoop:
3313 return emitMemMemWrapper(MI, MBB, SystemZ::XC);
3314 case SystemZ::CLCSequence:
3315 case SystemZ::CLCLoop:
3316 return emitMemMemWrapper(MI, MBB, SystemZ::CLC);
3317 case SystemZ::CLSTLoop:
3318 return emitStringWrapper(MI, MBB, SystemZ::CLST);
3319 case SystemZ::MVSTLoop:
3320 return emitStringWrapper(MI, MBB, SystemZ::MVST);
3321 case SystemZ::SRSTLoop:
3322 return emitStringWrapper(MI, MBB, SystemZ::SRST);
3324 llvm_unreachable("Unexpected instr type to insert");