1 //===-- SystemZISelLowering.cpp - SystemZ DAG lowering implementation -----===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements the SystemZTargetLowering class.
12 //===----------------------------------------------------------------------===//
14 #include "SystemZISelLowering.h"
15 #include "SystemZCallingConv.h"
16 #include "SystemZConstantPoolValue.h"
17 #include "SystemZMachineFunctionInfo.h"
18 #include "SystemZTargetMachine.h"
19 #include "llvm/CodeGen/CallingConvLower.h"
20 #include "llvm/CodeGen/MachineInstrBuilder.h"
21 #include "llvm/CodeGen/MachineRegisterInfo.h"
22 #include "llvm/CodeGen/TargetLoweringObjectFileImpl.h"
23 #include "llvm/IR/Intrinsics.h"
28 #define DEBUG_TYPE "systemz-lower"
31 // Represents a sequence for extracting a 0/1 value from an IPM result:
32 // (((X ^ XORValue) + AddValue) >> Bit)
33 struct IPMConversion {
34 IPMConversion(unsigned xorValue, int64_t addValue, unsigned bit)
35 : XORValue(xorValue), AddValue(addValue), Bit(bit) {}
42 // Represents information about a comparison.
44 Comparison(SDValue Op0In, SDValue Op1In)
45 : Op0(Op0In), Op1(Op1In), Opcode(0), ICmpType(0), CCValid(0), CCMask(0) {}
47 // The operands to the comparison.
50 // The opcode that should be used to compare Op0 and Op1.
53 // A SystemZICMP value. Only used for integer comparisons.
56 // The mask of CC values that Opcode can produce.
59 // The mask of CC values for which the original condition is true.
62 } // end anonymous namespace
64 // Classify VT as either 32 or 64 bit.
65 static bool is32Bit(EVT VT) {
66 switch (VT.getSimpleVT().SimpleTy) {
72 llvm_unreachable("Unsupported type");
76 // Return a version of MachineOperand that can be safely used before the
78 static MachineOperand earlyUseOperand(MachineOperand Op) {
84 SystemZTargetLowering::SystemZTargetLowering(const TargetMachine &TM,
85 const SystemZSubtarget &STI)
86 : TargetLowering(TM), Subtarget(STI) {
87 MVT PtrVT = MVT::getIntegerVT(8 * TM.getPointerSize());
89 // Set up the register classes.
90 if (Subtarget.hasHighWord())
91 addRegisterClass(MVT::i32, &SystemZ::GRX32BitRegClass);
93 addRegisterClass(MVT::i32, &SystemZ::GR32BitRegClass);
94 addRegisterClass(MVT::i64, &SystemZ::GR64BitRegClass);
95 if (Subtarget.hasVector()) {
96 addRegisterClass(MVT::f32, &SystemZ::VR32BitRegClass);
97 addRegisterClass(MVT::f64, &SystemZ::VR64BitRegClass);
99 addRegisterClass(MVT::f32, &SystemZ::FP32BitRegClass);
100 addRegisterClass(MVT::f64, &SystemZ::FP64BitRegClass);
102 addRegisterClass(MVT::f128, &SystemZ::FP128BitRegClass);
104 if (Subtarget.hasVector()) {
105 addRegisterClass(MVT::v16i8, &SystemZ::VR128BitRegClass);
106 addRegisterClass(MVT::v8i16, &SystemZ::VR128BitRegClass);
107 addRegisterClass(MVT::v4i32, &SystemZ::VR128BitRegClass);
108 addRegisterClass(MVT::v2i64, &SystemZ::VR128BitRegClass);
109 addRegisterClass(MVT::v4f32, &SystemZ::VR128BitRegClass);
110 addRegisterClass(MVT::v2f64, &SystemZ::VR128BitRegClass);
113 // Compute derived properties from the register classes
114 computeRegisterProperties(Subtarget.getRegisterInfo());
116 // Set up special registers.
117 setExceptionPointerRegister(SystemZ::R6D);
118 setExceptionSelectorRegister(SystemZ::R7D);
119 setStackPointerRegisterToSaveRestore(SystemZ::R15D);
121 // TODO: It may be better to default to latency-oriented scheduling, however
122 // LLVM's current latency-oriented scheduler can't handle physreg definitions
123 // such as SystemZ has with CC, so set this to the register-pressure
124 // scheduler, because it can.
125 setSchedulingPreference(Sched::RegPressure);
127 setBooleanContents(ZeroOrOneBooleanContent);
128 setBooleanVectorContents(ZeroOrNegativeOneBooleanContent);
130 // Instructions are strings of 2-byte aligned 2-byte values.
131 setMinFunctionAlignment(2);
133 // Handle operations that are handled in a similar way for all types.
134 for (unsigned I = MVT::FIRST_INTEGER_VALUETYPE;
135 I <= MVT::LAST_FP_VALUETYPE;
137 MVT VT = MVT::SimpleValueType(I);
138 if (isTypeLegal(VT)) {
139 // Lower SET_CC into an IPM-based sequence.
140 setOperationAction(ISD::SETCC, VT, Custom);
142 // Expand SELECT(C, A, B) into SELECT_CC(X, 0, A, B, NE).
143 setOperationAction(ISD::SELECT, VT, Expand);
145 // Lower SELECT_CC and BR_CC into separate comparisons and branches.
146 setOperationAction(ISD::SELECT_CC, VT, Custom);
147 setOperationAction(ISD::BR_CC, VT, Custom);
151 // Expand jump table branches as address arithmetic followed by an
153 setOperationAction(ISD::BR_JT, MVT::Other, Expand);
155 // Expand BRCOND into a BR_CC (see above).
156 setOperationAction(ISD::BRCOND, MVT::Other, Expand);
158 // Handle integer types.
159 for (unsigned I = MVT::FIRST_INTEGER_VALUETYPE;
160 I <= MVT::LAST_INTEGER_VALUETYPE;
162 MVT VT = MVT::SimpleValueType(I);
163 if (isTypeLegal(VT)) {
164 // Expand individual DIV and REMs into DIVREMs.
165 setOperationAction(ISD::SDIV, VT, Expand);
166 setOperationAction(ISD::UDIV, VT, Expand);
167 setOperationAction(ISD::SREM, VT, Expand);
168 setOperationAction(ISD::UREM, VT, Expand);
169 setOperationAction(ISD::SDIVREM, VT, Custom);
170 setOperationAction(ISD::UDIVREM, VT, Custom);
172 // Lower ATOMIC_LOAD and ATOMIC_STORE into normal volatile loads and
173 // stores, putting a serialization instruction after the stores.
174 setOperationAction(ISD::ATOMIC_LOAD, VT, Custom);
175 setOperationAction(ISD::ATOMIC_STORE, VT, Custom);
177 // Lower ATOMIC_LOAD_SUB into ATOMIC_LOAD_ADD if LAA and LAAG are
178 // available, or if the operand is constant.
179 setOperationAction(ISD::ATOMIC_LOAD_SUB, VT, Custom);
181 // Use POPCNT on z196 and above.
182 if (Subtarget.hasPopulationCount())
183 setOperationAction(ISD::CTPOP, VT, Custom);
185 setOperationAction(ISD::CTPOP, VT, Expand);
187 // No special instructions for these.
188 setOperationAction(ISD::CTTZ, VT, Expand);
189 setOperationAction(ISD::CTTZ_ZERO_UNDEF, VT, Expand);
190 setOperationAction(ISD::CTLZ_ZERO_UNDEF, VT, Expand);
191 setOperationAction(ISD::ROTR, VT, Expand);
193 // Use *MUL_LOHI where possible instead of MULH*.
194 setOperationAction(ISD::MULHS, VT, Expand);
195 setOperationAction(ISD::MULHU, VT, Expand);
196 setOperationAction(ISD::SMUL_LOHI, VT, Custom);
197 setOperationAction(ISD::UMUL_LOHI, VT, Custom);
199 // Only z196 and above have native support for conversions to unsigned.
200 if (!Subtarget.hasFPExtension())
201 setOperationAction(ISD::FP_TO_UINT, VT, Expand);
205 // Type legalization will convert 8- and 16-bit atomic operations into
206 // forms that operate on i32s (but still keeping the original memory VT).
207 // Lower them into full i32 operations.
208 setOperationAction(ISD::ATOMIC_SWAP, MVT::i32, Custom);
209 setOperationAction(ISD::ATOMIC_LOAD_ADD, MVT::i32, Custom);
210 setOperationAction(ISD::ATOMIC_LOAD_SUB, MVT::i32, Custom);
211 setOperationAction(ISD::ATOMIC_LOAD_AND, MVT::i32, Custom);
212 setOperationAction(ISD::ATOMIC_LOAD_OR, MVT::i32, Custom);
213 setOperationAction(ISD::ATOMIC_LOAD_XOR, MVT::i32, Custom);
214 setOperationAction(ISD::ATOMIC_LOAD_NAND, MVT::i32, Custom);
215 setOperationAction(ISD::ATOMIC_LOAD_MIN, MVT::i32, Custom);
216 setOperationAction(ISD::ATOMIC_LOAD_MAX, MVT::i32, Custom);
217 setOperationAction(ISD::ATOMIC_LOAD_UMIN, MVT::i32, Custom);
218 setOperationAction(ISD::ATOMIC_LOAD_UMAX, MVT::i32, Custom);
219 setOperationAction(ISD::ATOMIC_CMP_SWAP, MVT::i32, Custom);
221 // z10 has instructions for signed but not unsigned FP conversion.
222 // Handle unsigned 32-bit types as signed 64-bit types.
223 if (!Subtarget.hasFPExtension()) {
224 setOperationAction(ISD::UINT_TO_FP, MVT::i32, Promote);
225 setOperationAction(ISD::UINT_TO_FP, MVT::i64, Expand);
228 // We have native support for a 64-bit CTLZ, via FLOGR.
229 setOperationAction(ISD::CTLZ, MVT::i32, Promote);
230 setOperationAction(ISD::CTLZ, MVT::i64, Legal);
232 // Give LowerOperation the chance to replace 64-bit ORs with subregs.
233 setOperationAction(ISD::OR, MVT::i64, Custom);
235 // FIXME: Can we support these natively?
236 setOperationAction(ISD::SRL_PARTS, MVT::i64, Expand);
237 setOperationAction(ISD::SHL_PARTS, MVT::i64, Expand);
238 setOperationAction(ISD::SRA_PARTS, MVT::i64, Expand);
240 // We have native instructions for i8, i16 and i32 extensions, but not i1.
241 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand);
242 for (MVT VT : MVT::integer_valuetypes()) {
243 setLoadExtAction(ISD::SEXTLOAD, VT, MVT::i1, Promote);
244 setLoadExtAction(ISD::ZEXTLOAD, VT, MVT::i1, Promote);
245 setLoadExtAction(ISD::EXTLOAD, VT, MVT::i1, Promote);
248 // Handle the various types of symbolic address.
249 setOperationAction(ISD::ConstantPool, PtrVT, Custom);
250 setOperationAction(ISD::GlobalAddress, PtrVT, Custom);
251 setOperationAction(ISD::GlobalTLSAddress, PtrVT, Custom);
252 setOperationAction(ISD::BlockAddress, PtrVT, Custom);
253 setOperationAction(ISD::JumpTable, PtrVT, Custom);
255 // We need to handle dynamic allocations specially because of the
256 // 160-byte area at the bottom of the stack.
257 setOperationAction(ISD::DYNAMIC_STACKALLOC, PtrVT, Custom);
259 // Use custom expanders so that we can force the function to use
261 setOperationAction(ISD::STACKSAVE, MVT::Other, Custom);
262 setOperationAction(ISD::STACKRESTORE, MVT::Other, Custom);
264 // Handle prefetches with PFD or PFDRL.
265 setOperationAction(ISD::PREFETCH, MVT::Other, Custom);
267 for (MVT VT : MVT::vector_valuetypes()) {
268 // Assume by default that all vector operations need to be expanded.
269 for (unsigned Opcode = 0; Opcode < ISD::BUILTIN_OP_END; ++Opcode)
270 if (getOperationAction(Opcode, VT) == Legal)
271 setOperationAction(Opcode, VT, Expand);
273 // Likewise all truncating stores and extending loads.
274 for (MVT InnerVT : MVT::vector_valuetypes()) {
275 setTruncStoreAction(VT, InnerVT, Expand);
276 setLoadExtAction(ISD::SEXTLOAD, VT, InnerVT, Expand);
277 setLoadExtAction(ISD::ZEXTLOAD, VT, InnerVT, Expand);
278 setLoadExtAction(ISD::EXTLOAD, VT, InnerVT, Expand);
281 if (isTypeLegal(VT)) {
282 // These operations are legal for anything that can be stored in a
283 // vector register, even if there is no native support for the format
284 // as such. In particular, we can do these for v4f32 even though there
285 // are no specific instructions for that format.
286 setOperationAction(ISD::LOAD, VT, Legal);
287 setOperationAction(ISD::STORE, VT, Legal);
288 setOperationAction(ISD::VSELECT, VT, Legal);
289 setOperationAction(ISD::BITCAST, VT, Legal);
290 setOperationAction(ISD::UNDEF, VT, Legal);
292 // Likewise, except that we need to replace the nodes with something
294 setOperationAction(ISD::BUILD_VECTOR, VT, Custom);
295 setOperationAction(ISD::VECTOR_SHUFFLE, VT, Custom);
299 // Handle integer vector types.
300 for (MVT VT : MVT::integer_vector_valuetypes()) {
301 if (isTypeLegal(VT)) {
302 // These operations have direct equivalents.
303 setOperationAction(ISD::EXTRACT_VECTOR_ELT, VT, Legal);
304 setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Legal);
305 setOperationAction(ISD::ADD, VT, Legal);
306 setOperationAction(ISD::SUB, VT, Legal);
307 if (VT != MVT::v2i64)
308 setOperationAction(ISD::MUL, VT, Legal);
309 setOperationAction(ISD::AND, VT, Legal);
310 setOperationAction(ISD::OR, VT, Legal);
311 setOperationAction(ISD::XOR, VT, Legal);
312 setOperationAction(ISD::CTPOP, VT, Custom);
313 setOperationAction(ISD::CTTZ, VT, Legal);
314 setOperationAction(ISD::CTLZ, VT, Legal);
315 setOperationAction(ISD::CTTZ_ZERO_UNDEF, VT, Custom);
316 setOperationAction(ISD::CTLZ_ZERO_UNDEF, VT, Custom);
318 // Convert a GPR scalar to a vector by inserting it into element 0.
319 setOperationAction(ISD::SCALAR_TO_VECTOR, VT, Custom);
321 // Use a series of unpacks for extensions.
322 setOperationAction(ISD::SIGN_EXTEND_VECTOR_INREG, VT, Custom);
323 setOperationAction(ISD::ZERO_EXTEND_VECTOR_INREG, VT, Custom);
325 // Detect shifts by a scalar amount and convert them into
327 setOperationAction(ISD::SHL, VT, Custom);
328 setOperationAction(ISD::SRA, VT, Custom);
329 setOperationAction(ISD::SRL, VT, Custom);
331 // At present ROTL isn't matched by DAGCombiner. ROTR should be
332 // converted into ROTL.
333 setOperationAction(ISD::ROTL, VT, Expand);
334 setOperationAction(ISD::ROTR, VT, Expand);
336 // Map SETCCs onto one of VCE, VCH or VCHL, swapping the operands
337 // and inverting the result as necessary.
338 setOperationAction(ISD::SETCC, VT, Custom);
342 if (Subtarget.hasVector()) {
343 // There should be no need to check for float types other than v2f64
344 // since <2 x f32> isn't a legal type.
345 setOperationAction(ISD::FP_TO_SINT, MVT::v2i64, Legal);
346 setOperationAction(ISD::FP_TO_UINT, MVT::v2i64, Legal);
347 setOperationAction(ISD::SINT_TO_FP, MVT::v2i64, Legal);
348 setOperationAction(ISD::UINT_TO_FP, MVT::v2i64, Legal);
351 // Handle floating-point types.
352 for (unsigned I = MVT::FIRST_FP_VALUETYPE;
353 I <= MVT::LAST_FP_VALUETYPE;
355 MVT VT = MVT::SimpleValueType(I);
356 if (isTypeLegal(VT)) {
357 // We can use FI for FRINT.
358 setOperationAction(ISD::FRINT, VT, Legal);
360 // We can use the extended form of FI for other rounding operations.
361 if (Subtarget.hasFPExtension()) {
362 setOperationAction(ISD::FNEARBYINT, VT, Legal);
363 setOperationAction(ISD::FFLOOR, VT, Legal);
364 setOperationAction(ISD::FCEIL, VT, Legal);
365 setOperationAction(ISD::FTRUNC, VT, Legal);
366 setOperationAction(ISD::FROUND, VT, Legal);
369 // No special instructions for these.
370 setOperationAction(ISD::FSIN, VT, Expand);
371 setOperationAction(ISD::FCOS, VT, Expand);
372 setOperationAction(ISD::FSINCOS, VT, Expand);
373 setOperationAction(ISD::FREM, VT, Expand);
374 setOperationAction(ISD::FPOW, VT, Expand);
378 // Handle floating-point vector types.
379 if (Subtarget.hasVector()) {
380 // Scalar-to-vector conversion is just a subreg.
381 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v4f32, Legal);
382 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v2f64, Legal);
384 // Some insertions and extractions can be done directly but others
385 // need to go via integers.
386 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4f32, Custom);
387 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v2f64, Custom);
388 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4f32, Custom);
389 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v2f64, Custom);
391 // These operations have direct equivalents.
392 setOperationAction(ISD::FADD, MVT::v2f64, Legal);
393 setOperationAction(ISD::FNEG, MVT::v2f64, Legal);
394 setOperationAction(ISD::FSUB, MVT::v2f64, Legal);
395 setOperationAction(ISD::FMUL, MVT::v2f64, Legal);
396 setOperationAction(ISD::FMA, MVT::v2f64, Legal);
397 setOperationAction(ISD::FDIV, MVT::v2f64, Legal);
398 setOperationAction(ISD::FABS, MVT::v2f64, Legal);
399 setOperationAction(ISD::FSQRT, MVT::v2f64, Legal);
400 setOperationAction(ISD::FRINT, MVT::v2f64, Legal);
401 setOperationAction(ISD::FNEARBYINT, MVT::v2f64, Legal);
402 setOperationAction(ISD::FFLOOR, MVT::v2f64, Legal);
403 setOperationAction(ISD::FCEIL, MVT::v2f64, Legal);
404 setOperationAction(ISD::FTRUNC, MVT::v2f64, Legal);
405 setOperationAction(ISD::FROUND, MVT::v2f64, Legal);
408 // We have fused multiply-addition for f32 and f64 but not f128.
409 setOperationAction(ISD::FMA, MVT::f32, Legal);
410 setOperationAction(ISD::FMA, MVT::f64, Legal);
411 setOperationAction(ISD::FMA, MVT::f128, Expand);
413 // Needed so that we don't try to implement f128 constant loads using
414 // a load-and-extend of a f80 constant (in cases where the constant
415 // would fit in an f80).
416 for (MVT VT : MVT::fp_valuetypes())
417 setLoadExtAction(ISD::EXTLOAD, VT, MVT::f80, Expand);
419 // Floating-point truncation and stores need to be done separately.
420 setTruncStoreAction(MVT::f64, MVT::f32, Expand);
421 setTruncStoreAction(MVT::f128, MVT::f32, Expand);
422 setTruncStoreAction(MVT::f128, MVT::f64, Expand);
424 // We have 64-bit FPR<->GPR moves, but need special handling for
426 if (!Subtarget.hasVector()) {
427 setOperationAction(ISD::BITCAST, MVT::i32, Custom);
428 setOperationAction(ISD::BITCAST, MVT::f32, Custom);
431 // VASTART and VACOPY need to deal with the SystemZ-specific varargs
432 // structure, but VAEND is a no-op.
433 setOperationAction(ISD::VASTART, MVT::Other, Custom);
434 setOperationAction(ISD::VACOPY, MVT::Other, Custom);
435 setOperationAction(ISD::VAEND, MVT::Other, Expand);
437 // Codes for which we want to perform some z-specific combinations.
438 setTargetDAGCombine(ISD::SIGN_EXTEND);
439 setTargetDAGCombine(ISD::STORE);
440 setTargetDAGCombine(ISD::EXTRACT_VECTOR_ELT);
441 setTargetDAGCombine(ISD::FP_ROUND);
443 // Handle intrinsics.
444 setOperationAction(ISD::INTRINSIC_W_CHAIN, MVT::Other, Custom);
445 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom);
447 // We want to use MVC in preference to even a single load/store pair.
448 MaxStoresPerMemcpy = 0;
449 MaxStoresPerMemcpyOptSize = 0;
451 // The main memset sequence is a byte store followed by an MVC.
452 // Two STC or MV..I stores win over that, but the kind of fused stores
453 // generated by target-independent code don't when the byte value is
454 // variable. E.g. "STC <reg>;MHI <reg>,257;STH <reg>" is not better
455 // than "STC;MVC". Handle the choice in target-specific code instead.
456 MaxStoresPerMemset = 0;
457 MaxStoresPerMemsetOptSize = 0;
460 EVT SystemZTargetLowering::getSetCCResultType(const DataLayout &DL,
461 LLVMContext &, EVT VT) const {
464 return VT.changeVectorElementTypeToInteger();
467 bool SystemZTargetLowering::isFMAFasterThanFMulAndFAdd(EVT VT) const {
468 VT = VT.getScalarType();
473 switch (VT.getSimpleVT().SimpleTy) {
486 bool SystemZTargetLowering::isFPImmLegal(const APFloat &Imm, EVT VT) const {
487 // We can load zero using LZ?R and negative zero using LZ?R;LC?BR.
488 return Imm.isZero() || Imm.isNegZero();
491 bool SystemZTargetLowering::isLegalICmpImmediate(int64_t Imm) const {
492 // We can use CGFI or CLGFI.
493 return isInt<32>(Imm) || isUInt<32>(Imm);
496 bool SystemZTargetLowering::isLegalAddImmediate(int64_t Imm) const {
497 // We can use ALGFI or SLGFI.
498 return isUInt<32>(Imm) || isUInt<32>(-Imm);
501 bool SystemZTargetLowering::allowsMisalignedMemoryAccesses(EVT VT,
505 // Unaligned accesses should never be slower than the expanded version.
506 // We check specifically for aligned accesses in the few cases where
507 // they are required.
513 bool SystemZTargetLowering::isLegalAddressingMode(const DataLayout &DL,
514 const AddrMode &AM, Type *Ty,
516 // Punt on globals for now, although they can be used in limited
517 // RELATIVE LONG cases.
521 // Require a 20-bit signed offset.
522 if (!isInt<20>(AM.BaseOffs))
525 // Indexing is OK but no scale factor can be applied.
526 return AM.Scale == 0 || AM.Scale == 1;
529 bool SystemZTargetLowering::isTruncateFree(Type *FromType, Type *ToType) const {
530 if (!FromType->isIntegerTy() || !ToType->isIntegerTy())
532 unsigned FromBits = FromType->getPrimitiveSizeInBits();
533 unsigned ToBits = ToType->getPrimitiveSizeInBits();
534 return FromBits > ToBits;
537 bool SystemZTargetLowering::isTruncateFree(EVT FromVT, EVT ToVT) const {
538 if (!FromVT.isInteger() || !ToVT.isInteger())
540 unsigned FromBits = FromVT.getSizeInBits();
541 unsigned ToBits = ToVT.getSizeInBits();
542 return FromBits > ToBits;
545 //===----------------------------------------------------------------------===//
546 // Inline asm support
547 //===----------------------------------------------------------------------===//
549 TargetLowering::ConstraintType
550 SystemZTargetLowering::getConstraintType(StringRef Constraint) const {
551 if (Constraint.size() == 1) {
552 switch (Constraint[0]) {
553 case 'a': // Address register
554 case 'd': // Data register (equivalent to 'r')
555 case 'f': // Floating-point register
556 case 'h': // High-part register
557 case 'r': // General-purpose register
558 return C_RegisterClass;
560 case 'Q': // Memory with base and unsigned 12-bit displacement
561 case 'R': // Likewise, plus an index
562 case 'S': // Memory with base and signed 20-bit displacement
563 case 'T': // Likewise, plus an index
564 case 'm': // Equivalent to 'T'.
567 case 'I': // Unsigned 8-bit constant
568 case 'J': // Unsigned 12-bit constant
569 case 'K': // Signed 16-bit constant
570 case 'L': // Signed 20-bit displacement (on all targets we support)
571 case 'M': // 0x7fffffff
578 return TargetLowering::getConstraintType(Constraint);
581 TargetLowering::ConstraintWeight SystemZTargetLowering::
582 getSingleConstraintMatchWeight(AsmOperandInfo &info,
583 const char *constraint) const {
584 ConstraintWeight weight = CW_Invalid;
585 Value *CallOperandVal = info.CallOperandVal;
586 // If we don't have a value, we can't do a match,
587 // but allow it at the lowest weight.
590 Type *type = CallOperandVal->getType();
591 // Look at the constraint type.
592 switch (*constraint) {
594 weight = TargetLowering::getSingleConstraintMatchWeight(info, constraint);
597 case 'a': // Address register
598 case 'd': // Data register (equivalent to 'r')
599 case 'h': // High-part register
600 case 'r': // General-purpose register
601 if (CallOperandVal->getType()->isIntegerTy())
602 weight = CW_Register;
605 case 'f': // Floating-point register
606 if (type->isFloatingPointTy())
607 weight = CW_Register;
610 case 'I': // Unsigned 8-bit constant
611 if (auto *C = dyn_cast<ConstantInt>(CallOperandVal))
612 if (isUInt<8>(C->getZExtValue()))
613 weight = CW_Constant;
616 case 'J': // Unsigned 12-bit constant
617 if (auto *C = dyn_cast<ConstantInt>(CallOperandVal))
618 if (isUInt<12>(C->getZExtValue()))
619 weight = CW_Constant;
622 case 'K': // Signed 16-bit constant
623 if (auto *C = dyn_cast<ConstantInt>(CallOperandVal))
624 if (isInt<16>(C->getSExtValue()))
625 weight = CW_Constant;
628 case 'L': // Signed 20-bit displacement (on all targets we support)
629 if (auto *C = dyn_cast<ConstantInt>(CallOperandVal))
630 if (isInt<20>(C->getSExtValue()))
631 weight = CW_Constant;
634 case 'M': // 0x7fffffff
635 if (auto *C = dyn_cast<ConstantInt>(CallOperandVal))
636 if (C->getZExtValue() == 0x7fffffff)
637 weight = CW_Constant;
643 // Parse a "{tNNN}" register constraint for which the register type "t"
644 // has already been verified. MC is the class associated with "t" and
645 // Map maps 0-based register numbers to LLVM register numbers.
646 static std::pair<unsigned, const TargetRegisterClass *>
647 parseRegisterNumber(StringRef Constraint, const TargetRegisterClass *RC,
648 const unsigned *Map) {
649 assert(*(Constraint.end()-1) == '}' && "Missing '}'");
650 if (isdigit(Constraint[2])) {
653 Constraint.slice(2, Constraint.size() - 1).getAsInteger(10, Index);
654 if (!Failed && Index < 16 && Map[Index])
655 return std::make_pair(Map[Index], RC);
657 return std::make_pair(0U, nullptr);
660 std::pair<unsigned, const TargetRegisterClass *>
661 SystemZTargetLowering::getRegForInlineAsmConstraint(
662 const TargetRegisterInfo *TRI, StringRef Constraint, MVT VT) const {
663 if (Constraint.size() == 1) {
664 // GCC Constraint Letters
665 switch (Constraint[0]) {
667 case 'd': // Data register (equivalent to 'r')
668 case 'r': // General-purpose register
670 return std::make_pair(0U, &SystemZ::GR64BitRegClass);
671 else if (VT == MVT::i128)
672 return std::make_pair(0U, &SystemZ::GR128BitRegClass);
673 return std::make_pair(0U, &SystemZ::GR32BitRegClass);
675 case 'a': // Address register
677 return std::make_pair(0U, &SystemZ::ADDR64BitRegClass);
678 else if (VT == MVT::i128)
679 return std::make_pair(0U, &SystemZ::ADDR128BitRegClass);
680 return std::make_pair(0U, &SystemZ::ADDR32BitRegClass);
682 case 'h': // High-part register (an LLVM extension)
683 return std::make_pair(0U, &SystemZ::GRH32BitRegClass);
685 case 'f': // Floating-point register
687 return std::make_pair(0U, &SystemZ::FP64BitRegClass);
688 else if (VT == MVT::f128)
689 return std::make_pair(0U, &SystemZ::FP128BitRegClass);
690 return std::make_pair(0U, &SystemZ::FP32BitRegClass);
693 if (Constraint.size() > 0 && Constraint[0] == '{') {
694 // We need to override the default register parsing for GPRs and FPRs
695 // because the interpretation depends on VT. The internal names of
696 // the registers are also different from the external names
697 // (F0D and F0S instead of F0, etc.).
698 if (Constraint[1] == 'r') {
700 return parseRegisterNumber(Constraint, &SystemZ::GR32BitRegClass,
701 SystemZMC::GR32Regs);
703 return parseRegisterNumber(Constraint, &SystemZ::GR128BitRegClass,
704 SystemZMC::GR128Regs);
705 return parseRegisterNumber(Constraint, &SystemZ::GR64BitRegClass,
706 SystemZMC::GR64Regs);
708 if (Constraint[1] == 'f') {
710 return parseRegisterNumber(Constraint, &SystemZ::FP32BitRegClass,
711 SystemZMC::FP32Regs);
713 return parseRegisterNumber(Constraint, &SystemZ::FP128BitRegClass,
714 SystemZMC::FP128Regs);
715 return parseRegisterNumber(Constraint, &SystemZ::FP64BitRegClass,
716 SystemZMC::FP64Regs);
719 return TargetLowering::getRegForInlineAsmConstraint(TRI, Constraint, VT);
722 void SystemZTargetLowering::
723 LowerAsmOperandForConstraint(SDValue Op, std::string &Constraint,
724 std::vector<SDValue> &Ops,
725 SelectionDAG &DAG) const {
726 // Only support length 1 constraints for now.
727 if (Constraint.length() == 1) {
728 switch (Constraint[0]) {
729 case 'I': // Unsigned 8-bit constant
730 if (auto *C = dyn_cast<ConstantSDNode>(Op))
731 if (isUInt<8>(C->getZExtValue()))
732 Ops.push_back(DAG.getTargetConstant(C->getZExtValue(), SDLoc(Op),
736 case 'J': // Unsigned 12-bit constant
737 if (auto *C = dyn_cast<ConstantSDNode>(Op))
738 if (isUInt<12>(C->getZExtValue()))
739 Ops.push_back(DAG.getTargetConstant(C->getZExtValue(), SDLoc(Op),
743 case 'K': // Signed 16-bit constant
744 if (auto *C = dyn_cast<ConstantSDNode>(Op))
745 if (isInt<16>(C->getSExtValue()))
746 Ops.push_back(DAG.getTargetConstant(C->getSExtValue(), SDLoc(Op),
750 case 'L': // Signed 20-bit displacement (on all targets we support)
751 if (auto *C = dyn_cast<ConstantSDNode>(Op))
752 if (isInt<20>(C->getSExtValue()))
753 Ops.push_back(DAG.getTargetConstant(C->getSExtValue(), SDLoc(Op),
757 case 'M': // 0x7fffffff
758 if (auto *C = dyn_cast<ConstantSDNode>(Op))
759 if (C->getZExtValue() == 0x7fffffff)
760 Ops.push_back(DAG.getTargetConstant(C->getZExtValue(), SDLoc(Op),
765 TargetLowering::LowerAsmOperandForConstraint(Op, Constraint, Ops, DAG);
768 //===----------------------------------------------------------------------===//
769 // Calling conventions
770 //===----------------------------------------------------------------------===//
772 #include "SystemZGenCallingConv.inc"
774 bool SystemZTargetLowering::allowTruncateForTailCall(Type *FromType,
775 Type *ToType) const {
776 return isTruncateFree(FromType, ToType);
779 bool SystemZTargetLowering::mayBeEmittedAsTailCall(CallInst *CI) const {
780 if (!CI->isTailCall())
785 // We do not yet support 128-bit single-element vector types. If the user
786 // attempts to use such types as function argument or return type, prefer
787 // to error out instead of emitting code violating the ABI.
788 static void VerifyVectorType(MVT VT, EVT ArgVT) {
789 if (ArgVT.isVector() && !VT.isVector())
790 report_fatal_error("Unsupported vector argument or return type");
793 static void VerifyVectorTypes(const SmallVectorImpl<ISD::InputArg> &Ins) {
794 for (unsigned i = 0; i < Ins.size(); ++i)
795 VerifyVectorType(Ins[i].VT, Ins[i].ArgVT);
798 static void VerifyVectorTypes(const SmallVectorImpl<ISD::OutputArg> &Outs) {
799 for (unsigned i = 0; i < Outs.size(); ++i)
800 VerifyVectorType(Outs[i].VT, Outs[i].ArgVT);
803 // Value is a value that has been passed to us in the location described by VA
804 // (and so has type VA.getLocVT()). Convert Value to VA.getValVT(), chaining
805 // any loads onto Chain.
806 static SDValue convertLocVTToValVT(SelectionDAG &DAG, SDLoc DL,
807 CCValAssign &VA, SDValue Chain,
809 // If the argument has been promoted from a smaller type, insert an
810 // assertion to capture this.
811 if (VA.getLocInfo() == CCValAssign::SExt)
812 Value = DAG.getNode(ISD::AssertSext, DL, VA.getLocVT(), Value,
813 DAG.getValueType(VA.getValVT()));
814 else if (VA.getLocInfo() == CCValAssign::ZExt)
815 Value = DAG.getNode(ISD::AssertZext, DL, VA.getLocVT(), Value,
816 DAG.getValueType(VA.getValVT()));
819 Value = DAG.getNode(ISD::TRUNCATE, DL, VA.getValVT(), Value);
820 else if (VA.getLocInfo() == CCValAssign::Indirect)
821 Value = DAG.getLoad(VA.getValVT(), DL, Chain, Value,
822 MachinePointerInfo(), false, false, false, 0);
823 else if (VA.getLocInfo() == CCValAssign::BCvt) {
824 // If this is a short vector argument loaded from the stack,
825 // extend from i64 to full vector size and then bitcast.
826 assert(VA.getLocVT() == MVT::i64);
827 assert(VA.getValVT().isVector());
828 Value = DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v2i64,
829 Value, DAG.getUNDEF(MVT::i64));
830 Value = DAG.getNode(ISD::BITCAST, DL, VA.getValVT(), Value);
832 assert(VA.getLocInfo() == CCValAssign::Full && "Unsupported getLocInfo");
836 // Value is a value of type VA.getValVT() that we need to copy into
837 // the location described by VA. Return a copy of Value converted to
838 // VA.getValVT(). The caller is responsible for handling indirect values.
839 static SDValue convertValVTToLocVT(SelectionDAG &DAG, SDLoc DL,
840 CCValAssign &VA, SDValue Value) {
841 switch (VA.getLocInfo()) {
842 case CCValAssign::SExt:
843 return DAG.getNode(ISD::SIGN_EXTEND, DL, VA.getLocVT(), Value);
844 case CCValAssign::ZExt:
845 return DAG.getNode(ISD::ZERO_EXTEND, DL, VA.getLocVT(), Value);
846 case CCValAssign::AExt:
847 return DAG.getNode(ISD::ANY_EXTEND, DL, VA.getLocVT(), Value);
848 case CCValAssign::BCvt:
849 // If this is a short vector argument to be stored to the stack,
850 // bitcast to v2i64 and then extract first element.
851 assert(VA.getLocVT() == MVT::i64);
852 assert(VA.getValVT().isVector());
853 Value = DAG.getNode(ISD::BITCAST, DL, MVT::v2i64, Value);
854 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, VA.getLocVT(), Value,
855 DAG.getConstant(0, DL, MVT::i32));
856 case CCValAssign::Full:
859 llvm_unreachable("Unhandled getLocInfo()");
863 SDValue SystemZTargetLowering::
864 LowerFormalArguments(SDValue Chain, CallingConv::ID CallConv, bool IsVarArg,
865 const SmallVectorImpl<ISD::InputArg> &Ins,
866 SDLoc DL, SelectionDAG &DAG,
867 SmallVectorImpl<SDValue> &InVals) const {
868 MachineFunction &MF = DAG.getMachineFunction();
869 MachineFrameInfo *MFI = MF.getFrameInfo();
870 MachineRegisterInfo &MRI = MF.getRegInfo();
871 SystemZMachineFunctionInfo *FuncInfo =
872 MF.getInfo<SystemZMachineFunctionInfo>();
874 static_cast<const SystemZFrameLowering *>(Subtarget.getFrameLowering());
876 // Detect unsupported vector argument types.
877 if (Subtarget.hasVector())
878 VerifyVectorTypes(Ins);
880 // Assign locations to all of the incoming arguments.
881 SmallVector<CCValAssign, 16> ArgLocs;
882 SystemZCCState CCInfo(CallConv, IsVarArg, MF, ArgLocs, *DAG.getContext());
883 CCInfo.AnalyzeFormalArguments(Ins, CC_SystemZ);
885 unsigned NumFixedGPRs = 0;
886 unsigned NumFixedFPRs = 0;
887 for (unsigned I = 0, E = ArgLocs.size(); I != E; ++I) {
889 CCValAssign &VA = ArgLocs[I];
890 EVT LocVT = VA.getLocVT();
892 // Arguments passed in registers
893 const TargetRegisterClass *RC;
894 switch (LocVT.getSimpleVT().SimpleTy) {
896 // Integers smaller than i64 should be promoted to i64.
897 llvm_unreachable("Unexpected argument type");
900 RC = &SystemZ::GR32BitRegClass;
904 RC = &SystemZ::GR64BitRegClass;
908 RC = &SystemZ::FP32BitRegClass;
912 RC = &SystemZ::FP64BitRegClass;
920 RC = &SystemZ::VR128BitRegClass;
924 unsigned VReg = MRI.createVirtualRegister(RC);
925 MRI.addLiveIn(VA.getLocReg(), VReg);
926 ArgValue = DAG.getCopyFromReg(Chain, DL, VReg, LocVT);
928 assert(VA.isMemLoc() && "Argument not register or memory");
930 // Create the frame index object for this incoming parameter.
931 int FI = MFI->CreateFixedObject(LocVT.getSizeInBits() / 8,
932 VA.getLocMemOffset(), true);
934 // Create the SelectionDAG nodes corresponding to a load
935 // from this parameter. Unpromoted ints and floats are
936 // passed as right-justified 8-byte values.
937 EVT PtrVT = getPointerTy(DAG.getDataLayout());
938 SDValue FIN = DAG.getFrameIndex(FI, PtrVT);
939 if (VA.getLocVT() == MVT::i32 || VA.getLocVT() == MVT::f32)
940 FIN = DAG.getNode(ISD::ADD, DL, PtrVT, FIN,
941 DAG.getIntPtrConstant(4, DL));
942 ArgValue = DAG.getLoad(LocVT, DL, Chain, FIN,
943 MachinePointerInfo::getFixedStack(MF, FI), false,
947 // Convert the value of the argument register into the value that's
949 InVals.push_back(convertLocVTToValVT(DAG, DL, VA, Chain, ArgValue));
953 // Save the number of non-varargs registers for later use by va_start, etc.
954 FuncInfo->setVarArgsFirstGPR(NumFixedGPRs);
955 FuncInfo->setVarArgsFirstFPR(NumFixedFPRs);
957 // Likewise the address (in the form of a frame index) of where the
958 // first stack vararg would be. The 1-byte size here is arbitrary.
959 int64_t StackSize = CCInfo.getNextStackOffset();
960 FuncInfo->setVarArgsFrameIndex(MFI->CreateFixedObject(1, StackSize, true));
962 // ...and a similar frame index for the caller-allocated save area
963 // that will be used to store the incoming registers.
964 int64_t RegSaveOffset = TFL->getOffsetOfLocalArea();
965 unsigned RegSaveIndex = MFI->CreateFixedObject(1, RegSaveOffset, true);
966 FuncInfo->setRegSaveFrameIndex(RegSaveIndex);
968 // Store the FPR varargs in the reserved frame slots. (We store the
969 // GPRs as part of the prologue.)
970 if (NumFixedFPRs < SystemZ::NumArgFPRs) {
971 SDValue MemOps[SystemZ::NumArgFPRs];
972 for (unsigned I = NumFixedFPRs; I < SystemZ::NumArgFPRs; ++I) {
973 unsigned Offset = TFL->getRegSpillOffset(SystemZ::ArgFPRs[I]);
974 int FI = MFI->CreateFixedObject(8, RegSaveOffset + Offset, true);
975 SDValue FIN = DAG.getFrameIndex(FI, getPointerTy(DAG.getDataLayout()));
976 unsigned VReg = MF.addLiveIn(SystemZ::ArgFPRs[I],
977 &SystemZ::FP64BitRegClass);
978 SDValue ArgValue = DAG.getCopyFromReg(Chain, DL, VReg, MVT::f64);
979 MemOps[I] = DAG.getStore(ArgValue.getValue(1), DL, ArgValue, FIN,
980 MachinePointerInfo::getFixedStack(MF, FI),
983 // Join the stores, which are independent of one another.
984 Chain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other,
985 makeArrayRef(&MemOps[NumFixedFPRs],
986 SystemZ::NumArgFPRs-NumFixedFPRs));
993 static bool canUseSiblingCall(const CCState &ArgCCInfo,
994 SmallVectorImpl<CCValAssign> &ArgLocs) {
995 // Punt if there are any indirect or stack arguments, or if the call
996 // needs the call-saved argument register R6.
997 for (unsigned I = 0, E = ArgLocs.size(); I != E; ++I) {
998 CCValAssign &VA = ArgLocs[I];
999 if (VA.getLocInfo() == CCValAssign::Indirect)
1003 unsigned Reg = VA.getLocReg();
1004 if (Reg == SystemZ::R6H || Reg == SystemZ::R6L || Reg == SystemZ::R6D)
1011 SystemZTargetLowering::LowerCall(CallLoweringInfo &CLI,
1012 SmallVectorImpl<SDValue> &InVals) const {
1013 SelectionDAG &DAG = CLI.DAG;
1015 SmallVectorImpl<ISD::OutputArg> &Outs = CLI.Outs;
1016 SmallVectorImpl<SDValue> &OutVals = CLI.OutVals;
1017 SmallVectorImpl<ISD::InputArg> &Ins = CLI.Ins;
1018 SDValue Chain = CLI.Chain;
1019 SDValue Callee = CLI.Callee;
1020 bool &IsTailCall = CLI.IsTailCall;
1021 CallingConv::ID CallConv = CLI.CallConv;
1022 bool IsVarArg = CLI.IsVarArg;
1023 MachineFunction &MF = DAG.getMachineFunction();
1024 EVT PtrVT = getPointerTy(MF.getDataLayout());
1026 // Detect unsupported vector argument and return types.
1027 if (Subtarget.hasVector()) {
1028 VerifyVectorTypes(Outs);
1029 VerifyVectorTypes(Ins);
1032 // Analyze the operands of the call, assigning locations to each operand.
1033 SmallVector<CCValAssign, 16> ArgLocs;
1034 SystemZCCState ArgCCInfo(CallConv, IsVarArg, MF, ArgLocs, *DAG.getContext());
1035 ArgCCInfo.AnalyzeCallOperands(Outs, CC_SystemZ);
1037 // We don't support GuaranteedTailCallOpt, only automatically-detected
1039 if (IsTailCall && !canUseSiblingCall(ArgCCInfo, ArgLocs))
1042 // Get a count of how many bytes are to be pushed on the stack.
1043 unsigned NumBytes = ArgCCInfo.getNextStackOffset();
1045 // Mark the start of the call.
1047 Chain = DAG.getCALLSEQ_START(Chain,
1048 DAG.getConstant(NumBytes, DL, PtrVT, true),
1051 // Copy argument values to their designated locations.
1052 SmallVector<std::pair<unsigned, SDValue>, 9> RegsToPass;
1053 SmallVector<SDValue, 8> MemOpChains;
1055 for (unsigned I = 0, E = ArgLocs.size(); I != E; ++I) {
1056 CCValAssign &VA = ArgLocs[I];
1057 SDValue ArgValue = OutVals[I];
1059 if (VA.getLocInfo() == CCValAssign::Indirect) {
1060 // Store the argument in a stack slot and pass its address.
1061 SDValue SpillSlot = DAG.CreateStackTemporary(VA.getValVT());
1062 int FI = cast<FrameIndexSDNode>(SpillSlot)->getIndex();
1063 MemOpChains.push_back(DAG.getStore(
1064 Chain, DL, ArgValue, SpillSlot,
1065 MachinePointerInfo::getFixedStack(MF, FI), false, false, 0));
1066 ArgValue = SpillSlot;
1068 ArgValue = convertValVTToLocVT(DAG, DL, VA, ArgValue);
1071 // Queue up the argument copies and emit them at the end.
1072 RegsToPass.push_back(std::make_pair(VA.getLocReg(), ArgValue));
1074 assert(VA.isMemLoc() && "Argument not register or memory");
1076 // Work out the address of the stack slot. Unpromoted ints and
1077 // floats are passed as right-justified 8-byte values.
1078 if (!StackPtr.getNode())
1079 StackPtr = DAG.getCopyFromReg(Chain, DL, SystemZ::R15D, PtrVT);
1080 unsigned Offset = SystemZMC::CallFrameSize + VA.getLocMemOffset();
1081 if (VA.getLocVT() == MVT::i32 || VA.getLocVT() == MVT::f32)
1083 SDValue Address = DAG.getNode(ISD::ADD, DL, PtrVT, StackPtr,
1084 DAG.getIntPtrConstant(Offset, DL));
1087 MemOpChains.push_back(DAG.getStore(Chain, DL, ArgValue, Address,
1088 MachinePointerInfo(),
1093 // Join the stores, which are independent of one another.
1094 if (!MemOpChains.empty())
1095 Chain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other, MemOpChains);
1097 // Accept direct calls by converting symbolic call addresses to the
1098 // associated Target* opcodes. Force %r1 to be used for indirect
1101 if (auto *G = dyn_cast<GlobalAddressSDNode>(Callee)) {
1102 Callee = DAG.getTargetGlobalAddress(G->getGlobal(), DL, PtrVT);
1103 Callee = DAG.getNode(SystemZISD::PCREL_WRAPPER, DL, PtrVT, Callee);
1104 } else if (auto *E = dyn_cast<ExternalSymbolSDNode>(Callee)) {
1105 Callee = DAG.getTargetExternalSymbol(E->getSymbol(), PtrVT);
1106 Callee = DAG.getNode(SystemZISD::PCREL_WRAPPER, DL, PtrVT, Callee);
1107 } else if (IsTailCall) {
1108 Chain = DAG.getCopyToReg(Chain, DL, SystemZ::R1D, Callee, Glue);
1109 Glue = Chain.getValue(1);
1110 Callee = DAG.getRegister(SystemZ::R1D, Callee.getValueType());
1113 // Build a sequence of copy-to-reg nodes, chained and glued together.
1114 for (unsigned I = 0, E = RegsToPass.size(); I != E; ++I) {
1115 Chain = DAG.getCopyToReg(Chain, DL, RegsToPass[I].first,
1116 RegsToPass[I].second, Glue);
1117 Glue = Chain.getValue(1);
1120 // The first call operand is the chain and the second is the target address.
1121 SmallVector<SDValue, 8> Ops;
1122 Ops.push_back(Chain);
1123 Ops.push_back(Callee);
1125 // Add argument registers to the end of the list so that they are
1126 // known live into the call.
1127 for (unsigned I = 0, E = RegsToPass.size(); I != E; ++I)
1128 Ops.push_back(DAG.getRegister(RegsToPass[I].first,
1129 RegsToPass[I].second.getValueType()));
1131 // Add a register mask operand representing the call-preserved registers.
1132 const TargetRegisterInfo *TRI = Subtarget.getRegisterInfo();
1133 const uint32_t *Mask = TRI->getCallPreservedMask(MF, CallConv);
1134 assert(Mask && "Missing call preserved mask for calling convention");
1135 Ops.push_back(DAG.getRegisterMask(Mask));
1137 // Glue the call to the argument copies, if any.
1139 Ops.push_back(Glue);
1142 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
1144 return DAG.getNode(SystemZISD::SIBCALL, DL, NodeTys, Ops);
1145 Chain = DAG.getNode(SystemZISD::CALL, DL, NodeTys, Ops);
1146 Glue = Chain.getValue(1);
1148 // Mark the end of the call, which is glued to the call itself.
1149 Chain = DAG.getCALLSEQ_END(Chain,
1150 DAG.getConstant(NumBytes, DL, PtrVT, true),
1151 DAG.getConstant(0, DL, PtrVT, true),
1153 Glue = Chain.getValue(1);
1155 // Assign locations to each value returned by this call.
1156 SmallVector<CCValAssign, 16> RetLocs;
1157 CCState RetCCInfo(CallConv, IsVarArg, MF, RetLocs, *DAG.getContext());
1158 RetCCInfo.AnalyzeCallResult(Ins, RetCC_SystemZ);
1160 // Copy all of the result registers out of their specified physreg.
1161 for (unsigned I = 0, E = RetLocs.size(); I != E; ++I) {
1162 CCValAssign &VA = RetLocs[I];
1164 // Copy the value out, gluing the copy to the end of the call sequence.
1165 SDValue RetValue = DAG.getCopyFromReg(Chain, DL, VA.getLocReg(),
1166 VA.getLocVT(), Glue);
1167 Chain = RetValue.getValue(1);
1168 Glue = RetValue.getValue(2);
1170 // Convert the value of the return register into the value that's
1172 InVals.push_back(convertLocVTToValVT(DAG, DL, VA, Chain, RetValue));
1178 bool SystemZTargetLowering::
1179 CanLowerReturn(CallingConv::ID CallConv,
1180 MachineFunction &MF, bool isVarArg,
1181 const SmallVectorImpl<ISD::OutputArg> &Outs,
1182 LLVMContext &Context) const {
1183 // Detect unsupported vector return types.
1184 if (Subtarget.hasVector())
1185 VerifyVectorTypes(Outs);
1187 SmallVector<CCValAssign, 16> RetLocs;
1188 CCState RetCCInfo(CallConv, isVarArg, MF, RetLocs, Context);
1189 return RetCCInfo.CheckReturn(Outs, RetCC_SystemZ);
1193 SystemZTargetLowering::LowerReturn(SDValue Chain,
1194 CallingConv::ID CallConv, bool IsVarArg,
1195 const SmallVectorImpl<ISD::OutputArg> &Outs,
1196 const SmallVectorImpl<SDValue> &OutVals,
1197 SDLoc DL, SelectionDAG &DAG) const {
1198 MachineFunction &MF = DAG.getMachineFunction();
1200 // Detect unsupported vector return types.
1201 if (Subtarget.hasVector())
1202 VerifyVectorTypes(Outs);
1204 // Assign locations to each returned value.
1205 SmallVector<CCValAssign, 16> RetLocs;
1206 CCState RetCCInfo(CallConv, IsVarArg, MF, RetLocs, *DAG.getContext());
1207 RetCCInfo.AnalyzeReturn(Outs, RetCC_SystemZ);
1209 // Quick exit for void returns
1210 if (RetLocs.empty())
1211 return DAG.getNode(SystemZISD::RET_FLAG, DL, MVT::Other, Chain);
1213 // Copy the result values into the output registers.
1215 SmallVector<SDValue, 4> RetOps;
1216 RetOps.push_back(Chain);
1217 for (unsigned I = 0, E = RetLocs.size(); I != E; ++I) {
1218 CCValAssign &VA = RetLocs[I];
1219 SDValue RetValue = OutVals[I];
1221 // Make the return register live on exit.
1222 assert(VA.isRegLoc() && "Can only return in registers!");
1224 // Promote the value as required.
1225 RetValue = convertValVTToLocVT(DAG, DL, VA, RetValue);
1227 // Chain and glue the copies together.
1228 unsigned Reg = VA.getLocReg();
1229 Chain = DAG.getCopyToReg(Chain, DL, Reg, RetValue, Glue);
1230 Glue = Chain.getValue(1);
1231 RetOps.push_back(DAG.getRegister(Reg, VA.getLocVT()));
1234 // Update chain and glue.
1237 RetOps.push_back(Glue);
1239 return DAG.getNode(SystemZISD::RET_FLAG, DL, MVT::Other, RetOps);
1242 SDValue SystemZTargetLowering::
1243 prepareVolatileOrAtomicLoad(SDValue Chain, SDLoc DL, SelectionDAG &DAG) const {
1244 return DAG.getNode(SystemZISD::SERIALIZE, DL, MVT::Other, Chain);
1247 // Return true if Op is an intrinsic node with chain that returns the CC value
1248 // as its only (other) argument. Provide the associated SystemZISD opcode and
1249 // the mask of valid CC values if so.
1250 static bool isIntrinsicWithCCAndChain(SDValue Op, unsigned &Opcode,
1251 unsigned &CCValid) {
1252 unsigned Id = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
1254 case Intrinsic::s390_tbegin:
1255 Opcode = SystemZISD::TBEGIN;
1256 CCValid = SystemZ::CCMASK_TBEGIN;
1259 case Intrinsic::s390_tbegin_nofloat:
1260 Opcode = SystemZISD::TBEGIN_NOFLOAT;
1261 CCValid = SystemZ::CCMASK_TBEGIN;
1264 case Intrinsic::s390_tend:
1265 Opcode = SystemZISD::TEND;
1266 CCValid = SystemZ::CCMASK_TEND;
1274 // Return true if Op is an intrinsic node without chain that returns the
1275 // CC value as its final argument. Provide the associated SystemZISD
1276 // opcode and the mask of valid CC values if so.
1277 static bool isIntrinsicWithCC(SDValue Op, unsigned &Opcode, unsigned &CCValid) {
1278 unsigned Id = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
1280 case Intrinsic::s390_vpkshs:
1281 case Intrinsic::s390_vpksfs:
1282 case Intrinsic::s390_vpksgs:
1283 Opcode = SystemZISD::PACKS_CC;
1284 CCValid = SystemZ::CCMASK_VCMP;
1287 case Intrinsic::s390_vpklshs:
1288 case Intrinsic::s390_vpklsfs:
1289 case Intrinsic::s390_vpklsgs:
1290 Opcode = SystemZISD::PACKLS_CC;
1291 CCValid = SystemZ::CCMASK_VCMP;
1294 case Intrinsic::s390_vceqbs:
1295 case Intrinsic::s390_vceqhs:
1296 case Intrinsic::s390_vceqfs:
1297 case Intrinsic::s390_vceqgs:
1298 Opcode = SystemZISD::VICMPES;
1299 CCValid = SystemZ::CCMASK_VCMP;
1302 case Intrinsic::s390_vchbs:
1303 case Intrinsic::s390_vchhs:
1304 case Intrinsic::s390_vchfs:
1305 case Intrinsic::s390_vchgs:
1306 Opcode = SystemZISD::VICMPHS;
1307 CCValid = SystemZ::CCMASK_VCMP;
1310 case Intrinsic::s390_vchlbs:
1311 case Intrinsic::s390_vchlhs:
1312 case Intrinsic::s390_vchlfs:
1313 case Intrinsic::s390_vchlgs:
1314 Opcode = SystemZISD::VICMPHLS;
1315 CCValid = SystemZ::CCMASK_VCMP;
1318 case Intrinsic::s390_vtm:
1319 Opcode = SystemZISD::VTM;
1320 CCValid = SystemZ::CCMASK_VCMP;
1323 case Intrinsic::s390_vfaebs:
1324 case Intrinsic::s390_vfaehs:
1325 case Intrinsic::s390_vfaefs:
1326 Opcode = SystemZISD::VFAE_CC;
1327 CCValid = SystemZ::CCMASK_ANY;
1330 case Intrinsic::s390_vfaezbs:
1331 case Intrinsic::s390_vfaezhs:
1332 case Intrinsic::s390_vfaezfs:
1333 Opcode = SystemZISD::VFAEZ_CC;
1334 CCValid = SystemZ::CCMASK_ANY;
1337 case Intrinsic::s390_vfeebs:
1338 case Intrinsic::s390_vfeehs:
1339 case Intrinsic::s390_vfeefs:
1340 Opcode = SystemZISD::VFEE_CC;
1341 CCValid = SystemZ::CCMASK_ANY;
1344 case Intrinsic::s390_vfeezbs:
1345 case Intrinsic::s390_vfeezhs:
1346 case Intrinsic::s390_vfeezfs:
1347 Opcode = SystemZISD::VFEEZ_CC;
1348 CCValid = SystemZ::CCMASK_ANY;
1351 case Intrinsic::s390_vfenebs:
1352 case Intrinsic::s390_vfenehs:
1353 case Intrinsic::s390_vfenefs:
1354 Opcode = SystemZISD::VFENE_CC;
1355 CCValid = SystemZ::CCMASK_ANY;
1358 case Intrinsic::s390_vfenezbs:
1359 case Intrinsic::s390_vfenezhs:
1360 case Intrinsic::s390_vfenezfs:
1361 Opcode = SystemZISD::VFENEZ_CC;
1362 CCValid = SystemZ::CCMASK_ANY;
1365 case Intrinsic::s390_vistrbs:
1366 case Intrinsic::s390_vistrhs:
1367 case Intrinsic::s390_vistrfs:
1368 Opcode = SystemZISD::VISTR_CC;
1369 CCValid = SystemZ::CCMASK_0 | SystemZ::CCMASK_3;
1372 case Intrinsic::s390_vstrcbs:
1373 case Intrinsic::s390_vstrchs:
1374 case Intrinsic::s390_vstrcfs:
1375 Opcode = SystemZISD::VSTRC_CC;
1376 CCValid = SystemZ::CCMASK_ANY;
1379 case Intrinsic::s390_vstrczbs:
1380 case Intrinsic::s390_vstrczhs:
1381 case Intrinsic::s390_vstrczfs:
1382 Opcode = SystemZISD::VSTRCZ_CC;
1383 CCValid = SystemZ::CCMASK_ANY;
1386 case Intrinsic::s390_vfcedbs:
1387 Opcode = SystemZISD::VFCMPES;
1388 CCValid = SystemZ::CCMASK_VCMP;
1391 case Intrinsic::s390_vfchdbs:
1392 Opcode = SystemZISD::VFCMPHS;
1393 CCValid = SystemZ::CCMASK_VCMP;
1396 case Intrinsic::s390_vfchedbs:
1397 Opcode = SystemZISD::VFCMPHES;
1398 CCValid = SystemZ::CCMASK_VCMP;
1401 case Intrinsic::s390_vftcidb:
1402 Opcode = SystemZISD::VFTCI;
1403 CCValid = SystemZ::CCMASK_VCMP;
1411 // Emit an intrinsic with chain with a glued value instead of its CC result.
1412 static SDValue emitIntrinsicWithChainAndGlue(SelectionDAG &DAG, SDValue Op,
1414 // Copy all operands except the intrinsic ID.
1415 unsigned NumOps = Op.getNumOperands();
1416 SmallVector<SDValue, 6> Ops;
1417 Ops.reserve(NumOps - 1);
1418 Ops.push_back(Op.getOperand(0));
1419 for (unsigned I = 2; I < NumOps; ++I)
1420 Ops.push_back(Op.getOperand(I));
1422 assert(Op->getNumValues() == 2 && "Expected only CC result and chain");
1423 SDVTList RawVTs = DAG.getVTList(MVT::Other, MVT::Glue);
1424 SDValue Intr = DAG.getNode(Opcode, SDLoc(Op), RawVTs, Ops);
1425 SDValue OldChain = SDValue(Op.getNode(), 1);
1426 SDValue NewChain = SDValue(Intr.getNode(), 0);
1427 DAG.ReplaceAllUsesOfValueWith(OldChain, NewChain);
1431 // Emit an intrinsic with a glued value instead of its CC result.
1432 static SDValue emitIntrinsicWithGlue(SelectionDAG &DAG, SDValue Op,
1434 // Copy all operands except the intrinsic ID.
1435 unsigned NumOps = Op.getNumOperands();
1436 SmallVector<SDValue, 6> Ops;
1437 Ops.reserve(NumOps - 1);
1438 for (unsigned I = 1; I < NumOps; ++I)
1439 Ops.push_back(Op.getOperand(I));
1441 if (Op->getNumValues() == 1)
1442 return DAG.getNode(Opcode, SDLoc(Op), MVT::Glue, Ops);
1443 assert(Op->getNumValues() == 2 && "Expected exactly one non-CC result");
1444 SDVTList RawVTs = DAG.getVTList(Op->getValueType(0), MVT::Glue);
1445 return DAG.getNode(Opcode, SDLoc(Op), RawVTs, Ops);
1448 // CC is a comparison that will be implemented using an integer or
1449 // floating-point comparison. Return the condition code mask for
1450 // a branch on true. In the integer case, CCMASK_CMP_UO is set for
1451 // unsigned comparisons and clear for signed ones. In the floating-point
1452 // case, CCMASK_CMP_UO has its normal mask meaning (unordered).
1453 static unsigned CCMaskForCondCode(ISD::CondCode CC) {
1455 case ISD::SET##X: return SystemZ::CCMASK_CMP_##X; \
1456 case ISD::SETO##X: return SystemZ::CCMASK_CMP_##X; \
1457 case ISD::SETU##X: return SystemZ::CCMASK_CMP_UO | SystemZ::CCMASK_CMP_##X
1461 llvm_unreachable("Invalid integer condition!");
1470 case ISD::SETO: return SystemZ::CCMASK_CMP_O;
1471 case ISD::SETUO: return SystemZ::CCMASK_CMP_UO;
1476 // Return a sequence for getting a 1 from an IPM result when CC has a
1477 // value in CCMask and a 0 when CC has a value in CCValid & ~CCMask.
1478 // The handling of CC values outside CCValid doesn't matter.
1479 static IPMConversion getIPMConversion(unsigned CCValid, unsigned CCMask) {
1480 // Deal with cases where the result can be taken directly from a bit
1481 // of the IPM result.
1482 if (CCMask == (CCValid & (SystemZ::CCMASK_1 | SystemZ::CCMASK_3)))
1483 return IPMConversion(0, 0, SystemZ::IPM_CC);
1484 if (CCMask == (CCValid & (SystemZ::CCMASK_2 | SystemZ::CCMASK_3)))
1485 return IPMConversion(0, 0, SystemZ::IPM_CC + 1);
1487 // Deal with cases where we can add a value to force the sign bit
1488 // to contain the right value. Putting the bit in 31 means we can
1489 // use SRL rather than RISBG(L), and also makes it easier to get a
1490 // 0/-1 value, so it has priority over the other tests below.
1492 // These sequences rely on the fact that the upper two bits of the
1493 // IPM result are zero.
1494 uint64_t TopBit = uint64_t(1) << 31;
1495 if (CCMask == (CCValid & SystemZ::CCMASK_0))
1496 return IPMConversion(0, -(1 << SystemZ::IPM_CC), 31);
1497 if (CCMask == (CCValid & (SystemZ::CCMASK_0 | SystemZ::CCMASK_1)))
1498 return IPMConversion(0, -(2 << SystemZ::IPM_CC), 31);
1499 if (CCMask == (CCValid & (SystemZ::CCMASK_0
1501 | SystemZ::CCMASK_2)))
1502 return IPMConversion(0, -(3 << SystemZ::IPM_CC), 31);
1503 if (CCMask == (CCValid & SystemZ::CCMASK_3))
1504 return IPMConversion(0, TopBit - (3 << SystemZ::IPM_CC), 31);
1505 if (CCMask == (CCValid & (SystemZ::CCMASK_1
1507 | SystemZ::CCMASK_3)))
1508 return IPMConversion(0, TopBit - (1 << SystemZ::IPM_CC), 31);
1510 // Next try inverting the value and testing a bit. 0/1 could be
1511 // handled this way too, but we dealt with that case above.
1512 if (CCMask == (CCValid & (SystemZ::CCMASK_0 | SystemZ::CCMASK_2)))
1513 return IPMConversion(-1, 0, SystemZ::IPM_CC);
1515 // Handle cases where adding a value forces a non-sign bit to contain
1517 if (CCMask == (CCValid & (SystemZ::CCMASK_1 | SystemZ::CCMASK_2)))
1518 return IPMConversion(0, 1 << SystemZ::IPM_CC, SystemZ::IPM_CC + 1);
1519 if (CCMask == (CCValid & (SystemZ::CCMASK_0 | SystemZ::CCMASK_3)))
1520 return IPMConversion(0, -(1 << SystemZ::IPM_CC), SystemZ::IPM_CC + 1);
1522 // The remaining cases are 1, 2, 0/1/3 and 0/2/3. All these are
1523 // can be done by inverting the low CC bit and applying one of the
1524 // sign-based extractions above.
1525 if (CCMask == (CCValid & SystemZ::CCMASK_1))
1526 return IPMConversion(1 << SystemZ::IPM_CC, -(1 << SystemZ::IPM_CC), 31);
1527 if (CCMask == (CCValid & SystemZ::CCMASK_2))
1528 return IPMConversion(1 << SystemZ::IPM_CC,
1529 TopBit - (3 << SystemZ::IPM_CC), 31);
1530 if (CCMask == (CCValid & (SystemZ::CCMASK_0
1532 | SystemZ::CCMASK_3)))
1533 return IPMConversion(1 << SystemZ::IPM_CC, -(3 << SystemZ::IPM_CC), 31);
1534 if (CCMask == (CCValid & (SystemZ::CCMASK_0
1536 | SystemZ::CCMASK_3)))
1537 return IPMConversion(1 << SystemZ::IPM_CC,
1538 TopBit - (1 << SystemZ::IPM_CC), 31);
1540 llvm_unreachable("Unexpected CC combination");
1543 // If C can be converted to a comparison against zero, adjust the operands
1545 static void adjustZeroCmp(SelectionDAG &DAG, SDLoc DL, Comparison &C) {
1546 if (C.ICmpType == SystemZICMP::UnsignedOnly)
1549 auto *ConstOp1 = dyn_cast<ConstantSDNode>(C.Op1.getNode());
1553 int64_t Value = ConstOp1->getSExtValue();
1554 if ((Value == -1 && C.CCMask == SystemZ::CCMASK_CMP_GT) ||
1555 (Value == -1 && C.CCMask == SystemZ::CCMASK_CMP_LE) ||
1556 (Value == 1 && C.CCMask == SystemZ::CCMASK_CMP_LT) ||
1557 (Value == 1 && C.CCMask == SystemZ::CCMASK_CMP_GE)) {
1558 C.CCMask ^= SystemZ::CCMASK_CMP_EQ;
1559 C.Op1 = DAG.getConstant(0, DL, C.Op1.getValueType());
1563 // If a comparison described by C is suitable for CLI(Y), CHHSI or CLHHSI,
1564 // adjust the operands as necessary.
1565 static void adjustSubwordCmp(SelectionDAG &DAG, SDLoc DL, Comparison &C) {
1566 // For us to make any changes, it must a comparison between a single-use
1567 // load and a constant.
1568 if (!C.Op0.hasOneUse() ||
1569 C.Op0.getOpcode() != ISD::LOAD ||
1570 C.Op1.getOpcode() != ISD::Constant)
1573 // We must have an 8- or 16-bit load.
1574 auto *Load = cast<LoadSDNode>(C.Op0);
1575 unsigned NumBits = Load->getMemoryVT().getStoreSizeInBits();
1576 if (NumBits != 8 && NumBits != 16)
1579 // The load must be an extending one and the constant must be within the
1580 // range of the unextended value.
1581 auto *ConstOp1 = cast<ConstantSDNode>(C.Op1);
1582 uint64_t Value = ConstOp1->getZExtValue();
1583 uint64_t Mask = (1 << NumBits) - 1;
1584 if (Load->getExtensionType() == ISD::SEXTLOAD) {
1585 // Make sure that ConstOp1 is in range of C.Op0.
1586 int64_t SignedValue = ConstOp1->getSExtValue();
1587 if (uint64_t(SignedValue) + (uint64_t(1) << (NumBits - 1)) > Mask)
1589 if (C.ICmpType != SystemZICMP::SignedOnly) {
1590 // Unsigned comparison between two sign-extended values is equivalent
1591 // to unsigned comparison between two zero-extended values.
1593 } else if (NumBits == 8) {
1594 // Try to treat the comparison as unsigned, so that we can use CLI.
1595 // Adjust CCMask and Value as necessary.
1596 if (Value == 0 && C.CCMask == SystemZ::CCMASK_CMP_LT)
1597 // Test whether the high bit of the byte is set.
1598 Value = 127, C.CCMask = SystemZ::CCMASK_CMP_GT;
1599 else if (Value == 0 && C.CCMask == SystemZ::CCMASK_CMP_GE)
1600 // Test whether the high bit of the byte is clear.
1601 Value = 128, C.CCMask = SystemZ::CCMASK_CMP_LT;
1603 // No instruction exists for this combination.
1605 C.ICmpType = SystemZICMP::UnsignedOnly;
1607 } else if (Load->getExtensionType() == ISD::ZEXTLOAD) {
1610 assert(C.ICmpType == SystemZICMP::Any &&
1611 "Signedness shouldn't matter here.");
1615 // Make sure that the first operand is an i32 of the right extension type.
1616 ISD::LoadExtType ExtType = (C.ICmpType == SystemZICMP::SignedOnly ?
1619 if (C.Op0.getValueType() != MVT::i32 ||
1620 Load->getExtensionType() != ExtType)
1621 C.Op0 = DAG.getExtLoad(ExtType, SDLoc(Load), MVT::i32,
1622 Load->getChain(), Load->getBasePtr(),
1623 Load->getPointerInfo(), Load->getMemoryVT(),
1624 Load->isVolatile(), Load->isNonTemporal(),
1625 Load->isInvariant(), Load->getAlignment());
1627 // Make sure that the second operand is an i32 with the right value.
1628 if (C.Op1.getValueType() != MVT::i32 ||
1629 Value != ConstOp1->getZExtValue())
1630 C.Op1 = DAG.getConstant(Value, DL, MVT::i32);
1633 // Return true if Op is either an unextended load, or a load suitable
1634 // for integer register-memory comparisons of type ICmpType.
1635 static bool isNaturalMemoryOperand(SDValue Op, unsigned ICmpType) {
1636 auto *Load = dyn_cast<LoadSDNode>(Op.getNode());
1638 // There are no instructions to compare a register with a memory byte.
1639 if (Load->getMemoryVT() == MVT::i8)
1641 // Otherwise decide on extension type.
1642 switch (Load->getExtensionType()) {
1643 case ISD::NON_EXTLOAD:
1646 return ICmpType != SystemZICMP::UnsignedOnly;
1648 return ICmpType != SystemZICMP::SignedOnly;
1656 // Return true if it is better to swap the operands of C.
1657 static bool shouldSwapCmpOperands(const Comparison &C) {
1658 // Leave f128 comparisons alone, since they have no memory forms.
1659 if (C.Op0.getValueType() == MVT::f128)
1662 // Always keep a floating-point constant second, since comparisons with
1663 // zero can use LOAD TEST and comparisons with other constants make a
1664 // natural memory operand.
1665 if (isa<ConstantFPSDNode>(C.Op1))
1668 // Never swap comparisons with zero since there are many ways to optimize
1670 auto *ConstOp1 = dyn_cast<ConstantSDNode>(C.Op1);
1671 if (ConstOp1 && ConstOp1->getZExtValue() == 0)
1674 // Also keep natural memory operands second if the loaded value is
1675 // only used here. Several comparisons have memory forms.
1676 if (isNaturalMemoryOperand(C.Op1, C.ICmpType) && C.Op1.hasOneUse())
1679 // Look for cases where Cmp0 is a single-use load and Cmp1 isn't.
1680 // In that case we generally prefer the memory to be second.
1681 if (isNaturalMemoryOperand(C.Op0, C.ICmpType) && C.Op0.hasOneUse()) {
1682 // The only exceptions are when the second operand is a constant and
1683 // we can use things like CHHSI.
1686 // The unsigned memory-immediate instructions can handle 16-bit
1687 // unsigned integers.
1688 if (C.ICmpType != SystemZICMP::SignedOnly &&
1689 isUInt<16>(ConstOp1->getZExtValue()))
1691 // The signed memory-immediate instructions can handle 16-bit
1693 if (C.ICmpType != SystemZICMP::UnsignedOnly &&
1694 isInt<16>(ConstOp1->getSExtValue()))
1699 // Try to promote the use of CGFR and CLGFR.
1700 unsigned Opcode0 = C.Op0.getOpcode();
1701 if (C.ICmpType != SystemZICMP::UnsignedOnly && Opcode0 == ISD::SIGN_EXTEND)
1703 if (C.ICmpType != SystemZICMP::SignedOnly && Opcode0 == ISD::ZERO_EXTEND)
1705 if (C.ICmpType != SystemZICMP::SignedOnly &&
1706 Opcode0 == ISD::AND &&
1707 C.Op0.getOperand(1).getOpcode() == ISD::Constant &&
1708 cast<ConstantSDNode>(C.Op0.getOperand(1))->getZExtValue() == 0xffffffff)
1714 // Return a version of comparison CC mask CCMask in which the LT and GT
1715 // actions are swapped.
1716 static unsigned reverseCCMask(unsigned CCMask) {
1717 return ((CCMask & SystemZ::CCMASK_CMP_EQ) |
1718 (CCMask & SystemZ::CCMASK_CMP_GT ? SystemZ::CCMASK_CMP_LT : 0) |
1719 (CCMask & SystemZ::CCMASK_CMP_LT ? SystemZ::CCMASK_CMP_GT : 0) |
1720 (CCMask & SystemZ::CCMASK_CMP_UO));
1723 // Check whether C tests for equality between X and Y and whether X - Y
1724 // or Y - X is also computed. In that case it's better to compare the
1725 // result of the subtraction against zero.
1726 static void adjustForSubtraction(SelectionDAG &DAG, SDLoc DL, Comparison &C) {
1727 if (C.CCMask == SystemZ::CCMASK_CMP_EQ ||
1728 C.CCMask == SystemZ::CCMASK_CMP_NE) {
1729 for (auto I = C.Op0->use_begin(), E = C.Op0->use_end(); I != E; ++I) {
1731 if (N->getOpcode() == ISD::SUB &&
1732 ((N->getOperand(0) == C.Op0 && N->getOperand(1) == C.Op1) ||
1733 (N->getOperand(0) == C.Op1 && N->getOperand(1) == C.Op0))) {
1734 C.Op0 = SDValue(N, 0);
1735 C.Op1 = DAG.getConstant(0, DL, N->getValueType(0));
1742 // Check whether C compares a floating-point value with zero and if that
1743 // floating-point value is also negated. In this case we can use the
1744 // negation to set CC, so avoiding separate LOAD AND TEST and
1745 // LOAD (NEGATIVE/COMPLEMENT) instructions.
1746 static void adjustForFNeg(Comparison &C) {
1747 auto *C1 = dyn_cast<ConstantFPSDNode>(C.Op1);
1748 if (C1 && C1->isZero()) {
1749 for (auto I = C.Op0->use_begin(), E = C.Op0->use_end(); I != E; ++I) {
1751 if (N->getOpcode() == ISD::FNEG) {
1752 C.Op0 = SDValue(N, 0);
1753 C.CCMask = reverseCCMask(C.CCMask);
1760 // Check whether C compares (shl X, 32) with 0 and whether X is
1761 // also sign-extended. In that case it is better to test the result
1762 // of the sign extension using LTGFR.
1764 // This case is important because InstCombine transforms a comparison
1765 // with (sext (trunc X)) into a comparison with (shl X, 32).
1766 static void adjustForLTGFR(Comparison &C) {
1767 // Check for a comparison between (shl X, 32) and 0.
1768 if (C.Op0.getOpcode() == ISD::SHL &&
1769 C.Op0.getValueType() == MVT::i64 &&
1770 C.Op1.getOpcode() == ISD::Constant &&
1771 cast<ConstantSDNode>(C.Op1)->getZExtValue() == 0) {
1772 auto *C1 = dyn_cast<ConstantSDNode>(C.Op0.getOperand(1));
1773 if (C1 && C1->getZExtValue() == 32) {
1774 SDValue ShlOp0 = C.Op0.getOperand(0);
1775 // See whether X has any SIGN_EXTEND_INREG uses.
1776 for (auto I = ShlOp0->use_begin(), E = ShlOp0->use_end(); I != E; ++I) {
1778 if (N->getOpcode() == ISD::SIGN_EXTEND_INREG &&
1779 cast<VTSDNode>(N->getOperand(1))->getVT() == MVT::i32) {
1780 C.Op0 = SDValue(N, 0);
1788 // If C compares the truncation of an extending load, try to compare
1789 // the untruncated value instead. This exposes more opportunities to
1791 static void adjustICmpTruncate(SelectionDAG &DAG, SDLoc DL, Comparison &C) {
1792 if (C.Op0.getOpcode() == ISD::TRUNCATE &&
1793 C.Op0.getOperand(0).getOpcode() == ISD::LOAD &&
1794 C.Op1.getOpcode() == ISD::Constant &&
1795 cast<ConstantSDNode>(C.Op1)->getZExtValue() == 0) {
1796 auto *L = cast<LoadSDNode>(C.Op0.getOperand(0));
1797 if (L->getMemoryVT().getStoreSizeInBits()
1798 <= C.Op0.getValueType().getSizeInBits()) {
1799 unsigned Type = L->getExtensionType();
1800 if ((Type == ISD::ZEXTLOAD && C.ICmpType != SystemZICMP::SignedOnly) ||
1801 (Type == ISD::SEXTLOAD && C.ICmpType != SystemZICMP::UnsignedOnly)) {
1802 C.Op0 = C.Op0.getOperand(0);
1803 C.Op1 = DAG.getConstant(0, DL, C.Op0.getValueType());
1809 // Return true if shift operation N has an in-range constant shift value.
1810 // Store it in ShiftVal if so.
1811 static bool isSimpleShift(SDValue N, unsigned &ShiftVal) {
1812 auto *Shift = dyn_cast<ConstantSDNode>(N.getOperand(1));
1816 uint64_t Amount = Shift->getZExtValue();
1817 if (Amount >= N.getValueType().getSizeInBits())
1824 // Check whether an AND with Mask is suitable for a TEST UNDER MASK
1825 // instruction and whether the CC value is descriptive enough to handle
1826 // a comparison of type Opcode between the AND result and CmpVal.
1827 // CCMask says which comparison result is being tested and BitSize is
1828 // the number of bits in the operands. If TEST UNDER MASK can be used,
1829 // return the corresponding CC mask, otherwise return 0.
1830 static unsigned getTestUnderMaskCond(unsigned BitSize, unsigned CCMask,
1831 uint64_t Mask, uint64_t CmpVal,
1832 unsigned ICmpType) {
1833 assert(Mask != 0 && "ANDs with zero should have been removed by now");
1835 // Check whether the mask is suitable for TMHH, TMHL, TMLH or TMLL.
1836 if (!SystemZ::isImmLL(Mask) && !SystemZ::isImmLH(Mask) &&
1837 !SystemZ::isImmHL(Mask) && !SystemZ::isImmHH(Mask))
1840 // Work out the masks for the lowest and highest bits.
1841 unsigned HighShift = 63 - countLeadingZeros(Mask);
1842 uint64_t High = uint64_t(1) << HighShift;
1843 uint64_t Low = uint64_t(1) << countTrailingZeros(Mask);
1845 // Signed ordered comparisons are effectively unsigned if the sign
1847 bool EffectivelyUnsigned = (ICmpType != SystemZICMP::SignedOnly);
1849 // Check for equality comparisons with 0, or the equivalent.
1851 if (CCMask == SystemZ::CCMASK_CMP_EQ)
1852 return SystemZ::CCMASK_TM_ALL_0;
1853 if (CCMask == SystemZ::CCMASK_CMP_NE)
1854 return SystemZ::CCMASK_TM_SOME_1;
1856 if (EffectivelyUnsigned && CmpVal <= Low) {
1857 if (CCMask == SystemZ::CCMASK_CMP_LT)
1858 return SystemZ::CCMASK_TM_ALL_0;
1859 if (CCMask == SystemZ::CCMASK_CMP_GE)
1860 return SystemZ::CCMASK_TM_SOME_1;
1862 if (EffectivelyUnsigned && CmpVal < Low) {
1863 if (CCMask == SystemZ::CCMASK_CMP_LE)
1864 return SystemZ::CCMASK_TM_ALL_0;
1865 if (CCMask == SystemZ::CCMASK_CMP_GT)
1866 return SystemZ::CCMASK_TM_SOME_1;
1869 // Check for equality comparisons with the mask, or the equivalent.
1870 if (CmpVal == Mask) {
1871 if (CCMask == SystemZ::CCMASK_CMP_EQ)
1872 return SystemZ::CCMASK_TM_ALL_1;
1873 if (CCMask == SystemZ::CCMASK_CMP_NE)
1874 return SystemZ::CCMASK_TM_SOME_0;
1876 if (EffectivelyUnsigned && CmpVal >= Mask - Low && CmpVal < Mask) {
1877 if (CCMask == SystemZ::CCMASK_CMP_GT)
1878 return SystemZ::CCMASK_TM_ALL_1;
1879 if (CCMask == SystemZ::CCMASK_CMP_LE)
1880 return SystemZ::CCMASK_TM_SOME_0;
1882 if (EffectivelyUnsigned && CmpVal > Mask - Low && CmpVal <= Mask) {
1883 if (CCMask == SystemZ::CCMASK_CMP_GE)
1884 return SystemZ::CCMASK_TM_ALL_1;
1885 if (CCMask == SystemZ::CCMASK_CMP_LT)
1886 return SystemZ::CCMASK_TM_SOME_0;
1889 // Check for ordered comparisons with the top bit.
1890 if (EffectivelyUnsigned && CmpVal >= Mask - High && CmpVal < High) {
1891 if (CCMask == SystemZ::CCMASK_CMP_LE)
1892 return SystemZ::CCMASK_TM_MSB_0;
1893 if (CCMask == SystemZ::CCMASK_CMP_GT)
1894 return SystemZ::CCMASK_TM_MSB_1;
1896 if (EffectivelyUnsigned && CmpVal > Mask - High && CmpVal <= High) {
1897 if (CCMask == SystemZ::CCMASK_CMP_LT)
1898 return SystemZ::CCMASK_TM_MSB_0;
1899 if (CCMask == SystemZ::CCMASK_CMP_GE)
1900 return SystemZ::CCMASK_TM_MSB_1;
1903 // If there are just two bits, we can do equality checks for Low and High
1905 if (Mask == Low + High) {
1906 if (CCMask == SystemZ::CCMASK_CMP_EQ && CmpVal == Low)
1907 return SystemZ::CCMASK_TM_MIXED_MSB_0;
1908 if (CCMask == SystemZ::CCMASK_CMP_NE && CmpVal == Low)
1909 return SystemZ::CCMASK_TM_MIXED_MSB_0 ^ SystemZ::CCMASK_ANY;
1910 if (CCMask == SystemZ::CCMASK_CMP_EQ && CmpVal == High)
1911 return SystemZ::CCMASK_TM_MIXED_MSB_1;
1912 if (CCMask == SystemZ::CCMASK_CMP_NE && CmpVal == High)
1913 return SystemZ::CCMASK_TM_MIXED_MSB_1 ^ SystemZ::CCMASK_ANY;
1916 // Looks like we've exhausted our options.
1920 // See whether C can be implemented as a TEST UNDER MASK instruction.
1921 // Update the arguments with the TM version if so.
1922 static void adjustForTestUnderMask(SelectionDAG &DAG, SDLoc DL, Comparison &C) {
1923 // Check that we have a comparison with a constant.
1924 auto *ConstOp1 = dyn_cast<ConstantSDNode>(C.Op1);
1927 uint64_t CmpVal = ConstOp1->getZExtValue();
1929 // Check whether the nonconstant input is an AND with a constant mask.
1932 ConstantSDNode *Mask = nullptr;
1933 if (C.Op0.getOpcode() == ISD::AND) {
1934 NewC.Op0 = C.Op0.getOperand(0);
1935 NewC.Op1 = C.Op0.getOperand(1);
1936 Mask = dyn_cast<ConstantSDNode>(NewC.Op1);
1939 MaskVal = Mask->getZExtValue();
1941 // There is no instruction to compare with a 64-bit immediate
1942 // so use TMHH instead if possible. We need an unsigned ordered
1943 // comparison with an i64 immediate.
1944 if (NewC.Op0.getValueType() != MVT::i64 ||
1945 NewC.CCMask == SystemZ::CCMASK_CMP_EQ ||
1946 NewC.CCMask == SystemZ::CCMASK_CMP_NE ||
1947 NewC.ICmpType == SystemZICMP::SignedOnly)
1949 // Convert LE and GT comparisons into LT and GE.
1950 if (NewC.CCMask == SystemZ::CCMASK_CMP_LE ||
1951 NewC.CCMask == SystemZ::CCMASK_CMP_GT) {
1952 if (CmpVal == uint64_t(-1))
1955 NewC.CCMask ^= SystemZ::CCMASK_CMP_EQ;
1957 // If the low N bits of Op1 are zero than the low N bits of Op0 can
1958 // be masked off without changing the result.
1959 MaskVal = -(CmpVal & -CmpVal);
1960 NewC.ICmpType = SystemZICMP::UnsignedOnly;
1965 // Check whether the combination of mask, comparison value and comparison
1966 // type are suitable.
1967 unsigned BitSize = NewC.Op0.getValueType().getSizeInBits();
1968 unsigned NewCCMask, ShiftVal;
1969 if (NewC.ICmpType != SystemZICMP::SignedOnly &&
1970 NewC.Op0.getOpcode() == ISD::SHL &&
1971 isSimpleShift(NewC.Op0, ShiftVal) &&
1972 (NewCCMask = getTestUnderMaskCond(BitSize, NewC.CCMask,
1973 MaskVal >> ShiftVal,
1975 SystemZICMP::Any))) {
1976 NewC.Op0 = NewC.Op0.getOperand(0);
1977 MaskVal >>= ShiftVal;
1978 } else if (NewC.ICmpType != SystemZICMP::SignedOnly &&
1979 NewC.Op0.getOpcode() == ISD::SRL &&
1980 isSimpleShift(NewC.Op0, ShiftVal) &&
1981 (NewCCMask = getTestUnderMaskCond(BitSize, NewC.CCMask,
1982 MaskVal << ShiftVal,
1984 SystemZICMP::UnsignedOnly))) {
1985 NewC.Op0 = NewC.Op0.getOperand(0);
1986 MaskVal <<= ShiftVal;
1988 NewCCMask = getTestUnderMaskCond(BitSize, NewC.CCMask, MaskVal, CmpVal,
1994 // Go ahead and make the change.
1995 C.Opcode = SystemZISD::TM;
1997 if (Mask && Mask->getZExtValue() == MaskVal)
1998 C.Op1 = SDValue(Mask, 0);
2000 C.Op1 = DAG.getConstant(MaskVal, DL, C.Op0.getValueType());
2001 C.CCValid = SystemZ::CCMASK_TM;
2002 C.CCMask = NewCCMask;
2005 // Return a Comparison that tests the condition-code result of intrinsic
2006 // node Call against constant integer CC using comparison code Cond.
2007 // Opcode is the opcode of the SystemZISD operation for the intrinsic
2008 // and CCValid is the set of possible condition-code results.
2009 static Comparison getIntrinsicCmp(SelectionDAG &DAG, unsigned Opcode,
2010 SDValue Call, unsigned CCValid, uint64_t CC,
2011 ISD::CondCode Cond) {
2012 Comparison C(Call, SDValue());
2014 C.CCValid = CCValid;
2015 if (Cond == ISD::SETEQ)
2016 // bit 3 for CC==0, bit 0 for CC==3, always false for CC>3.
2017 C.CCMask = CC < 4 ? 1 << (3 - CC) : 0;
2018 else if (Cond == ISD::SETNE)
2019 // ...and the inverse of that.
2020 C.CCMask = CC < 4 ? ~(1 << (3 - CC)) : -1;
2021 else if (Cond == ISD::SETLT || Cond == ISD::SETULT)
2022 // bits above bit 3 for CC==0 (always false), bits above bit 0 for CC==3,
2023 // always true for CC>3.
2024 C.CCMask = CC < 4 ? ~0U << (4 - CC) : -1;
2025 else if (Cond == ISD::SETGE || Cond == ISD::SETUGE)
2026 // ...and the inverse of that.
2027 C.CCMask = CC < 4 ? ~(~0U << (4 - CC)) : 0;
2028 else if (Cond == ISD::SETLE || Cond == ISD::SETULE)
2029 // bit 3 and above for CC==0, bit 0 and above for CC==3 (always true),
2030 // always true for CC>3.
2031 C.CCMask = CC < 4 ? ~0U << (3 - CC) : -1;
2032 else if (Cond == ISD::SETGT || Cond == ISD::SETUGT)
2033 // ...and the inverse of that.
2034 C.CCMask = CC < 4 ? ~(~0U << (3 - CC)) : 0;
2036 llvm_unreachable("Unexpected integer comparison type");
2037 C.CCMask &= CCValid;
2041 // Decide how to implement a comparison of type Cond between CmpOp0 with CmpOp1.
2042 static Comparison getCmp(SelectionDAG &DAG, SDValue CmpOp0, SDValue CmpOp1,
2043 ISD::CondCode Cond, SDLoc DL) {
2044 if (CmpOp1.getOpcode() == ISD::Constant) {
2045 uint64_t Constant = cast<ConstantSDNode>(CmpOp1)->getZExtValue();
2046 unsigned Opcode, CCValid;
2047 if (CmpOp0.getOpcode() == ISD::INTRINSIC_W_CHAIN &&
2048 CmpOp0.getResNo() == 0 && CmpOp0->hasNUsesOfValue(1, 0) &&
2049 isIntrinsicWithCCAndChain(CmpOp0, Opcode, CCValid))
2050 return getIntrinsicCmp(DAG, Opcode, CmpOp0, CCValid, Constant, Cond);
2051 if (CmpOp0.getOpcode() == ISD::INTRINSIC_WO_CHAIN &&
2052 CmpOp0.getResNo() == CmpOp0->getNumValues() - 1 &&
2053 isIntrinsicWithCC(CmpOp0, Opcode, CCValid))
2054 return getIntrinsicCmp(DAG, Opcode, CmpOp0, CCValid, Constant, Cond);
2056 Comparison C(CmpOp0, CmpOp1);
2057 C.CCMask = CCMaskForCondCode(Cond);
2058 if (C.Op0.getValueType().isFloatingPoint()) {
2059 C.CCValid = SystemZ::CCMASK_FCMP;
2060 C.Opcode = SystemZISD::FCMP;
2063 C.CCValid = SystemZ::CCMASK_ICMP;
2064 C.Opcode = SystemZISD::ICMP;
2065 // Choose the type of comparison. Equality and inequality tests can
2066 // use either signed or unsigned comparisons. The choice also doesn't
2067 // matter if both sign bits are known to be clear. In those cases we
2068 // want to give the main isel code the freedom to choose whichever
2070 if (C.CCMask == SystemZ::CCMASK_CMP_EQ ||
2071 C.CCMask == SystemZ::CCMASK_CMP_NE ||
2072 (DAG.SignBitIsZero(C.Op0) && DAG.SignBitIsZero(C.Op1)))
2073 C.ICmpType = SystemZICMP::Any;
2074 else if (C.CCMask & SystemZ::CCMASK_CMP_UO)
2075 C.ICmpType = SystemZICMP::UnsignedOnly;
2077 C.ICmpType = SystemZICMP::SignedOnly;
2078 C.CCMask &= ~SystemZ::CCMASK_CMP_UO;
2079 adjustZeroCmp(DAG, DL, C);
2080 adjustSubwordCmp(DAG, DL, C);
2081 adjustForSubtraction(DAG, DL, C);
2083 adjustICmpTruncate(DAG, DL, C);
2086 if (shouldSwapCmpOperands(C)) {
2087 std::swap(C.Op0, C.Op1);
2088 C.CCMask = reverseCCMask(C.CCMask);
2091 adjustForTestUnderMask(DAG, DL, C);
2095 // Emit the comparison instruction described by C.
2096 static SDValue emitCmp(SelectionDAG &DAG, SDLoc DL, Comparison &C) {
2097 if (!C.Op1.getNode()) {
2099 switch (C.Op0.getOpcode()) {
2100 case ISD::INTRINSIC_W_CHAIN:
2101 Op = emitIntrinsicWithChainAndGlue(DAG, C.Op0, C.Opcode);
2103 case ISD::INTRINSIC_WO_CHAIN:
2104 Op = emitIntrinsicWithGlue(DAG, C.Op0, C.Opcode);
2107 llvm_unreachable("Invalid comparison operands");
2109 return SDValue(Op.getNode(), Op->getNumValues() - 1);
2111 if (C.Opcode == SystemZISD::ICMP)
2112 return DAG.getNode(SystemZISD::ICMP, DL, MVT::Glue, C.Op0, C.Op1,
2113 DAG.getConstant(C.ICmpType, DL, MVT::i32));
2114 if (C.Opcode == SystemZISD::TM) {
2115 bool RegisterOnly = (bool(C.CCMask & SystemZ::CCMASK_TM_MIXED_MSB_0) !=
2116 bool(C.CCMask & SystemZ::CCMASK_TM_MIXED_MSB_1));
2117 return DAG.getNode(SystemZISD::TM, DL, MVT::Glue, C.Op0, C.Op1,
2118 DAG.getConstant(RegisterOnly, DL, MVT::i32));
2120 return DAG.getNode(C.Opcode, DL, MVT::Glue, C.Op0, C.Op1);
2123 // Implement a 32-bit *MUL_LOHI operation by extending both operands to
2124 // 64 bits. Extend is the extension type to use. Store the high part
2125 // in Hi and the low part in Lo.
2126 static void lowerMUL_LOHI32(SelectionDAG &DAG, SDLoc DL,
2127 unsigned Extend, SDValue Op0, SDValue Op1,
2128 SDValue &Hi, SDValue &Lo) {
2129 Op0 = DAG.getNode(Extend, DL, MVT::i64, Op0);
2130 Op1 = DAG.getNode(Extend, DL, MVT::i64, Op1);
2131 SDValue Mul = DAG.getNode(ISD::MUL, DL, MVT::i64, Op0, Op1);
2132 Hi = DAG.getNode(ISD::SRL, DL, MVT::i64, Mul,
2133 DAG.getConstant(32, DL, MVT::i64));
2134 Hi = DAG.getNode(ISD::TRUNCATE, DL, MVT::i32, Hi);
2135 Lo = DAG.getNode(ISD::TRUNCATE, DL, MVT::i32, Mul);
2138 // Lower a binary operation that produces two VT results, one in each
2139 // half of a GR128 pair. Op0 and Op1 are the VT operands to the operation,
2140 // Extend extends Op0 to a GR128, and Opcode performs the GR128 operation
2141 // on the extended Op0 and (unextended) Op1. Store the even register result
2142 // in Even and the odd register result in Odd.
2143 static void lowerGR128Binary(SelectionDAG &DAG, SDLoc DL, EVT VT,
2144 unsigned Extend, unsigned Opcode,
2145 SDValue Op0, SDValue Op1,
2146 SDValue &Even, SDValue &Odd) {
2147 SDNode *In128 = DAG.getMachineNode(Extend, DL, MVT::Untyped, Op0);
2148 SDValue Result = DAG.getNode(Opcode, DL, MVT::Untyped,
2149 SDValue(In128, 0), Op1);
2150 bool Is32Bit = is32Bit(VT);
2151 Even = DAG.getTargetExtractSubreg(SystemZ::even128(Is32Bit), DL, VT, Result);
2152 Odd = DAG.getTargetExtractSubreg(SystemZ::odd128(Is32Bit), DL, VT, Result);
2155 // Return an i32 value that is 1 if the CC value produced by Glue is
2156 // in the mask CCMask and 0 otherwise. CC is known to have a value
2157 // in CCValid, so other values can be ignored.
2158 static SDValue emitSETCC(SelectionDAG &DAG, SDLoc DL, SDValue Glue,
2159 unsigned CCValid, unsigned CCMask) {
2160 IPMConversion Conversion = getIPMConversion(CCValid, CCMask);
2161 SDValue Result = DAG.getNode(SystemZISD::IPM, DL, MVT::i32, Glue);
2163 if (Conversion.XORValue)
2164 Result = DAG.getNode(ISD::XOR, DL, MVT::i32, Result,
2165 DAG.getConstant(Conversion.XORValue, DL, MVT::i32));
2167 if (Conversion.AddValue)
2168 Result = DAG.getNode(ISD::ADD, DL, MVT::i32, Result,
2169 DAG.getConstant(Conversion.AddValue, DL, MVT::i32));
2171 // The SHR/AND sequence should get optimized to an RISBG.
2172 Result = DAG.getNode(ISD::SRL, DL, MVT::i32, Result,
2173 DAG.getConstant(Conversion.Bit, DL, MVT::i32));
2174 if (Conversion.Bit != 31)
2175 Result = DAG.getNode(ISD::AND, DL, MVT::i32, Result,
2176 DAG.getConstant(1, DL, MVT::i32));
2180 // Return the SystemISD vector comparison operation for CC, or 0 if it cannot
2181 // be done directly. IsFP is true if CC is for a floating-point rather than
2182 // integer comparison.
2183 static unsigned getVectorComparison(ISD::CondCode CC, bool IsFP) {
2187 return IsFP ? SystemZISD::VFCMPE : SystemZISD::VICMPE;
2191 return IsFP ? SystemZISD::VFCMPHE : static_cast<SystemZISD::NodeType>(0);
2195 return IsFP ? SystemZISD::VFCMPH : SystemZISD::VICMPH;
2198 return IsFP ? static_cast<SystemZISD::NodeType>(0) : SystemZISD::VICMPHL;
2205 // Return the SystemZISD vector comparison operation for CC or its inverse,
2206 // or 0 if neither can be done directly. Indicate in Invert whether the
2207 // result is for the inverse of CC. IsFP is true if CC is for a
2208 // floating-point rather than integer comparison.
2209 static unsigned getVectorComparisonOrInvert(ISD::CondCode CC, bool IsFP,
2211 if (unsigned Opcode = getVectorComparison(CC, IsFP)) {
2216 CC = ISD::getSetCCInverse(CC, !IsFP);
2217 if (unsigned Opcode = getVectorComparison(CC, IsFP)) {
2225 // Return a v2f64 that contains the extended form of elements Start and Start+1
2226 // of v4f32 value Op.
2227 static SDValue expandV4F32ToV2F64(SelectionDAG &DAG, int Start, SDLoc DL,
2229 int Mask[] = { Start, -1, Start + 1, -1 };
2230 Op = DAG.getVectorShuffle(MVT::v4f32, DL, Op, DAG.getUNDEF(MVT::v4f32), Mask);
2231 return DAG.getNode(SystemZISD::VEXTEND, DL, MVT::v2f64, Op);
2234 // Build a comparison of vectors CmpOp0 and CmpOp1 using opcode Opcode,
2235 // producing a result of type VT.
2236 static SDValue getVectorCmp(SelectionDAG &DAG, unsigned Opcode, SDLoc DL,
2237 EVT VT, SDValue CmpOp0, SDValue CmpOp1) {
2238 // There is no hardware support for v4f32, so extend the vector into
2239 // two v2f64s and compare those.
2240 if (CmpOp0.getValueType() == MVT::v4f32) {
2241 SDValue H0 = expandV4F32ToV2F64(DAG, 0, DL, CmpOp0);
2242 SDValue L0 = expandV4F32ToV2F64(DAG, 2, DL, CmpOp0);
2243 SDValue H1 = expandV4F32ToV2F64(DAG, 0, DL, CmpOp1);
2244 SDValue L1 = expandV4F32ToV2F64(DAG, 2, DL, CmpOp1);
2245 SDValue HRes = DAG.getNode(Opcode, DL, MVT::v2i64, H0, H1);
2246 SDValue LRes = DAG.getNode(Opcode, DL, MVT::v2i64, L0, L1);
2247 return DAG.getNode(SystemZISD::PACK, DL, VT, HRes, LRes);
2249 return DAG.getNode(Opcode, DL, VT, CmpOp0, CmpOp1);
2252 // Lower a vector comparison of type CC between CmpOp0 and CmpOp1, producing
2253 // an integer mask of type VT.
2254 static SDValue lowerVectorSETCC(SelectionDAG &DAG, SDLoc DL, EVT VT,
2255 ISD::CondCode CC, SDValue CmpOp0,
2257 bool IsFP = CmpOp0.getValueType().isFloatingPoint();
2258 bool Invert = false;
2261 // Handle tests for order using (or (ogt y x) (oge x y)).
2265 assert(IsFP && "Unexpected integer comparison");
2266 SDValue LT = getVectorCmp(DAG, SystemZISD::VFCMPH, DL, VT, CmpOp1, CmpOp0);
2267 SDValue GE = getVectorCmp(DAG, SystemZISD::VFCMPHE, DL, VT, CmpOp0, CmpOp1);
2268 Cmp = DAG.getNode(ISD::OR, DL, VT, LT, GE);
2272 // Handle <> tests using (or (ogt y x) (ogt x y)).
2276 assert(IsFP && "Unexpected integer comparison");
2277 SDValue LT = getVectorCmp(DAG, SystemZISD::VFCMPH, DL, VT, CmpOp1, CmpOp0);
2278 SDValue GT = getVectorCmp(DAG, SystemZISD::VFCMPH, DL, VT, CmpOp0, CmpOp1);
2279 Cmp = DAG.getNode(ISD::OR, DL, VT, LT, GT);
2283 // Otherwise a single comparison is enough. It doesn't really
2284 // matter whether we try the inversion or the swap first, since
2285 // there are no cases where both work.
2287 if (unsigned Opcode = getVectorComparisonOrInvert(CC, IsFP, Invert))
2288 Cmp = getVectorCmp(DAG, Opcode, DL, VT, CmpOp0, CmpOp1);
2290 CC = ISD::getSetCCSwappedOperands(CC);
2291 if (unsigned Opcode = getVectorComparisonOrInvert(CC, IsFP, Invert))
2292 Cmp = getVectorCmp(DAG, Opcode, DL, VT, CmpOp1, CmpOp0);
2294 llvm_unreachable("Unhandled comparison");
2299 SDValue Mask = DAG.getNode(SystemZISD::BYTE_MASK, DL, MVT::v16i8,
2300 DAG.getConstant(65535, DL, MVT::i32));
2301 Mask = DAG.getNode(ISD::BITCAST, DL, VT, Mask);
2302 Cmp = DAG.getNode(ISD::XOR, DL, VT, Cmp, Mask);
2307 SDValue SystemZTargetLowering::lowerSETCC(SDValue Op,
2308 SelectionDAG &DAG) const {
2309 SDValue CmpOp0 = Op.getOperand(0);
2310 SDValue CmpOp1 = Op.getOperand(1);
2311 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(2))->get();
2313 EVT VT = Op.getValueType();
2315 return lowerVectorSETCC(DAG, DL, VT, CC, CmpOp0, CmpOp1);
2317 Comparison C(getCmp(DAG, CmpOp0, CmpOp1, CC, DL));
2318 SDValue Glue = emitCmp(DAG, DL, C);
2319 return emitSETCC(DAG, DL, Glue, C.CCValid, C.CCMask);
2322 SDValue SystemZTargetLowering::lowerBR_CC(SDValue Op, SelectionDAG &DAG) const {
2323 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(1))->get();
2324 SDValue CmpOp0 = Op.getOperand(2);
2325 SDValue CmpOp1 = Op.getOperand(3);
2326 SDValue Dest = Op.getOperand(4);
2329 Comparison C(getCmp(DAG, CmpOp0, CmpOp1, CC, DL));
2330 SDValue Glue = emitCmp(DAG, DL, C);
2331 return DAG.getNode(SystemZISD::BR_CCMASK, DL, Op.getValueType(),
2332 Op.getOperand(0), DAG.getConstant(C.CCValid, DL, MVT::i32),
2333 DAG.getConstant(C.CCMask, DL, MVT::i32), Dest, Glue);
2336 // Return true if Pos is CmpOp and Neg is the negative of CmpOp,
2337 // allowing Pos and Neg to be wider than CmpOp.
2338 static bool isAbsolute(SDValue CmpOp, SDValue Pos, SDValue Neg) {
2339 return (Neg.getOpcode() == ISD::SUB &&
2340 Neg.getOperand(0).getOpcode() == ISD::Constant &&
2341 cast<ConstantSDNode>(Neg.getOperand(0))->getZExtValue() == 0 &&
2342 Neg.getOperand(1) == Pos &&
2344 (Pos.getOpcode() == ISD::SIGN_EXTEND &&
2345 Pos.getOperand(0) == CmpOp)));
2348 // Return the absolute or negative absolute of Op; IsNegative decides which.
2349 static SDValue getAbsolute(SelectionDAG &DAG, SDLoc DL, SDValue Op,
2351 Op = DAG.getNode(SystemZISD::IABS, DL, Op.getValueType(), Op);
2353 Op = DAG.getNode(ISD::SUB, DL, Op.getValueType(),
2354 DAG.getConstant(0, DL, Op.getValueType()), Op);
2358 SDValue SystemZTargetLowering::lowerSELECT_CC(SDValue Op,
2359 SelectionDAG &DAG) const {
2360 SDValue CmpOp0 = Op.getOperand(0);
2361 SDValue CmpOp1 = Op.getOperand(1);
2362 SDValue TrueOp = Op.getOperand(2);
2363 SDValue FalseOp = Op.getOperand(3);
2364 ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(4))->get();
2367 Comparison C(getCmp(DAG, CmpOp0, CmpOp1, CC, DL));
2369 // Check for absolute and negative-absolute selections, including those
2370 // where the comparison value is sign-extended (for LPGFR and LNGFR).
2371 // This check supplements the one in DAGCombiner.
2372 if (C.Opcode == SystemZISD::ICMP &&
2373 C.CCMask != SystemZ::CCMASK_CMP_EQ &&
2374 C.CCMask != SystemZ::CCMASK_CMP_NE &&
2375 C.Op1.getOpcode() == ISD::Constant &&
2376 cast<ConstantSDNode>(C.Op1)->getZExtValue() == 0) {
2377 if (isAbsolute(C.Op0, TrueOp, FalseOp))
2378 return getAbsolute(DAG, DL, TrueOp, C.CCMask & SystemZ::CCMASK_CMP_LT);
2379 if (isAbsolute(C.Op0, FalseOp, TrueOp))
2380 return getAbsolute(DAG, DL, FalseOp, C.CCMask & SystemZ::CCMASK_CMP_GT);
2383 SDValue Glue = emitCmp(DAG, DL, C);
2385 // Special case for handling -1/0 results. The shifts we use here
2386 // should get optimized with the IPM conversion sequence.
2387 auto *TrueC = dyn_cast<ConstantSDNode>(TrueOp);
2388 auto *FalseC = dyn_cast<ConstantSDNode>(FalseOp);
2389 if (TrueC && FalseC) {
2390 int64_t TrueVal = TrueC->getSExtValue();
2391 int64_t FalseVal = FalseC->getSExtValue();
2392 if ((TrueVal == -1 && FalseVal == 0) || (TrueVal == 0 && FalseVal == -1)) {
2393 // Invert the condition if we want -1 on false.
2395 C.CCMask ^= C.CCValid;
2396 SDValue Result = emitSETCC(DAG, DL, Glue, C.CCValid, C.CCMask);
2397 EVT VT = Op.getValueType();
2398 // Extend the result to VT. Upper bits are ignored.
2400 Result = DAG.getNode(ISD::ANY_EXTEND, DL, VT, Result);
2401 // Sign-extend from the low bit.
2402 SDValue ShAmt = DAG.getConstant(VT.getSizeInBits() - 1, DL, MVT::i32);
2403 SDValue Shl = DAG.getNode(ISD::SHL, DL, VT, Result, ShAmt);
2404 return DAG.getNode(ISD::SRA, DL, VT, Shl, ShAmt);
2408 SDValue Ops[] = {TrueOp, FalseOp, DAG.getConstant(C.CCValid, DL, MVT::i32),
2409 DAG.getConstant(C.CCMask, DL, MVT::i32), Glue};
2411 SDVTList VTs = DAG.getVTList(Op.getValueType(), MVT::Glue);
2412 return DAG.getNode(SystemZISD::SELECT_CCMASK, DL, VTs, Ops);
2415 SDValue SystemZTargetLowering::lowerGlobalAddress(GlobalAddressSDNode *Node,
2416 SelectionDAG &DAG) const {
2418 const GlobalValue *GV = Node->getGlobal();
2419 int64_t Offset = Node->getOffset();
2420 EVT PtrVT = getPointerTy(DAG.getDataLayout());
2421 Reloc::Model RM = DAG.getTarget().getRelocationModel();
2422 CodeModel::Model CM = DAG.getTarget().getCodeModel();
2425 if (Subtarget.isPC32DBLSymbol(GV, RM, CM)) {
2426 // Assign anchors at 1<<12 byte boundaries.
2427 uint64_t Anchor = Offset & ~uint64_t(0xfff);
2428 Result = DAG.getTargetGlobalAddress(GV, DL, PtrVT, Anchor);
2429 Result = DAG.getNode(SystemZISD::PCREL_WRAPPER, DL, PtrVT, Result);
2431 // The offset can be folded into the address if it is aligned to a halfword.
2433 if (Offset != 0 && (Offset & 1) == 0) {
2434 SDValue Full = DAG.getTargetGlobalAddress(GV, DL, PtrVT, Anchor + Offset);
2435 Result = DAG.getNode(SystemZISD::PCREL_OFFSET, DL, PtrVT, Full, Result);
2439 Result = DAG.getTargetGlobalAddress(GV, DL, PtrVT, 0, SystemZII::MO_GOT);
2440 Result = DAG.getNode(SystemZISD::PCREL_WRAPPER, DL, PtrVT, Result);
2441 Result = DAG.getLoad(PtrVT, DL, DAG.getEntryNode(), Result,
2442 MachinePointerInfo::getGOT(DAG.getMachineFunction()),
2443 false, false, false, 0);
2446 // If there was a non-zero offset that we didn't fold, create an explicit
2449 Result = DAG.getNode(ISD::ADD, DL, PtrVT, Result,
2450 DAG.getConstant(Offset, DL, PtrVT));
2455 SDValue SystemZTargetLowering::lowerTLSGetOffset(GlobalAddressSDNode *Node,
2458 SDValue GOTOffset) const {
2460 EVT PtrVT = getPointerTy(DAG.getDataLayout());
2461 SDValue Chain = DAG.getEntryNode();
2464 // __tls_get_offset takes the GOT offset in %r2 and the GOT in %r12.
2465 SDValue GOT = DAG.getGLOBAL_OFFSET_TABLE(PtrVT);
2466 Chain = DAG.getCopyToReg(Chain, DL, SystemZ::R12D, GOT, Glue);
2467 Glue = Chain.getValue(1);
2468 Chain = DAG.getCopyToReg(Chain, DL, SystemZ::R2D, GOTOffset, Glue);
2469 Glue = Chain.getValue(1);
2471 // The first call operand is the chain and the second is the TLS symbol.
2472 SmallVector<SDValue, 8> Ops;
2473 Ops.push_back(Chain);
2474 Ops.push_back(DAG.getTargetGlobalAddress(Node->getGlobal(), DL,
2475 Node->getValueType(0),
2478 // Add argument registers to the end of the list so that they are
2479 // known live into the call.
2480 Ops.push_back(DAG.getRegister(SystemZ::R2D, PtrVT));
2481 Ops.push_back(DAG.getRegister(SystemZ::R12D, PtrVT));
2483 // Add a register mask operand representing the call-preserved registers.
2484 const TargetRegisterInfo *TRI = Subtarget.getRegisterInfo();
2485 const uint32_t *Mask =
2486 TRI->getCallPreservedMask(DAG.getMachineFunction(), CallingConv::C);
2487 assert(Mask && "Missing call preserved mask for calling convention");
2488 Ops.push_back(DAG.getRegisterMask(Mask));
2490 // Glue the call to the argument copies.
2491 Ops.push_back(Glue);
2494 SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
2495 Chain = DAG.getNode(Opcode, DL, NodeTys, Ops);
2496 Glue = Chain.getValue(1);
2498 // Copy the return value from %r2.
2499 return DAG.getCopyFromReg(Chain, DL, SystemZ::R2D, PtrVT, Glue);
2502 SDValue SystemZTargetLowering::lowerGlobalTLSAddress(GlobalAddressSDNode *Node,
2503 SelectionDAG &DAG) const {
2504 if (DAG.getTarget().Options.EmulatedTLS)
2505 return LowerToTLSEmulatedModel(Node, DAG);
2507 const GlobalValue *GV = Node->getGlobal();
2508 EVT PtrVT = getPointerTy(DAG.getDataLayout());
2509 TLSModel::Model model = DAG.getTarget().getTLSModel(GV);
2511 // The high part of the thread pointer is in access register 0.
2512 SDValue TPHi = DAG.getNode(SystemZISD::EXTRACT_ACCESS, DL, MVT::i32,
2513 DAG.getConstant(0, DL, MVT::i32));
2514 TPHi = DAG.getNode(ISD::ANY_EXTEND, DL, PtrVT, TPHi);
2516 // The low part of the thread pointer is in access register 1.
2517 SDValue TPLo = DAG.getNode(SystemZISD::EXTRACT_ACCESS, DL, MVT::i32,
2518 DAG.getConstant(1, DL, MVT::i32));
2519 TPLo = DAG.getNode(ISD::ZERO_EXTEND, DL, PtrVT, TPLo);
2521 // Merge them into a single 64-bit address.
2522 SDValue TPHiShifted = DAG.getNode(ISD::SHL, DL, PtrVT, TPHi,
2523 DAG.getConstant(32, DL, PtrVT));
2524 SDValue TP = DAG.getNode(ISD::OR, DL, PtrVT, TPHiShifted, TPLo);
2526 // Get the offset of GA from the thread pointer, based on the TLS model.
2529 case TLSModel::GeneralDynamic: {
2530 // Load the GOT offset of the tls_index (module ID / per-symbol offset).
2531 SystemZConstantPoolValue *CPV =
2532 SystemZConstantPoolValue::Create(GV, SystemZCP::TLSGD);
2534 Offset = DAG.getConstantPool(CPV, PtrVT, 8);
2535 Offset = DAG.getLoad(
2536 PtrVT, DL, DAG.getEntryNode(), Offset,
2537 MachinePointerInfo::getConstantPool(DAG.getMachineFunction()), false,
2540 // Call __tls_get_offset to retrieve the offset.
2541 Offset = lowerTLSGetOffset(Node, DAG, SystemZISD::TLS_GDCALL, Offset);
2545 case TLSModel::LocalDynamic: {
2546 // Load the GOT offset of the module ID.
2547 SystemZConstantPoolValue *CPV =
2548 SystemZConstantPoolValue::Create(GV, SystemZCP::TLSLDM);
2550 Offset = DAG.getConstantPool(CPV, PtrVT, 8);
2551 Offset = DAG.getLoad(
2552 PtrVT, DL, DAG.getEntryNode(), Offset,
2553 MachinePointerInfo::getConstantPool(DAG.getMachineFunction()), false,
2556 // Call __tls_get_offset to retrieve the module base offset.
2557 Offset = lowerTLSGetOffset(Node, DAG, SystemZISD::TLS_LDCALL, Offset);
2559 // Note: The SystemZLDCleanupPass will remove redundant computations
2560 // of the module base offset. Count total number of local-dynamic
2561 // accesses to trigger execution of that pass.
2562 SystemZMachineFunctionInfo* MFI =
2563 DAG.getMachineFunction().getInfo<SystemZMachineFunctionInfo>();
2564 MFI->incNumLocalDynamicTLSAccesses();
2566 // Add the per-symbol offset.
2567 CPV = SystemZConstantPoolValue::Create(GV, SystemZCP::DTPOFF);
2569 SDValue DTPOffset = DAG.getConstantPool(CPV, PtrVT, 8);
2570 DTPOffset = DAG.getLoad(
2571 PtrVT, DL, DAG.getEntryNode(), DTPOffset,
2572 MachinePointerInfo::getConstantPool(DAG.getMachineFunction()), false,
2575 Offset = DAG.getNode(ISD::ADD, DL, PtrVT, Offset, DTPOffset);
2579 case TLSModel::InitialExec: {
2580 // Load the offset from the GOT.
2581 Offset = DAG.getTargetGlobalAddress(GV, DL, PtrVT, 0,
2582 SystemZII::MO_INDNTPOFF);
2583 Offset = DAG.getNode(SystemZISD::PCREL_WRAPPER, DL, PtrVT, Offset);
2584 Offset = DAG.getLoad(PtrVT, DL, DAG.getEntryNode(), Offset,
2585 MachinePointerInfo::getGOT(DAG.getMachineFunction()),
2586 false, false, false, 0);
2590 case TLSModel::LocalExec: {
2591 // Force the offset into the constant pool and load it from there.
2592 SystemZConstantPoolValue *CPV =
2593 SystemZConstantPoolValue::Create(GV, SystemZCP::NTPOFF);
2595 Offset = DAG.getConstantPool(CPV, PtrVT, 8);
2596 Offset = DAG.getLoad(
2597 PtrVT, DL, DAG.getEntryNode(), Offset,
2598 MachinePointerInfo::getConstantPool(DAG.getMachineFunction()), false,
2604 // Add the base and offset together.
2605 return DAG.getNode(ISD::ADD, DL, PtrVT, TP, Offset);
2608 SDValue SystemZTargetLowering::lowerBlockAddress(BlockAddressSDNode *Node,
2609 SelectionDAG &DAG) const {
2611 const BlockAddress *BA = Node->getBlockAddress();
2612 int64_t Offset = Node->getOffset();
2613 EVT PtrVT = getPointerTy(DAG.getDataLayout());
2615 SDValue Result = DAG.getTargetBlockAddress(BA, PtrVT, Offset);
2616 Result = DAG.getNode(SystemZISD::PCREL_WRAPPER, DL, PtrVT, Result);
2620 SDValue SystemZTargetLowering::lowerJumpTable(JumpTableSDNode *JT,
2621 SelectionDAG &DAG) const {
2623 EVT PtrVT = getPointerTy(DAG.getDataLayout());
2624 SDValue Result = DAG.getTargetJumpTable(JT->getIndex(), PtrVT);
2626 // Use LARL to load the address of the table.
2627 return DAG.getNode(SystemZISD::PCREL_WRAPPER, DL, PtrVT, Result);
2630 SDValue SystemZTargetLowering::lowerConstantPool(ConstantPoolSDNode *CP,
2631 SelectionDAG &DAG) const {
2633 EVT PtrVT = getPointerTy(DAG.getDataLayout());
2636 if (CP->isMachineConstantPoolEntry())
2637 Result = DAG.getTargetConstantPool(CP->getMachineCPVal(), PtrVT,
2638 CP->getAlignment());
2640 Result = DAG.getTargetConstantPool(CP->getConstVal(), PtrVT,
2641 CP->getAlignment(), CP->getOffset());
2643 // Use LARL to load the address of the constant pool entry.
2644 return DAG.getNode(SystemZISD::PCREL_WRAPPER, DL, PtrVT, Result);
2647 SDValue SystemZTargetLowering::lowerBITCAST(SDValue Op,
2648 SelectionDAG &DAG) const {
2650 SDValue In = Op.getOperand(0);
2651 EVT InVT = In.getValueType();
2652 EVT ResVT = Op.getValueType();
2654 // Convert loads directly. This is normally done by DAGCombiner,
2655 // but we need this case for bitcasts that are created during lowering
2656 // and which are then lowered themselves.
2657 if (auto *LoadN = dyn_cast<LoadSDNode>(In))
2658 return DAG.getLoad(ResVT, DL, LoadN->getChain(), LoadN->getBasePtr(),
2659 LoadN->getMemOperand());
2661 if (InVT == MVT::i32 && ResVT == MVT::f32) {
2663 if (Subtarget.hasHighWord()) {
2664 SDNode *U64 = DAG.getMachineNode(TargetOpcode::IMPLICIT_DEF, DL,
2666 In64 = DAG.getTargetInsertSubreg(SystemZ::subreg_h32, DL,
2667 MVT::i64, SDValue(U64, 0), In);
2669 In64 = DAG.getNode(ISD::ANY_EXTEND, DL, MVT::i64, In);
2670 In64 = DAG.getNode(ISD::SHL, DL, MVT::i64, In64,
2671 DAG.getConstant(32, DL, MVT::i64));
2673 SDValue Out64 = DAG.getNode(ISD::BITCAST, DL, MVT::f64, In64);
2674 return DAG.getTargetExtractSubreg(SystemZ::subreg_r32,
2675 DL, MVT::f32, Out64);
2677 if (InVT == MVT::f32 && ResVT == MVT::i32) {
2678 SDNode *U64 = DAG.getMachineNode(TargetOpcode::IMPLICIT_DEF, DL, MVT::f64);
2679 SDValue In64 = DAG.getTargetInsertSubreg(SystemZ::subreg_r32, DL,
2680 MVT::f64, SDValue(U64, 0), In);
2681 SDValue Out64 = DAG.getNode(ISD::BITCAST, DL, MVT::i64, In64);
2682 if (Subtarget.hasHighWord())
2683 return DAG.getTargetExtractSubreg(SystemZ::subreg_h32, DL,
2685 SDValue Shift = DAG.getNode(ISD::SRL, DL, MVT::i64, Out64,
2686 DAG.getConstant(32, DL, MVT::i64));
2687 return DAG.getNode(ISD::TRUNCATE, DL, MVT::i32, Shift);
2689 llvm_unreachable("Unexpected bitcast combination");
2692 SDValue SystemZTargetLowering::lowerVASTART(SDValue Op,
2693 SelectionDAG &DAG) const {
2694 MachineFunction &MF = DAG.getMachineFunction();
2695 SystemZMachineFunctionInfo *FuncInfo =
2696 MF.getInfo<SystemZMachineFunctionInfo>();
2697 EVT PtrVT = getPointerTy(DAG.getDataLayout());
2699 SDValue Chain = Op.getOperand(0);
2700 SDValue Addr = Op.getOperand(1);
2701 const Value *SV = cast<SrcValueSDNode>(Op.getOperand(2))->getValue();
2704 // The initial values of each field.
2705 const unsigned NumFields = 4;
2706 SDValue Fields[NumFields] = {
2707 DAG.getConstant(FuncInfo->getVarArgsFirstGPR(), DL, PtrVT),
2708 DAG.getConstant(FuncInfo->getVarArgsFirstFPR(), DL, PtrVT),
2709 DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(), PtrVT),
2710 DAG.getFrameIndex(FuncInfo->getRegSaveFrameIndex(), PtrVT)
2713 // Store each field into its respective slot.
2714 SDValue MemOps[NumFields];
2715 unsigned Offset = 0;
2716 for (unsigned I = 0; I < NumFields; ++I) {
2717 SDValue FieldAddr = Addr;
2719 FieldAddr = DAG.getNode(ISD::ADD, DL, PtrVT, FieldAddr,
2720 DAG.getIntPtrConstant(Offset, DL));
2721 MemOps[I] = DAG.getStore(Chain, DL, Fields[I], FieldAddr,
2722 MachinePointerInfo(SV, Offset),
2726 return DAG.getNode(ISD::TokenFactor, DL, MVT::Other, MemOps);
2729 SDValue SystemZTargetLowering::lowerVACOPY(SDValue Op,
2730 SelectionDAG &DAG) const {
2731 SDValue Chain = Op.getOperand(0);
2732 SDValue DstPtr = Op.getOperand(1);
2733 SDValue SrcPtr = Op.getOperand(2);
2734 const Value *DstSV = cast<SrcValueSDNode>(Op.getOperand(3))->getValue();
2735 const Value *SrcSV = cast<SrcValueSDNode>(Op.getOperand(4))->getValue();
2738 return DAG.getMemcpy(Chain, DL, DstPtr, SrcPtr, DAG.getIntPtrConstant(32, DL),
2739 /*Align*/8, /*isVolatile*/false, /*AlwaysInline*/false,
2740 /*isTailCall*/false,
2741 MachinePointerInfo(DstSV), MachinePointerInfo(SrcSV));
2744 SDValue SystemZTargetLowering::
2745 lowerDYNAMIC_STACKALLOC(SDValue Op, SelectionDAG &DAG) const {
2746 SDValue Chain = Op.getOperand(0);
2747 SDValue Size = Op.getOperand(1);
2750 unsigned SPReg = getStackPointerRegisterToSaveRestore();
2752 // Get a reference to the stack pointer.
2753 SDValue OldSP = DAG.getCopyFromReg(Chain, DL, SPReg, MVT::i64);
2755 // Get the new stack pointer value.
2756 SDValue NewSP = DAG.getNode(ISD::SUB, DL, MVT::i64, OldSP, Size);
2758 // Copy the new stack pointer back.
2759 Chain = DAG.getCopyToReg(Chain, DL, SPReg, NewSP);
2761 // The allocated data lives above the 160 bytes allocated for the standard
2762 // frame, plus any outgoing stack arguments. We don't know how much that
2763 // amounts to yet, so emit a special ADJDYNALLOC placeholder.
2764 SDValue ArgAdjust = DAG.getNode(SystemZISD::ADJDYNALLOC, DL, MVT::i64);
2765 SDValue Result = DAG.getNode(ISD::ADD, DL, MVT::i64, NewSP, ArgAdjust);
2767 SDValue Ops[2] = { Result, Chain };
2768 return DAG.getMergeValues(Ops, DL);
2771 SDValue SystemZTargetLowering::lowerSMUL_LOHI(SDValue Op,
2772 SelectionDAG &DAG) const {
2773 EVT VT = Op.getValueType();
2777 // Just do a normal 64-bit multiplication and extract the results.
2778 // We define this so that it can be used for constant division.
2779 lowerMUL_LOHI32(DAG, DL, ISD::SIGN_EXTEND, Op.getOperand(0),
2780 Op.getOperand(1), Ops[1], Ops[0]);
2782 // Do a full 128-bit multiplication based on UMUL_LOHI64:
2784 // (ll * rl) + ((lh * rl) << 64) + ((ll * rh) << 64)
2786 // but using the fact that the upper halves are either all zeros
2789 // (ll * rl) - ((lh & rl) << 64) - ((ll & rh) << 64)
2791 // and grouping the right terms together since they are quicker than the
2794 // (ll * rl) - (((lh & rl) + (ll & rh)) << 64)
2795 SDValue C63 = DAG.getConstant(63, DL, MVT::i64);
2796 SDValue LL = Op.getOperand(0);
2797 SDValue RL = Op.getOperand(1);
2798 SDValue LH = DAG.getNode(ISD::SRA, DL, VT, LL, C63);
2799 SDValue RH = DAG.getNode(ISD::SRA, DL, VT, RL, C63);
2800 // UMUL_LOHI64 returns the low result in the odd register and the high
2801 // result in the even register. SMUL_LOHI is defined to return the
2802 // low half first, so the results are in reverse order.
2803 lowerGR128Binary(DAG, DL, VT, SystemZ::AEXT128_64, SystemZISD::UMUL_LOHI64,
2804 LL, RL, Ops[1], Ops[0]);
2805 SDValue NegLLTimesRH = DAG.getNode(ISD::AND, DL, VT, LL, RH);
2806 SDValue NegLHTimesRL = DAG.getNode(ISD::AND, DL, VT, LH, RL);
2807 SDValue NegSum = DAG.getNode(ISD::ADD, DL, VT, NegLLTimesRH, NegLHTimesRL);
2808 Ops[1] = DAG.getNode(ISD::SUB, DL, VT, Ops[1], NegSum);
2810 return DAG.getMergeValues(Ops, DL);
2813 SDValue SystemZTargetLowering::lowerUMUL_LOHI(SDValue Op,
2814 SelectionDAG &DAG) const {
2815 EVT VT = Op.getValueType();
2819 // Just do a normal 64-bit multiplication and extract the results.
2820 // We define this so that it can be used for constant division.
2821 lowerMUL_LOHI32(DAG, DL, ISD::ZERO_EXTEND, Op.getOperand(0),
2822 Op.getOperand(1), Ops[1], Ops[0]);
2824 // UMUL_LOHI64 returns the low result in the odd register and the high
2825 // result in the even register. UMUL_LOHI is defined to return the
2826 // low half first, so the results are in reverse order.
2827 lowerGR128Binary(DAG, DL, VT, SystemZ::AEXT128_64, SystemZISD::UMUL_LOHI64,
2828 Op.getOperand(0), Op.getOperand(1), Ops[1], Ops[0]);
2829 return DAG.getMergeValues(Ops, DL);
2832 SDValue SystemZTargetLowering::lowerSDIVREM(SDValue Op,
2833 SelectionDAG &DAG) const {
2834 SDValue Op0 = Op.getOperand(0);
2835 SDValue Op1 = Op.getOperand(1);
2836 EVT VT = Op.getValueType();
2840 // We use DSGF for 32-bit division.
2842 Op0 = DAG.getNode(ISD::SIGN_EXTEND, DL, MVT::i64, Op0);
2843 Opcode = SystemZISD::SDIVREM32;
2844 } else if (DAG.ComputeNumSignBits(Op1) > 32) {
2845 Op1 = DAG.getNode(ISD::TRUNCATE, DL, MVT::i32, Op1);
2846 Opcode = SystemZISD::SDIVREM32;
2848 Opcode = SystemZISD::SDIVREM64;
2850 // DSG(F) takes a 64-bit dividend, so the even register in the GR128
2851 // input is "don't care". The instruction returns the remainder in
2852 // the even register and the quotient in the odd register.
2854 lowerGR128Binary(DAG, DL, VT, SystemZ::AEXT128_64, Opcode,
2855 Op0, Op1, Ops[1], Ops[0]);
2856 return DAG.getMergeValues(Ops, DL);
2859 SDValue SystemZTargetLowering::lowerUDIVREM(SDValue Op,
2860 SelectionDAG &DAG) const {
2861 EVT VT = Op.getValueType();
2864 // DL(G) uses a double-width dividend, so we need to clear the even
2865 // register in the GR128 input. The instruction returns the remainder
2866 // in the even register and the quotient in the odd register.
2869 lowerGR128Binary(DAG, DL, VT, SystemZ::ZEXT128_32, SystemZISD::UDIVREM32,
2870 Op.getOperand(0), Op.getOperand(1), Ops[1], Ops[0]);
2872 lowerGR128Binary(DAG, DL, VT, SystemZ::ZEXT128_64, SystemZISD::UDIVREM64,
2873 Op.getOperand(0), Op.getOperand(1), Ops[1], Ops[0]);
2874 return DAG.getMergeValues(Ops, DL);
2877 SDValue SystemZTargetLowering::lowerOR(SDValue Op, SelectionDAG &DAG) const {
2878 assert(Op.getValueType() == MVT::i64 && "Should be 64-bit operation");
2880 // Get the known-zero masks for each operand.
2881 SDValue Ops[] = { Op.getOperand(0), Op.getOperand(1) };
2882 APInt KnownZero[2], KnownOne[2];
2883 DAG.computeKnownBits(Ops[0], KnownZero[0], KnownOne[0]);
2884 DAG.computeKnownBits(Ops[1], KnownZero[1], KnownOne[1]);
2886 // See if the upper 32 bits of one operand and the lower 32 bits of the
2887 // other are known zero. They are the low and high operands respectively.
2888 uint64_t Masks[] = { KnownZero[0].getZExtValue(),
2889 KnownZero[1].getZExtValue() };
2891 if ((Masks[0] >> 32) == 0xffffffff && uint32_t(Masks[1]) == 0xffffffff)
2893 else if ((Masks[1] >> 32) == 0xffffffff && uint32_t(Masks[0]) == 0xffffffff)
2898 SDValue LowOp = Ops[Low];
2899 SDValue HighOp = Ops[High];
2901 // If the high part is a constant, we're better off using IILH.
2902 if (HighOp.getOpcode() == ISD::Constant)
2905 // If the low part is a constant that is outside the range of LHI,
2906 // then we're better off using IILF.
2907 if (LowOp.getOpcode() == ISD::Constant) {
2908 int64_t Value = int32_t(cast<ConstantSDNode>(LowOp)->getZExtValue());
2909 if (!isInt<16>(Value))
2913 // Check whether the high part is an AND that doesn't change the
2914 // high 32 bits and just masks out low bits. We can skip it if so.
2915 if (HighOp.getOpcode() == ISD::AND &&
2916 HighOp.getOperand(1).getOpcode() == ISD::Constant) {
2917 SDValue HighOp0 = HighOp.getOperand(0);
2918 uint64_t Mask = cast<ConstantSDNode>(HighOp.getOperand(1))->getZExtValue();
2919 if (DAG.MaskedValueIsZero(HighOp0, APInt(64, ~(Mask | 0xffffffff))))
2923 // Take advantage of the fact that all GR32 operations only change the
2924 // low 32 bits by truncating Low to an i32 and inserting it directly
2925 // using a subreg. The interesting cases are those where the truncation
2928 SDValue Low32 = DAG.getNode(ISD::TRUNCATE, DL, MVT::i32, LowOp);
2929 return DAG.getTargetInsertSubreg(SystemZ::subreg_l32, DL,
2930 MVT::i64, HighOp, Low32);
2933 SDValue SystemZTargetLowering::lowerCTPOP(SDValue Op,
2934 SelectionDAG &DAG) const {
2935 EVT VT = Op.getValueType();
2937 Op = Op.getOperand(0);
2939 // Handle vector types via VPOPCT.
2940 if (VT.isVector()) {
2941 Op = DAG.getNode(ISD::BITCAST, DL, MVT::v16i8, Op);
2942 Op = DAG.getNode(SystemZISD::POPCNT, DL, MVT::v16i8, Op);
2943 switch (VT.getVectorElementType().getSizeInBits()) {
2947 Op = DAG.getNode(ISD::BITCAST, DL, VT, Op);
2948 SDValue Shift = DAG.getConstant(8, DL, MVT::i32);
2949 SDValue Tmp = DAG.getNode(SystemZISD::VSHL_BY_SCALAR, DL, VT, Op, Shift);
2950 Op = DAG.getNode(ISD::ADD, DL, VT, Op, Tmp);
2951 Op = DAG.getNode(SystemZISD::VSRL_BY_SCALAR, DL, VT, Op, Shift);
2955 SDValue Tmp = DAG.getNode(SystemZISD::BYTE_MASK, DL, MVT::v16i8,
2956 DAG.getConstant(0, DL, MVT::i32));
2957 Op = DAG.getNode(SystemZISD::VSUM, DL, VT, Op, Tmp);
2961 SDValue Tmp = DAG.getNode(SystemZISD::BYTE_MASK, DL, MVT::v16i8,
2962 DAG.getConstant(0, DL, MVT::i32));
2963 Op = DAG.getNode(SystemZISD::VSUM, DL, MVT::v4i32, Op, Tmp);
2964 Op = DAG.getNode(SystemZISD::VSUM, DL, VT, Op, Tmp);
2968 llvm_unreachable("Unexpected type");
2973 // Get the known-zero mask for the operand.
2974 APInt KnownZero, KnownOne;
2975 DAG.computeKnownBits(Op, KnownZero, KnownOne);
2976 unsigned NumSignificantBits = (~KnownZero).getActiveBits();
2977 if (NumSignificantBits == 0)
2978 return DAG.getConstant(0, DL, VT);
2980 // Skip known-zero high parts of the operand.
2981 int64_t OrigBitSize = VT.getSizeInBits();
2982 int64_t BitSize = (int64_t)1 << Log2_32_Ceil(NumSignificantBits);
2983 BitSize = std::min(BitSize, OrigBitSize);
2985 // The POPCNT instruction counts the number of bits in each byte.
2986 Op = DAG.getNode(ISD::ANY_EXTEND, DL, MVT::i64, Op);
2987 Op = DAG.getNode(SystemZISD::POPCNT, DL, MVT::i64, Op);
2988 Op = DAG.getNode(ISD::TRUNCATE, DL, VT, Op);
2990 // Add up per-byte counts in a binary tree. All bits of Op at
2991 // position larger than BitSize remain zero throughout.
2992 for (int64_t I = BitSize / 2; I >= 8; I = I / 2) {
2993 SDValue Tmp = DAG.getNode(ISD::SHL, DL, VT, Op, DAG.getConstant(I, DL, VT));
2994 if (BitSize != OrigBitSize)
2995 Tmp = DAG.getNode(ISD::AND, DL, VT, Tmp,
2996 DAG.getConstant(((uint64_t)1 << BitSize) - 1, DL, VT));
2997 Op = DAG.getNode(ISD::ADD, DL, VT, Op, Tmp);
3000 // Extract overall result from high byte.
3002 Op = DAG.getNode(ISD::SRL, DL, VT, Op,
3003 DAG.getConstant(BitSize - 8, DL, VT));
3008 // Op is an atomic load. Lower it into a normal volatile load.
3009 SDValue SystemZTargetLowering::lowerATOMIC_LOAD(SDValue Op,
3010 SelectionDAG &DAG) const {
3011 auto *Node = cast<AtomicSDNode>(Op.getNode());
3012 return DAG.getExtLoad(ISD::EXTLOAD, SDLoc(Op), Op.getValueType(),
3013 Node->getChain(), Node->getBasePtr(),
3014 Node->getMemoryVT(), Node->getMemOperand());
3017 // Op is an atomic store. Lower it into a normal volatile store followed
3018 // by a serialization.
3019 SDValue SystemZTargetLowering::lowerATOMIC_STORE(SDValue Op,
3020 SelectionDAG &DAG) const {
3021 auto *Node = cast<AtomicSDNode>(Op.getNode());
3022 SDValue Chain = DAG.getTruncStore(Node->getChain(), SDLoc(Op), Node->getVal(),
3023 Node->getBasePtr(), Node->getMemoryVT(),
3024 Node->getMemOperand());
3025 return SDValue(DAG.getMachineNode(SystemZ::Serialize, SDLoc(Op), MVT::Other,
3029 // Op is an 8-, 16-bit or 32-bit ATOMIC_LOAD_* operation. Lower the first
3030 // two into the fullword ATOMIC_LOADW_* operation given by Opcode.
3031 SDValue SystemZTargetLowering::lowerATOMIC_LOAD_OP(SDValue Op,
3033 unsigned Opcode) const {
3034 auto *Node = cast<AtomicSDNode>(Op.getNode());
3036 // 32-bit operations need no code outside the main loop.
3037 EVT NarrowVT = Node->getMemoryVT();
3038 EVT WideVT = MVT::i32;
3039 if (NarrowVT == WideVT)
3042 int64_t BitSize = NarrowVT.getSizeInBits();
3043 SDValue ChainIn = Node->getChain();
3044 SDValue Addr = Node->getBasePtr();
3045 SDValue Src2 = Node->getVal();
3046 MachineMemOperand *MMO = Node->getMemOperand();
3048 EVT PtrVT = Addr.getValueType();
3050 // Convert atomic subtracts of constants into additions.
3051 if (Opcode == SystemZISD::ATOMIC_LOADW_SUB)
3052 if (auto *Const = dyn_cast<ConstantSDNode>(Src2)) {
3053 Opcode = SystemZISD::ATOMIC_LOADW_ADD;
3054 Src2 = DAG.getConstant(-Const->getSExtValue(), DL, Src2.getValueType());
3057 // Get the address of the containing word.
3058 SDValue AlignedAddr = DAG.getNode(ISD::AND, DL, PtrVT, Addr,
3059 DAG.getConstant(-4, DL, PtrVT));
3061 // Get the number of bits that the word must be rotated left in order
3062 // to bring the field to the top bits of a GR32.
3063 SDValue BitShift = DAG.getNode(ISD::SHL, DL, PtrVT, Addr,
3064 DAG.getConstant(3, DL, PtrVT));
3065 BitShift = DAG.getNode(ISD::TRUNCATE, DL, WideVT, BitShift);
3067 // Get the complementing shift amount, for rotating a field in the top
3068 // bits back to its proper position.
3069 SDValue NegBitShift = DAG.getNode(ISD::SUB, DL, WideVT,
3070 DAG.getConstant(0, DL, WideVT), BitShift);
3072 // Extend the source operand to 32 bits and prepare it for the inner loop.
3073 // ATOMIC_SWAPW uses RISBG to rotate the field left, but all other
3074 // operations require the source to be shifted in advance. (This shift
3075 // can be folded if the source is constant.) For AND and NAND, the lower
3076 // bits must be set, while for other opcodes they should be left clear.
3077 if (Opcode != SystemZISD::ATOMIC_SWAPW)
3078 Src2 = DAG.getNode(ISD::SHL, DL, WideVT, Src2,
3079 DAG.getConstant(32 - BitSize, DL, WideVT));
3080 if (Opcode == SystemZISD::ATOMIC_LOADW_AND ||
3081 Opcode == SystemZISD::ATOMIC_LOADW_NAND)
3082 Src2 = DAG.getNode(ISD::OR, DL, WideVT, Src2,
3083 DAG.getConstant(uint32_t(-1) >> BitSize, DL, WideVT));
3085 // Construct the ATOMIC_LOADW_* node.
3086 SDVTList VTList = DAG.getVTList(WideVT, MVT::Other);
3087 SDValue Ops[] = { ChainIn, AlignedAddr, Src2, BitShift, NegBitShift,
3088 DAG.getConstant(BitSize, DL, WideVT) };
3089 SDValue AtomicOp = DAG.getMemIntrinsicNode(Opcode, DL, VTList, Ops,
3092 // Rotate the result of the final CS so that the field is in the lower
3093 // bits of a GR32, then truncate it.
3094 SDValue ResultShift = DAG.getNode(ISD::ADD, DL, WideVT, BitShift,
3095 DAG.getConstant(BitSize, DL, WideVT));
3096 SDValue Result = DAG.getNode(ISD::ROTL, DL, WideVT, AtomicOp, ResultShift);
3098 SDValue RetOps[2] = { Result, AtomicOp.getValue(1) };
3099 return DAG.getMergeValues(RetOps, DL);
3102 // Op is an ATOMIC_LOAD_SUB operation. Lower 8- and 16-bit operations
3103 // into ATOMIC_LOADW_SUBs and decide whether to convert 32- and 64-bit
3104 // operations into additions.
3105 SDValue SystemZTargetLowering::lowerATOMIC_LOAD_SUB(SDValue Op,
3106 SelectionDAG &DAG) const {
3107 auto *Node = cast<AtomicSDNode>(Op.getNode());
3108 EVT MemVT = Node->getMemoryVT();
3109 if (MemVT == MVT::i32 || MemVT == MVT::i64) {
3110 // A full-width operation.
3111 assert(Op.getValueType() == MemVT && "Mismatched VTs");
3112 SDValue Src2 = Node->getVal();
3116 if (auto *Op2 = dyn_cast<ConstantSDNode>(Src2)) {
3117 // Use an addition if the operand is constant and either LAA(G) is
3118 // available or the negative value is in the range of A(G)FHI.
3119 int64_t Value = (-Op2->getAPIntValue()).getSExtValue();
3120 if (isInt<32>(Value) || Subtarget.hasInterlockedAccess1())
3121 NegSrc2 = DAG.getConstant(Value, DL, MemVT);
3122 } else if (Subtarget.hasInterlockedAccess1())
3123 // Use LAA(G) if available.
3124 NegSrc2 = DAG.getNode(ISD::SUB, DL, MemVT, DAG.getConstant(0, DL, MemVT),
3127 if (NegSrc2.getNode())
3128 return DAG.getAtomic(ISD::ATOMIC_LOAD_ADD, DL, MemVT,
3129 Node->getChain(), Node->getBasePtr(), NegSrc2,
3130 Node->getMemOperand(), Node->getOrdering(),
3131 Node->getSynchScope());
3133 // Use the node as-is.
3137 return lowerATOMIC_LOAD_OP(Op, DAG, SystemZISD::ATOMIC_LOADW_SUB);
3140 // Node is an 8- or 16-bit ATOMIC_CMP_SWAP operation. Lower the first two
3141 // into a fullword ATOMIC_CMP_SWAPW operation.
3142 SDValue SystemZTargetLowering::lowerATOMIC_CMP_SWAP(SDValue Op,
3143 SelectionDAG &DAG) const {
3144 auto *Node = cast<AtomicSDNode>(Op.getNode());
3146 // We have native support for 32-bit compare and swap.
3147 EVT NarrowVT = Node->getMemoryVT();
3148 EVT WideVT = MVT::i32;
3149 if (NarrowVT == WideVT)
3152 int64_t BitSize = NarrowVT.getSizeInBits();
3153 SDValue ChainIn = Node->getOperand(0);
3154 SDValue Addr = Node->getOperand(1);
3155 SDValue CmpVal = Node->getOperand(2);
3156 SDValue SwapVal = Node->getOperand(3);
3157 MachineMemOperand *MMO = Node->getMemOperand();
3159 EVT PtrVT = Addr.getValueType();
3161 // Get the address of the containing word.
3162 SDValue AlignedAddr = DAG.getNode(ISD::AND, DL, PtrVT, Addr,
3163 DAG.getConstant(-4, DL, PtrVT));
3165 // Get the number of bits that the word must be rotated left in order
3166 // to bring the field to the top bits of a GR32.
3167 SDValue BitShift = DAG.getNode(ISD::SHL, DL, PtrVT, Addr,
3168 DAG.getConstant(3, DL, PtrVT));
3169 BitShift = DAG.getNode(ISD::TRUNCATE, DL, WideVT, BitShift);
3171 // Get the complementing shift amount, for rotating a field in the top
3172 // bits back to its proper position.
3173 SDValue NegBitShift = DAG.getNode(ISD::SUB, DL, WideVT,
3174 DAG.getConstant(0, DL, WideVT), BitShift);
3176 // Construct the ATOMIC_CMP_SWAPW node.
3177 SDVTList VTList = DAG.getVTList(WideVT, MVT::Other);
3178 SDValue Ops[] = { ChainIn, AlignedAddr, CmpVal, SwapVal, BitShift,
3179 NegBitShift, DAG.getConstant(BitSize, DL, WideVT) };
3180 SDValue AtomicOp = DAG.getMemIntrinsicNode(SystemZISD::ATOMIC_CMP_SWAPW, DL,
3181 VTList, Ops, NarrowVT, MMO);
3185 SDValue SystemZTargetLowering::lowerSTACKSAVE(SDValue Op,
3186 SelectionDAG &DAG) const {
3187 MachineFunction &MF = DAG.getMachineFunction();
3188 MF.getInfo<SystemZMachineFunctionInfo>()->setManipulatesSP(true);
3189 return DAG.getCopyFromReg(Op.getOperand(0), SDLoc(Op),
3190 SystemZ::R15D, Op.getValueType());
3193 SDValue SystemZTargetLowering::lowerSTACKRESTORE(SDValue Op,
3194 SelectionDAG &DAG) const {
3195 MachineFunction &MF = DAG.getMachineFunction();
3196 MF.getInfo<SystemZMachineFunctionInfo>()->setManipulatesSP(true);
3197 return DAG.getCopyToReg(Op.getOperand(0), SDLoc(Op),
3198 SystemZ::R15D, Op.getOperand(1));
3201 SDValue SystemZTargetLowering::lowerPREFETCH(SDValue Op,
3202 SelectionDAG &DAG) const {
3203 bool IsData = cast<ConstantSDNode>(Op.getOperand(4))->getZExtValue();
3205 // Just preserve the chain.
3206 return Op.getOperand(0);
3209 bool IsWrite = cast<ConstantSDNode>(Op.getOperand(2))->getZExtValue();
3210 unsigned Code = IsWrite ? SystemZ::PFD_WRITE : SystemZ::PFD_READ;
3211 auto *Node = cast<MemIntrinsicSDNode>(Op.getNode());
3214 DAG.getConstant(Code, DL, MVT::i32),
3217 return DAG.getMemIntrinsicNode(SystemZISD::PREFETCH, DL,
3218 Node->getVTList(), Ops,
3219 Node->getMemoryVT(), Node->getMemOperand());
3222 // Return an i32 that contains the value of CC immediately after After,
3223 // whose final operand must be MVT::Glue.
3224 static SDValue getCCResult(SelectionDAG &DAG, SDNode *After) {
3226 SDValue Glue = SDValue(After, After->getNumValues() - 1);
3227 SDValue IPM = DAG.getNode(SystemZISD::IPM, DL, MVT::i32, Glue);
3228 return DAG.getNode(ISD::SRL, DL, MVT::i32, IPM,
3229 DAG.getConstant(SystemZ::IPM_CC, DL, MVT::i32));
3233 SystemZTargetLowering::lowerINTRINSIC_W_CHAIN(SDValue Op,
3234 SelectionDAG &DAG) const {
3235 unsigned Opcode, CCValid;
3236 if (isIntrinsicWithCCAndChain(Op, Opcode, CCValid)) {
3237 assert(Op->getNumValues() == 2 && "Expected only CC result and chain");
3238 SDValue Glued = emitIntrinsicWithChainAndGlue(DAG, Op, Opcode);
3239 SDValue CC = getCCResult(DAG, Glued.getNode());
3240 DAG.ReplaceAllUsesOfValueWith(SDValue(Op.getNode(), 0), CC);
3248 SystemZTargetLowering::lowerINTRINSIC_WO_CHAIN(SDValue Op,
3249 SelectionDAG &DAG) const {
3250 unsigned Opcode, CCValid;
3251 if (isIntrinsicWithCC(Op, Opcode, CCValid)) {
3252 SDValue Glued = emitIntrinsicWithGlue(DAG, Op, Opcode);
3253 SDValue CC = getCCResult(DAG, Glued.getNode());
3254 if (Op->getNumValues() == 1)
3256 assert(Op->getNumValues() == 2 && "Expected a CC and non-CC result");
3257 return DAG.getNode(ISD::MERGE_VALUES, SDLoc(Op), Op->getVTList(), Glued,
3261 unsigned Id = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
3263 case Intrinsic::s390_vpdi:
3264 return DAG.getNode(SystemZISD::PERMUTE_DWORDS, SDLoc(Op), Op.getValueType(),
3265 Op.getOperand(1), Op.getOperand(2), Op.getOperand(3));
3267 case Intrinsic::s390_vperm:
3268 return DAG.getNode(SystemZISD::PERMUTE, SDLoc(Op), Op.getValueType(),
3269 Op.getOperand(1), Op.getOperand(2), Op.getOperand(3));
3271 case Intrinsic::s390_vuphb:
3272 case Intrinsic::s390_vuphh:
3273 case Intrinsic::s390_vuphf:
3274 return DAG.getNode(SystemZISD::UNPACK_HIGH, SDLoc(Op), Op.getValueType(),
3277 case Intrinsic::s390_vuplhb:
3278 case Intrinsic::s390_vuplhh:
3279 case Intrinsic::s390_vuplhf:
3280 return DAG.getNode(SystemZISD::UNPACKL_HIGH, SDLoc(Op), Op.getValueType(),
3283 case Intrinsic::s390_vuplb:
3284 case Intrinsic::s390_vuplhw:
3285 case Intrinsic::s390_vuplf:
3286 return DAG.getNode(SystemZISD::UNPACK_LOW, SDLoc(Op), Op.getValueType(),
3289 case Intrinsic::s390_vupllb:
3290 case Intrinsic::s390_vupllh:
3291 case Intrinsic::s390_vupllf:
3292 return DAG.getNode(SystemZISD::UNPACKL_LOW, SDLoc(Op), Op.getValueType(),
3295 case Intrinsic::s390_vsumb:
3296 case Intrinsic::s390_vsumh:
3297 case Intrinsic::s390_vsumgh:
3298 case Intrinsic::s390_vsumgf:
3299 case Intrinsic::s390_vsumqf:
3300 case Intrinsic::s390_vsumqg:
3301 return DAG.getNode(SystemZISD::VSUM, SDLoc(Op), Op.getValueType(),
3302 Op.getOperand(1), Op.getOperand(2));
3309 // Says that SystemZISD operation Opcode can be used to perform the equivalent
3310 // of a VPERM with permute vector Bytes. If Opcode takes three operands,
3311 // Operand is the constant third operand, otherwise it is the number of
3312 // bytes in each element of the result.
3316 unsigned char Bytes[SystemZ::VectorBytes];
3320 static const Permute PermuteForms[] = {
3322 { SystemZISD::MERGE_HIGH, 8,
3323 { 0, 1, 2, 3, 4, 5, 6, 7, 16, 17, 18, 19, 20, 21, 22, 23 } },
3325 { SystemZISD::MERGE_HIGH, 4,
3326 { 0, 1, 2, 3, 16, 17, 18, 19, 4, 5, 6, 7, 20, 21, 22, 23 } },
3328 { SystemZISD::MERGE_HIGH, 2,
3329 { 0, 1, 16, 17, 2, 3, 18, 19, 4, 5, 20, 21, 6, 7, 22, 23 } },
3331 { SystemZISD::MERGE_HIGH, 1,
3332 { 0, 16, 1, 17, 2, 18, 3, 19, 4, 20, 5, 21, 6, 22, 7, 23 } },
3334 { SystemZISD::MERGE_LOW, 8,
3335 { 8, 9, 10, 11, 12, 13, 14, 15, 24, 25, 26, 27, 28, 29, 30, 31 } },
3337 { SystemZISD::MERGE_LOW, 4,
3338 { 8, 9, 10, 11, 24, 25, 26, 27, 12, 13, 14, 15, 28, 29, 30, 31 } },
3340 { SystemZISD::MERGE_LOW, 2,
3341 { 8, 9, 24, 25, 10, 11, 26, 27, 12, 13, 28, 29, 14, 15, 30, 31 } },
3343 { SystemZISD::MERGE_LOW, 1,
3344 { 8, 24, 9, 25, 10, 26, 11, 27, 12, 28, 13, 29, 14, 30, 15, 31 } },
3346 { SystemZISD::PACK, 4,
3347 { 4, 5, 6, 7, 12, 13, 14, 15, 20, 21, 22, 23, 28, 29, 30, 31 } },
3349 { SystemZISD::PACK, 2,
3350 { 2, 3, 6, 7, 10, 11, 14, 15, 18, 19, 22, 23, 26, 27, 30, 31 } },
3352 { SystemZISD::PACK, 1,
3353 { 1, 3, 5, 7, 9, 11, 13, 15, 17, 19, 21, 23, 25, 27, 29, 31 } },
3354 // VPDI V1, V2, 4 (low half of V1, high half of V2)
3355 { SystemZISD::PERMUTE_DWORDS, 4,
3356 { 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23 } },
3357 // VPDI V1, V2, 1 (high half of V1, low half of V2)
3358 { SystemZISD::PERMUTE_DWORDS, 1,
3359 { 0, 1, 2, 3, 4, 5, 6, 7, 24, 25, 26, 27, 28, 29, 30, 31 } }
3362 // Called after matching a vector shuffle against a particular pattern.
3363 // Both the original shuffle and the pattern have two vector operands.
3364 // OpNos[0] is the operand of the original shuffle that should be used for
3365 // operand 0 of the pattern, or -1 if operand 0 of the pattern can be anything.
3366 // OpNos[1] is the same for operand 1 of the pattern. Resolve these -1s and
3367 // set OpNo0 and OpNo1 to the shuffle operands that should actually be used
3368 // for operands 0 and 1 of the pattern.
3369 static bool chooseShuffleOpNos(int *OpNos, unsigned &OpNo0, unsigned &OpNo1) {
3373 OpNo0 = OpNo1 = OpNos[1];
3374 } else if (OpNos[1] < 0) {
3375 OpNo0 = OpNo1 = OpNos[0];
3383 // Bytes is a VPERM-like permute vector, except that -1 is used for
3384 // undefined bytes. Return true if the VPERM can be implemented using P.
3385 // When returning true set OpNo0 to the VPERM operand that should be
3386 // used for operand 0 of P and likewise OpNo1 for operand 1 of P.
3388 // For example, if swapping the VPERM operands allows P to match, OpNo0
3389 // will be 1 and OpNo1 will be 0. If instead Bytes only refers to one
3390 // operand, but rewriting it to use two duplicated operands allows it to
3391 // match P, then OpNo0 and OpNo1 will be the same.
3392 static bool matchPermute(const SmallVectorImpl<int> &Bytes, const Permute &P,
3393 unsigned &OpNo0, unsigned &OpNo1) {
3394 int OpNos[] = { -1, -1 };
3395 for (unsigned I = 0; I < SystemZ::VectorBytes; ++I) {
3398 // Make sure that the two permute vectors use the same suboperand
3399 // byte number. Only the operand numbers (the high bits) are
3400 // allowed to differ.
3401 if ((Elt ^ P.Bytes[I]) & (SystemZ::VectorBytes - 1))
3403 int ModelOpNo = P.Bytes[I] / SystemZ::VectorBytes;
3404 int RealOpNo = unsigned(Elt) / SystemZ::VectorBytes;
3405 // Make sure that the operand mappings are consistent with previous
3407 if (OpNos[ModelOpNo] == 1 - RealOpNo)
3409 OpNos[ModelOpNo] = RealOpNo;
3412 return chooseShuffleOpNos(OpNos, OpNo0, OpNo1);
3415 // As above, but search for a matching permute.
3416 static const Permute *matchPermute(const SmallVectorImpl<int> &Bytes,
3417 unsigned &OpNo0, unsigned &OpNo1) {
3418 for (auto &P : PermuteForms)
3419 if (matchPermute(Bytes, P, OpNo0, OpNo1))
3424 // Bytes is a VPERM-like permute vector, except that -1 is used for
3425 // undefined bytes. This permute is an operand of an outer permute.
3426 // See whether redistributing the -1 bytes gives a shuffle that can be
3427 // implemented using P. If so, set Transform to a VPERM-like permute vector
3428 // that, when applied to the result of P, gives the original permute in Bytes.
3429 static bool matchDoublePermute(const SmallVectorImpl<int> &Bytes,
3431 SmallVectorImpl<int> &Transform) {
3433 for (unsigned From = 0; From < SystemZ::VectorBytes; ++From) {
3434 int Elt = Bytes[From];
3436 // Byte number From of the result is undefined.
3437 Transform[From] = -1;
3439 while (P.Bytes[To] != Elt) {
3441 if (To == SystemZ::VectorBytes)
3444 Transform[From] = To;
3450 // As above, but search for a matching permute.
3451 static const Permute *matchDoublePermute(const SmallVectorImpl<int> &Bytes,
3452 SmallVectorImpl<int> &Transform) {
3453 for (auto &P : PermuteForms)
3454 if (matchDoublePermute(Bytes, P, Transform))
3459 // Convert the mask of the given VECTOR_SHUFFLE into a byte-level mask,
3460 // as if it had type vNi8.
3461 static void getVPermMask(ShuffleVectorSDNode *VSN,
3462 SmallVectorImpl<int> &Bytes) {
3463 EVT VT = VSN->getValueType(0);
3464 unsigned NumElements = VT.getVectorNumElements();
3465 unsigned BytesPerElement = VT.getVectorElementType().getStoreSize();
3466 Bytes.resize(NumElements * BytesPerElement, -1);
3467 for (unsigned I = 0; I < NumElements; ++I) {
3468 int Index = VSN->getMaskElt(I);
3470 for (unsigned J = 0; J < BytesPerElement; ++J)
3471 Bytes[I * BytesPerElement + J] = Index * BytesPerElement + J;
3475 // Bytes is a VPERM-like permute vector, except that -1 is used for
3476 // undefined bytes. See whether bytes [Start, Start + BytesPerElement) of
3477 // the result come from a contiguous sequence of bytes from one input.
3478 // Set Base to the selector for the first byte if so.
3479 static bool getShuffleInput(const SmallVectorImpl<int> &Bytes, unsigned Start,
3480 unsigned BytesPerElement, int &Base) {
3482 for (unsigned I = 0; I < BytesPerElement; ++I) {
3483 if (Bytes[Start + I] >= 0) {
3484 unsigned Elem = Bytes[Start + I];
3487 // Make sure the bytes would come from one input operand.
3488 if (unsigned(Base) % Bytes.size() + BytesPerElement > Bytes.size())
3490 } else if (unsigned(Base) != Elem - I)
3497 // Bytes is a VPERM-like permute vector, except that -1 is used for
3498 // undefined bytes. Return true if it can be performed using VSLDI.
3499 // When returning true, set StartIndex to the shift amount and OpNo0
3500 // and OpNo1 to the VPERM operands that should be used as the first
3501 // and second shift operand respectively.
3502 static bool isShlDoublePermute(const SmallVectorImpl<int> &Bytes,
3503 unsigned &StartIndex, unsigned &OpNo0,
3505 int OpNos[] = { -1, -1 };
3507 for (unsigned I = 0; I < 16; ++I) {
3508 int Index = Bytes[I];
3510 int ExpectedShift = (Index - I) % SystemZ::VectorBytes;
3511 int ModelOpNo = unsigned(ExpectedShift + I) / SystemZ::VectorBytes;
3512 int RealOpNo = unsigned(Index) / SystemZ::VectorBytes;
3514 Shift = ExpectedShift;
3515 else if (Shift != ExpectedShift)
3517 // Make sure that the operand mappings are consistent with previous
3519 if (OpNos[ModelOpNo] == 1 - RealOpNo)
3521 OpNos[ModelOpNo] = RealOpNo;
3525 return chooseShuffleOpNos(OpNos, OpNo0, OpNo1);
3528 // Create a node that performs P on operands Op0 and Op1, casting the
3529 // operands to the appropriate type. The type of the result is determined by P.
3530 static SDValue getPermuteNode(SelectionDAG &DAG, SDLoc DL,
3531 const Permute &P, SDValue Op0, SDValue Op1) {
3532 // VPDI (PERMUTE_DWORDS) always operates on v2i64s. The input
3533 // elements of a PACK are twice as wide as the outputs.
3534 unsigned InBytes = (P.Opcode == SystemZISD::PERMUTE_DWORDS ? 8 :
3535 P.Opcode == SystemZISD::PACK ? P.Operand * 2 :
3537 // Cast both operands to the appropriate type.
3538 MVT InVT = MVT::getVectorVT(MVT::getIntegerVT(InBytes * 8),
3539 SystemZ::VectorBytes / InBytes);
3540 Op0 = DAG.getNode(ISD::BITCAST, DL, InVT, Op0);
3541 Op1 = DAG.getNode(ISD::BITCAST, DL, InVT, Op1);
3543 if (P.Opcode == SystemZISD::PERMUTE_DWORDS) {
3544 SDValue Op2 = DAG.getConstant(P.Operand, DL, MVT::i32);
3545 Op = DAG.getNode(SystemZISD::PERMUTE_DWORDS, DL, InVT, Op0, Op1, Op2);
3546 } else if (P.Opcode == SystemZISD::PACK) {
3547 MVT OutVT = MVT::getVectorVT(MVT::getIntegerVT(P.Operand * 8),
3548 SystemZ::VectorBytes / P.Operand);
3549 Op = DAG.getNode(SystemZISD::PACK, DL, OutVT, Op0, Op1);
3551 Op = DAG.getNode(P.Opcode, DL, InVT, Op0, Op1);
3556 // Bytes is a VPERM-like permute vector, except that -1 is used for
3557 // undefined bytes. Implement it on operands Ops[0] and Ops[1] using
3559 static SDValue getGeneralPermuteNode(SelectionDAG &DAG, SDLoc DL, SDValue *Ops,
3560 const SmallVectorImpl<int> &Bytes) {
3561 for (unsigned I = 0; I < 2; ++I)
3562 Ops[I] = DAG.getNode(ISD::BITCAST, DL, MVT::v16i8, Ops[I]);
3564 // First see whether VSLDI can be used.
3565 unsigned StartIndex, OpNo0, OpNo1;
3566 if (isShlDoublePermute(Bytes, StartIndex, OpNo0, OpNo1))
3567 return DAG.getNode(SystemZISD::SHL_DOUBLE, DL, MVT::v16i8, Ops[OpNo0],
3568 Ops[OpNo1], DAG.getConstant(StartIndex, DL, MVT::i32));
3570 // Fall back on VPERM. Construct an SDNode for the permute vector.
3571 SDValue IndexNodes[SystemZ::VectorBytes];
3572 for (unsigned I = 0; I < SystemZ::VectorBytes; ++I)
3574 IndexNodes[I] = DAG.getConstant(Bytes[I], DL, MVT::i32);
3576 IndexNodes[I] = DAG.getUNDEF(MVT::i32);
3577 SDValue Op2 = DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v16i8, IndexNodes);
3578 return DAG.getNode(SystemZISD::PERMUTE, DL, MVT::v16i8, Ops[0], Ops[1], Op2);
3582 // Describes a general N-operand vector shuffle.
3583 struct GeneralShuffle {
3584 GeneralShuffle(EVT vt) : VT(vt) {}
3586 void add(SDValue, unsigned);
3587 SDValue getNode(SelectionDAG &, SDLoc);
3589 // The operands of the shuffle.
3590 SmallVector<SDValue, SystemZ::VectorBytes> Ops;
3592 // Index I is -1 if byte I of the result is undefined. Otherwise the
3593 // result comes from byte Bytes[I] % SystemZ::VectorBytes of operand
3594 // Bytes[I] / SystemZ::VectorBytes.
3595 SmallVector<int, SystemZ::VectorBytes> Bytes;
3597 // The type of the shuffle result.
3602 // Add an extra undefined element to the shuffle.
3603 void GeneralShuffle::addUndef() {
3604 unsigned BytesPerElement = VT.getVectorElementType().getStoreSize();
3605 for (unsigned I = 0; I < BytesPerElement; ++I)
3606 Bytes.push_back(-1);
3609 // Add an extra element to the shuffle, taking it from element Elem of Op.
3610 // A null Op indicates a vector input whose value will be calculated later;
3611 // there is at most one such input per shuffle and it always has the same
3612 // type as the result.
3613 void GeneralShuffle::add(SDValue Op, unsigned Elem) {
3614 unsigned BytesPerElement = VT.getVectorElementType().getStoreSize();
3616 // The source vector can have wider elements than the result,
3617 // either through an explicit TRUNCATE or because of type legalization.
3618 // We want the least significant part.
3619 EVT FromVT = Op.getNode() ? Op.getValueType() : VT;
3620 unsigned FromBytesPerElement = FromVT.getVectorElementType().getStoreSize();
3621 assert(FromBytesPerElement >= BytesPerElement &&
3622 "Invalid EXTRACT_VECTOR_ELT");
3623 unsigned Byte = ((Elem * FromBytesPerElement) % SystemZ::VectorBytes +
3624 (FromBytesPerElement - BytesPerElement));
3626 // Look through things like shuffles and bitcasts.
3627 while (Op.getNode()) {
3628 if (Op.getOpcode() == ISD::BITCAST)
3629 Op = Op.getOperand(0);
3630 else if (Op.getOpcode() == ISD::VECTOR_SHUFFLE && Op.hasOneUse()) {
3631 // See whether the bytes we need come from a contiguous part of one
3633 SmallVector<int, SystemZ::VectorBytes> OpBytes;
3634 getVPermMask(cast<ShuffleVectorSDNode>(Op), OpBytes);
3636 if (!getShuffleInput(OpBytes, Byte, BytesPerElement, NewByte))
3642 Op = Op.getOperand(unsigned(NewByte) / SystemZ::VectorBytes);
3643 Byte = unsigned(NewByte) % SystemZ::VectorBytes;
3644 } else if (Op.getOpcode() == ISD::UNDEF) {
3651 // Make sure that the source of the extraction is in Ops.
3653 for (; OpNo < Ops.size(); ++OpNo)
3654 if (Ops[OpNo] == Op)
3656 if (OpNo == Ops.size())
3659 // Add the element to Bytes.
3660 unsigned Base = OpNo * SystemZ::VectorBytes + Byte;
3661 for (unsigned I = 0; I < BytesPerElement; ++I)
3662 Bytes.push_back(Base + I);
3665 // Return SDNodes for the completed shuffle.
3666 SDValue GeneralShuffle::getNode(SelectionDAG &DAG, SDLoc DL) {
3667 assert(Bytes.size() == SystemZ::VectorBytes && "Incomplete vector");
3669 if (Ops.size() == 0)
3670 return DAG.getUNDEF(VT);
3672 // Make sure that there are at least two shuffle operands.
3673 if (Ops.size() == 1)
3674 Ops.push_back(DAG.getUNDEF(MVT::v16i8));
3676 // Create a tree of shuffles, deferring root node until after the loop.
3677 // Try to redistribute the undefined elements of non-root nodes so that
3678 // the non-root shuffles match something like a pack or merge, then adjust
3679 // the parent node's permute vector to compensate for the new order.
3680 // Among other things, this copes with vectors like <2 x i16> that were
3681 // padded with undefined elements during type legalization.
3683 // In the best case this redistribution will lead to the whole tree
3684 // using packs and merges. It should rarely be a loss in other cases.
3685 unsigned Stride = 1;
3686 for (; Stride * 2 < Ops.size(); Stride *= 2) {
3687 for (unsigned I = 0; I < Ops.size() - Stride; I += Stride * 2) {
3688 SDValue SubOps[] = { Ops[I], Ops[I + Stride] };
3690 // Create a mask for just these two operands.
3691 SmallVector<int, SystemZ::VectorBytes> NewBytes(SystemZ::VectorBytes);
3692 for (unsigned J = 0; J < SystemZ::VectorBytes; ++J) {
3693 unsigned OpNo = unsigned(Bytes[J]) / SystemZ::VectorBytes;
3694 unsigned Byte = unsigned(Bytes[J]) % SystemZ::VectorBytes;
3697 else if (OpNo == I + Stride)
3698 NewBytes[J] = SystemZ::VectorBytes + Byte;
3702 // See if it would be better to reorganize NewMask to avoid using VPERM.
3703 SmallVector<int, SystemZ::VectorBytes> NewBytesMap(SystemZ::VectorBytes);
3704 if (const Permute *P = matchDoublePermute(NewBytes, NewBytesMap)) {
3705 Ops[I] = getPermuteNode(DAG, DL, *P, SubOps[0], SubOps[1]);
3706 // Applying NewBytesMap to Ops[I] gets back to NewBytes.
3707 for (unsigned J = 0; J < SystemZ::VectorBytes; ++J) {
3708 if (NewBytes[J] >= 0) {
3709 assert(unsigned(NewBytesMap[J]) < SystemZ::VectorBytes &&
3710 "Invalid double permute");
3711 Bytes[J] = I * SystemZ::VectorBytes + NewBytesMap[J];
3713 assert(NewBytesMap[J] < 0 && "Invalid double permute");
3716 // Just use NewBytes on the operands.
3717 Ops[I] = getGeneralPermuteNode(DAG, DL, SubOps, NewBytes);
3718 for (unsigned J = 0; J < SystemZ::VectorBytes; ++J)
3719 if (NewBytes[J] >= 0)
3720 Bytes[J] = I * SystemZ::VectorBytes + J;
3725 // Now we just have 2 inputs. Put the second operand in Ops[1].
3727 Ops[1] = Ops[Stride];
3728 for (unsigned I = 0; I < SystemZ::VectorBytes; ++I)
3729 if (Bytes[I] >= int(SystemZ::VectorBytes))
3730 Bytes[I] -= (Stride - 1) * SystemZ::VectorBytes;
3733 // Look for an instruction that can do the permute without resorting
3735 unsigned OpNo0, OpNo1;
3737 if (const Permute *P = matchPermute(Bytes, OpNo0, OpNo1))
3738 Op = getPermuteNode(DAG, DL, *P, Ops[OpNo0], Ops[OpNo1]);
3740 Op = getGeneralPermuteNode(DAG, DL, &Ops[0], Bytes);
3741 return DAG.getNode(ISD::BITCAST, DL, VT, Op);
3744 // Return true if the given BUILD_VECTOR is a scalar-to-vector conversion.
3745 static bool isScalarToVector(SDValue Op) {
3746 for (unsigned I = 1, E = Op.getNumOperands(); I != E; ++I)
3747 if (Op.getOperand(I).getOpcode() != ISD::UNDEF)
3752 // Return a vector of type VT that contains Value in the first element.
3753 // The other elements don't matter.
3754 static SDValue buildScalarToVector(SelectionDAG &DAG, SDLoc DL, EVT VT,
3756 // If we have a constant, replicate it to all elements and let the
3757 // BUILD_VECTOR lowering take care of it.
3758 if (Value.getOpcode() == ISD::Constant ||
3759 Value.getOpcode() == ISD::ConstantFP) {
3760 SmallVector<SDValue, 16> Ops(VT.getVectorNumElements(), Value);
3761 return DAG.getNode(ISD::BUILD_VECTOR, DL, VT, Ops);
3763 if (Value.getOpcode() == ISD::UNDEF)
3764 return DAG.getUNDEF(VT);
3765 return DAG.getNode(ISD::SCALAR_TO_VECTOR, DL, VT, Value);
3768 // Return a vector of type VT in which Op0 is in element 0 and Op1 is in
3769 // element 1. Used for cases in which replication is cheap.
3770 static SDValue buildMergeScalars(SelectionDAG &DAG, SDLoc DL, EVT VT,
3771 SDValue Op0, SDValue Op1) {
3772 if (Op0.getOpcode() == ISD::UNDEF) {
3773 if (Op1.getOpcode() == ISD::UNDEF)
3774 return DAG.getUNDEF(VT);
3775 return DAG.getNode(SystemZISD::REPLICATE, DL, VT, Op1);
3777 if (Op1.getOpcode() == ISD::UNDEF)
3778 return DAG.getNode(SystemZISD::REPLICATE, DL, VT, Op0);
3779 return DAG.getNode(SystemZISD::MERGE_HIGH, DL, VT,
3780 buildScalarToVector(DAG, DL, VT, Op0),
3781 buildScalarToVector(DAG, DL, VT, Op1));
3784 // Extend GPR scalars Op0 and Op1 to doublewords and return a v2i64
3786 static SDValue joinDwords(SelectionDAG &DAG, SDLoc DL, SDValue Op0,
3788 if (Op0.getOpcode() == ISD::UNDEF && Op1.getOpcode() == ISD::UNDEF)
3789 return DAG.getUNDEF(MVT::v2i64);
3790 // If one of the two inputs is undefined then replicate the other one,
3791 // in order to avoid using another register unnecessarily.
3792 if (Op0.getOpcode() == ISD::UNDEF)
3793 Op0 = Op1 = DAG.getNode(ISD::ANY_EXTEND, DL, MVT::i64, Op1);
3794 else if (Op1.getOpcode() == ISD::UNDEF)
3795 Op0 = Op1 = DAG.getNode(ISD::ANY_EXTEND, DL, MVT::i64, Op0);
3797 Op0 = DAG.getNode(ISD::ANY_EXTEND, DL, MVT::i64, Op0);
3798 Op1 = DAG.getNode(ISD::ANY_EXTEND, DL, MVT::i64, Op1);
3800 return DAG.getNode(SystemZISD::JOIN_DWORDS, DL, MVT::v2i64, Op0, Op1);
3803 // Try to represent constant BUILD_VECTOR node BVN using a
3804 // SystemZISD::BYTE_MASK-style mask. Store the mask value in Mask
3806 static bool tryBuildVectorByteMask(BuildVectorSDNode *BVN, uint64_t &Mask) {
3807 EVT ElemVT = BVN->getValueType(0).getVectorElementType();
3808 unsigned BytesPerElement = ElemVT.getStoreSize();
3809 for (unsigned I = 0, E = BVN->getNumOperands(); I != E; ++I) {
3810 SDValue Op = BVN->getOperand(I);
3811 if (Op.getOpcode() != ISD::UNDEF) {
3813 if (Op.getOpcode() == ISD::Constant)
3814 Value = dyn_cast<ConstantSDNode>(Op)->getZExtValue();
3815 else if (Op.getOpcode() == ISD::ConstantFP)
3816 Value = (dyn_cast<ConstantFPSDNode>(Op)->getValueAPF().bitcastToAPInt()
3820 for (unsigned J = 0; J < BytesPerElement; ++J) {
3821 uint64_t Byte = (Value >> (J * 8)) & 0xff;
3823 Mask |= 1ULL << ((E - I - 1) * BytesPerElement + J);
3832 // Try to load a vector constant in which BitsPerElement-bit value Value
3833 // is replicated to fill the vector. VT is the type of the resulting
3834 // constant, which may have elements of a different size from BitsPerElement.
3835 // Return the SDValue of the constant on success, otherwise return
3837 static SDValue tryBuildVectorReplicate(SelectionDAG &DAG,
3838 const SystemZInstrInfo *TII,
3839 SDLoc DL, EVT VT, uint64_t Value,
3840 unsigned BitsPerElement) {
3841 // Signed 16-bit values can be replicated using VREPI.
3842 int64_t SignedValue = SignExtend64(Value, BitsPerElement);
3843 if (isInt<16>(SignedValue)) {
3844 MVT VecVT = MVT::getVectorVT(MVT::getIntegerVT(BitsPerElement),
3845 SystemZ::VectorBits / BitsPerElement);
3846 SDValue Op = DAG.getNode(SystemZISD::REPLICATE, DL, VecVT,
3847 DAG.getConstant(SignedValue, DL, MVT::i32));
3848 return DAG.getNode(ISD::BITCAST, DL, VT, Op);
3850 // See whether rotating the constant left some N places gives a value that
3851 // is one less than a power of 2 (i.e. all zeros followed by all ones).
3852 // If so we can use VGM.
3853 unsigned Start, End;
3854 if (TII->isRxSBGMask(Value, BitsPerElement, Start, End)) {
3855 // isRxSBGMask returns the bit numbers for a full 64-bit value,
3856 // with 0 denoting 1 << 63 and 63 denoting 1. Convert them to
3857 // bit numbers for an BitsPerElement value, so that 0 denotes
3858 // 1 << (BitsPerElement-1).
3859 Start -= 64 - BitsPerElement;
3860 End -= 64 - BitsPerElement;
3861 MVT VecVT = MVT::getVectorVT(MVT::getIntegerVT(BitsPerElement),
3862 SystemZ::VectorBits / BitsPerElement);
3863 SDValue Op = DAG.getNode(SystemZISD::ROTATE_MASK, DL, VecVT,
3864 DAG.getConstant(Start, DL, MVT::i32),
3865 DAG.getConstant(End, DL, MVT::i32));
3866 return DAG.getNode(ISD::BITCAST, DL, VT, Op);
3871 // If a BUILD_VECTOR contains some EXTRACT_VECTOR_ELTs, it's usually
3872 // better to use VECTOR_SHUFFLEs on them, only using BUILD_VECTOR for
3873 // the non-EXTRACT_VECTOR_ELT elements. See if the given BUILD_VECTOR
3874 // would benefit from this representation and return it if so.
3875 static SDValue tryBuildVectorShuffle(SelectionDAG &DAG,
3876 BuildVectorSDNode *BVN) {
3877 EVT VT = BVN->getValueType(0);
3878 unsigned NumElements = VT.getVectorNumElements();
3880 // Represent the BUILD_VECTOR as an N-operand VECTOR_SHUFFLE-like operation
3881 // on byte vectors. If there are non-EXTRACT_VECTOR_ELT elements that still
3882 // need a BUILD_VECTOR, add an additional placeholder operand for that
3883 // BUILD_VECTOR and store its operands in ResidueOps.
3884 GeneralShuffle GS(VT);
3885 SmallVector<SDValue, SystemZ::VectorBytes> ResidueOps;
3886 bool FoundOne = false;
3887 for (unsigned I = 0; I < NumElements; ++I) {
3888 SDValue Op = BVN->getOperand(I);
3889 if (Op.getOpcode() == ISD::TRUNCATE)
3890 Op = Op.getOperand(0);
3891 if (Op.getOpcode() == ISD::EXTRACT_VECTOR_ELT &&
3892 Op.getOperand(1).getOpcode() == ISD::Constant) {
3893 unsigned Elem = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
3894 GS.add(Op.getOperand(0), Elem);
3896 } else if (Op.getOpcode() == ISD::UNDEF) {
3899 GS.add(SDValue(), ResidueOps.size());
3900 ResidueOps.push_back(BVN->getOperand(I));
3904 // Nothing to do if there are no EXTRACT_VECTOR_ELTs.
3908 // Create the BUILD_VECTOR for the remaining elements, if any.
3909 if (!ResidueOps.empty()) {
3910 while (ResidueOps.size() < NumElements)
3911 ResidueOps.push_back(DAG.getUNDEF(VT.getVectorElementType()));
3912 for (auto &Op : GS.Ops) {
3913 if (!Op.getNode()) {
3914 Op = DAG.getNode(ISD::BUILD_VECTOR, SDLoc(BVN), VT, ResidueOps);
3919 return GS.getNode(DAG, SDLoc(BVN));
3922 // Combine GPR scalar values Elems into a vector of type VT.
3923 static SDValue buildVector(SelectionDAG &DAG, SDLoc DL, EVT VT,
3924 SmallVectorImpl<SDValue> &Elems) {
3925 // See whether there is a single replicated value.
3927 unsigned int NumElements = Elems.size();
3928 unsigned int Count = 0;
3929 for (auto Elem : Elems) {
3930 if (Elem.getOpcode() != ISD::UNDEF) {
3931 if (!Single.getNode())
3933 else if (Elem != Single) {
3940 // There are three cases here:
3942 // - if the only defined element is a loaded one, the best sequence
3943 // is a replicating load.
3945 // - otherwise, if the only defined element is an i64 value, we will
3946 // end up with the same VLVGP sequence regardless of whether we short-cut
3947 // for replication or fall through to the later code.
3949 // - otherwise, if the only defined element is an i32 or smaller value,
3950 // we would need 2 instructions to replicate it: VLVGP followed by VREPx.
3951 // This is only a win if the single defined element is used more than once.
3952 // In other cases we're better off using a single VLVGx.
3953 if (Single.getNode() && (Count > 1 || Single.getOpcode() == ISD::LOAD))
3954 return DAG.getNode(SystemZISD::REPLICATE, DL, VT, Single);
3956 // The best way of building a v2i64 from two i64s is to use VLVGP.
3957 if (VT == MVT::v2i64)
3958 return joinDwords(DAG, DL, Elems[0], Elems[1]);
3960 // Use a 64-bit merge high to combine two doubles.
3961 if (VT == MVT::v2f64)
3962 return buildMergeScalars(DAG, DL, VT, Elems[0], Elems[1]);
3964 // Build v4f32 values directly from the FPRs:
3966 // <Axxx> <Bxxx> <Cxxxx> <Dxxx>
3971 if (VT == MVT::v4f32) {
3972 SDValue Op01 = buildMergeScalars(DAG, DL, VT, Elems[0], Elems[1]);
3973 SDValue Op23 = buildMergeScalars(DAG, DL, VT, Elems[2], Elems[3]);
3974 // Avoid unnecessary undefs by reusing the other operand.
3975 if (Op01.getOpcode() == ISD::UNDEF)
3977 else if (Op23.getOpcode() == ISD::UNDEF)
3979 // Merging identical replications is a no-op.
3980 if (Op01.getOpcode() == SystemZISD::REPLICATE && Op01 == Op23)
3982 Op01 = DAG.getNode(ISD::BITCAST, DL, MVT::v2i64, Op01);
3983 Op23 = DAG.getNode(ISD::BITCAST, DL, MVT::v2i64, Op23);
3984 SDValue Op = DAG.getNode(SystemZISD::MERGE_HIGH,
3985 DL, MVT::v2i64, Op01, Op23);
3986 return DAG.getNode(ISD::BITCAST, DL, VT, Op);
3989 // Collect the constant terms.
3990 SmallVector<SDValue, SystemZ::VectorBytes> Constants(NumElements, SDValue());
3991 SmallVector<bool, SystemZ::VectorBytes> Done(NumElements, false);
3993 unsigned NumConstants = 0;
3994 for (unsigned I = 0; I < NumElements; ++I) {
3995 SDValue Elem = Elems[I];
3996 if (Elem.getOpcode() == ISD::Constant ||
3997 Elem.getOpcode() == ISD::ConstantFP) {
3999 Constants[I] = Elem;
4003 // If there was at least one constant, fill in the other elements of
4004 // Constants with undefs to get a full vector constant and use that
4005 // as the starting point.
4007 if (NumConstants > 0) {
4008 for (unsigned I = 0; I < NumElements; ++I)
4009 if (!Constants[I].getNode())
4010 Constants[I] = DAG.getUNDEF(Elems[I].getValueType());
4011 Result = DAG.getNode(ISD::BUILD_VECTOR, DL, VT, Constants);
4013 // Otherwise try to use VLVGP to start the sequence in order to
4014 // avoid a false dependency on any previous contents of the vector
4015 // register. This only makes sense if one of the associated elements
4017 unsigned I1 = NumElements / 2 - 1;
4018 unsigned I2 = NumElements - 1;
4019 bool Def1 = (Elems[I1].getOpcode() != ISD::UNDEF);
4020 bool Def2 = (Elems[I2].getOpcode() != ISD::UNDEF);
4022 SDValue Elem1 = Elems[Def1 ? I1 : I2];
4023 SDValue Elem2 = Elems[Def2 ? I2 : I1];
4024 Result = DAG.getNode(ISD::BITCAST, DL, VT,
4025 joinDwords(DAG, DL, Elem1, Elem2));
4029 Result = DAG.getUNDEF(VT);
4032 // Use VLVGx to insert the other elements.
4033 for (unsigned I = 0; I < NumElements; ++I)
4034 if (!Done[I] && Elems[I].getOpcode() != ISD::UNDEF)
4035 Result = DAG.getNode(ISD::INSERT_VECTOR_ELT, DL, VT, Result, Elems[I],
4036 DAG.getConstant(I, DL, MVT::i32));
4040 SDValue SystemZTargetLowering::lowerBUILD_VECTOR(SDValue Op,
4041 SelectionDAG &DAG) const {
4042 const SystemZInstrInfo *TII =
4043 static_cast<const SystemZInstrInfo *>(Subtarget.getInstrInfo());
4044 auto *BVN = cast<BuildVectorSDNode>(Op.getNode());
4046 EVT VT = Op.getValueType();
4048 if (BVN->isConstant()) {
4049 // Try using VECTOR GENERATE BYTE MASK. This is the architecturally-
4050 // preferred way of creating all-zero and all-one vectors so give it
4051 // priority over other methods below.
4053 if (tryBuildVectorByteMask(BVN, Mask)) {
4054 SDValue Op = DAG.getNode(SystemZISD::BYTE_MASK, DL, MVT::v16i8,
4055 DAG.getConstant(Mask, DL, MVT::i32));
4056 return DAG.getNode(ISD::BITCAST, DL, VT, Op);
4059 // Try using some form of replication.
4060 APInt SplatBits, SplatUndef;
4061 unsigned SplatBitSize;
4063 if (BVN->isConstantSplat(SplatBits, SplatUndef, SplatBitSize, HasAnyUndefs,
4065 SplatBitSize <= 64) {
4066 // First try assuming that any undefined bits above the highest set bit
4067 // and below the lowest set bit are 1s. This increases the likelihood of
4068 // being able to use a sign-extended element value in VECTOR REPLICATE
4069 // IMMEDIATE or a wraparound mask in VECTOR GENERATE MASK.
4070 uint64_t SplatBitsZ = SplatBits.getZExtValue();
4071 uint64_t SplatUndefZ = SplatUndef.getZExtValue();
4072 uint64_t Lower = (SplatUndefZ
4073 & ((uint64_t(1) << findFirstSet(SplatBitsZ)) - 1));
4074 uint64_t Upper = (SplatUndefZ
4075 & ~((uint64_t(1) << findLastSet(SplatBitsZ)) - 1));
4076 uint64_t Value = SplatBitsZ | Upper | Lower;
4077 SDValue Op = tryBuildVectorReplicate(DAG, TII, DL, VT, Value,
4082 // Now try assuming that any undefined bits between the first and
4083 // last defined set bits are set. This increases the chances of
4084 // using a non-wraparound mask.
4085 uint64_t Middle = SplatUndefZ & ~Upper & ~Lower;
4086 Value = SplatBitsZ | Middle;
4087 Op = tryBuildVectorReplicate(DAG, TII, DL, VT, Value, SplatBitSize);
4092 // Fall back to loading it from memory.
4096 // See if we should use shuffles to construct the vector from other vectors.
4097 SDValue Res = tryBuildVectorShuffle(DAG, BVN);
4101 // Detect SCALAR_TO_VECTOR conversions.
4102 if (isOperationLegal(ISD::SCALAR_TO_VECTOR, VT) && isScalarToVector(Op))
4103 return buildScalarToVector(DAG, DL, VT, Op.getOperand(0));
4105 // Otherwise use buildVector to build the vector up from GPRs.
4106 unsigned NumElements = Op.getNumOperands();
4107 SmallVector<SDValue, SystemZ::VectorBytes> Ops(NumElements);
4108 for (unsigned I = 0; I < NumElements; ++I)
4109 Ops[I] = Op.getOperand(I);
4110 return buildVector(DAG, DL, VT, Ops);
4113 SDValue SystemZTargetLowering::lowerVECTOR_SHUFFLE(SDValue Op,
4114 SelectionDAG &DAG) const {
4115 auto *VSN = cast<ShuffleVectorSDNode>(Op.getNode());
4117 EVT VT = Op.getValueType();
4118 unsigned NumElements = VT.getVectorNumElements();
4120 if (VSN->isSplat()) {
4121 SDValue Op0 = Op.getOperand(0);
4122 unsigned Index = VSN->getSplatIndex();
4123 assert(Index < VT.getVectorNumElements() &&
4124 "Splat index should be defined and in first operand");
4125 // See whether the value we're splatting is directly available as a scalar.
4126 if ((Index == 0 && Op0.getOpcode() == ISD::SCALAR_TO_VECTOR) ||
4127 Op0.getOpcode() == ISD::BUILD_VECTOR)
4128 return DAG.getNode(SystemZISD::REPLICATE, DL, VT, Op0.getOperand(Index));
4129 // Otherwise keep it as a vector-to-vector operation.
4130 return DAG.getNode(SystemZISD::SPLAT, DL, VT, Op.getOperand(0),
4131 DAG.getConstant(Index, DL, MVT::i32));
4134 GeneralShuffle GS(VT);
4135 for (unsigned I = 0; I < NumElements; ++I) {
4136 int Elt = VSN->getMaskElt(I);
4140 GS.add(Op.getOperand(unsigned(Elt) / NumElements),
4141 unsigned(Elt) % NumElements);
4143 return GS.getNode(DAG, SDLoc(VSN));
4146 SDValue SystemZTargetLowering::lowerSCALAR_TO_VECTOR(SDValue Op,
4147 SelectionDAG &DAG) const {
4149 // Just insert the scalar into element 0 of an undefined vector.
4150 return DAG.getNode(ISD::INSERT_VECTOR_ELT, DL,
4151 Op.getValueType(), DAG.getUNDEF(Op.getValueType()),
4152 Op.getOperand(0), DAG.getConstant(0, DL, MVT::i32));
4155 SDValue SystemZTargetLowering::lowerINSERT_VECTOR_ELT(SDValue Op,
4156 SelectionDAG &DAG) const {
4157 // Handle insertions of floating-point values.
4159 SDValue Op0 = Op.getOperand(0);
4160 SDValue Op1 = Op.getOperand(1);
4161 SDValue Op2 = Op.getOperand(2);
4162 EVT VT = Op.getValueType();
4164 // Insertions into constant indices of a v2f64 can be done using VPDI.
4165 // However, if the inserted value is a bitcast or a constant then it's
4166 // better to use GPRs, as below.
4167 if (VT == MVT::v2f64 &&
4168 Op1.getOpcode() != ISD::BITCAST &&
4169 Op1.getOpcode() != ISD::ConstantFP &&
4170 Op2.getOpcode() == ISD::Constant) {
4171 uint64_t Index = dyn_cast<ConstantSDNode>(Op2)->getZExtValue();
4172 unsigned Mask = VT.getVectorNumElements() - 1;
4177 // Otherwise bitcast to the equivalent integer form and insert via a GPR.
4178 MVT IntVT = MVT::getIntegerVT(VT.getVectorElementType().getSizeInBits());
4179 MVT IntVecVT = MVT::getVectorVT(IntVT, VT.getVectorNumElements());
4180 SDValue Res = DAG.getNode(ISD::INSERT_VECTOR_ELT, DL, IntVecVT,
4181 DAG.getNode(ISD::BITCAST, DL, IntVecVT, Op0),
4182 DAG.getNode(ISD::BITCAST, DL, IntVT, Op1), Op2);
4183 return DAG.getNode(ISD::BITCAST, DL, VT, Res);
4187 SystemZTargetLowering::lowerEXTRACT_VECTOR_ELT(SDValue Op,
4188 SelectionDAG &DAG) const {
4189 // Handle extractions of floating-point values.
4191 SDValue Op0 = Op.getOperand(0);
4192 SDValue Op1 = Op.getOperand(1);
4193 EVT VT = Op.getValueType();
4194 EVT VecVT = Op0.getValueType();
4196 // Extractions of constant indices can be done directly.
4197 if (auto *CIndexN = dyn_cast<ConstantSDNode>(Op1)) {
4198 uint64_t Index = CIndexN->getZExtValue();
4199 unsigned Mask = VecVT.getVectorNumElements() - 1;
4204 // Otherwise bitcast to the equivalent integer form and extract via a GPR.
4205 MVT IntVT = MVT::getIntegerVT(VT.getSizeInBits());
4206 MVT IntVecVT = MVT::getVectorVT(IntVT, VecVT.getVectorNumElements());
4207 SDValue Res = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, IntVT,
4208 DAG.getNode(ISD::BITCAST, DL, IntVecVT, Op0), Op1);
4209 return DAG.getNode(ISD::BITCAST, DL, VT, Res);
4213 SystemZTargetLowering::lowerExtendVectorInreg(SDValue Op, SelectionDAG &DAG,
4214 unsigned UnpackHigh) const {
4215 SDValue PackedOp = Op.getOperand(0);
4216 EVT OutVT = Op.getValueType();
4217 EVT InVT = PackedOp.getValueType();
4218 unsigned ToBits = OutVT.getVectorElementType().getSizeInBits();
4219 unsigned FromBits = InVT.getVectorElementType().getSizeInBits();
4222 EVT OutVT = MVT::getVectorVT(MVT::getIntegerVT(FromBits),
4223 SystemZ::VectorBits / FromBits);
4224 PackedOp = DAG.getNode(UnpackHigh, SDLoc(PackedOp), OutVT, PackedOp);
4225 } while (FromBits != ToBits);
4229 SDValue SystemZTargetLowering::lowerShift(SDValue Op, SelectionDAG &DAG,
4230 unsigned ByScalar) const {
4231 // Look for cases where a vector shift can use the *_BY_SCALAR form.
4232 SDValue Op0 = Op.getOperand(0);
4233 SDValue Op1 = Op.getOperand(1);
4235 EVT VT = Op.getValueType();
4236 unsigned ElemBitSize = VT.getVectorElementType().getSizeInBits();
4238 // See whether the shift vector is a splat represented as BUILD_VECTOR.
4239 if (auto *BVN = dyn_cast<BuildVectorSDNode>(Op1)) {
4240 APInt SplatBits, SplatUndef;
4241 unsigned SplatBitSize;
4243 // Check for constant splats. Use ElemBitSize as the minimum element
4244 // width and reject splats that need wider elements.
4245 if (BVN->isConstantSplat(SplatBits, SplatUndef, SplatBitSize, HasAnyUndefs,
4246 ElemBitSize, true) &&
4247 SplatBitSize == ElemBitSize) {
4248 SDValue Shift = DAG.getConstant(SplatBits.getZExtValue() & 0xfff,
4250 return DAG.getNode(ByScalar, DL, VT, Op0, Shift);
4252 // Check for variable splats.
4253 BitVector UndefElements;
4254 SDValue Splat = BVN->getSplatValue(&UndefElements);
4256 // Since i32 is the smallest legal type, we either need a no-op
4258 SDValue Shift = DAG.getNode(ISD::TRUNCATE, DL, MVT::i32, Splat);
4259 return DAG.getNode(ByScalar, DL, VT, Op0, Shift);
4263 // See whether the shift vector is a splat represented as SHUFFLE_VECTOR,
4264 // and the shift amount is directly available in a GPR.
4265 if (auto *VSN = dyn_cast<ShuffleVectorSDNode>(Op1)) {
4266 if (VSN->isSplat()) {
4267 SDValue VSNOp0 = VSN->getOperand(0);
4268 unsigned Index = VSN->getSplatIndex();
4269 assert(Index < VT.getVectorNumElements() &&
4270 "Splat index should be defined and in first operand");
4271 if ((Index == 0 && VSNOp0.getOpcode() == ISD::SCALAR_TO_VECTOR) ||
4272 VSNOp0.getOpcode() == ISD::BUILD_VECTOR) {
4273 // Since i32 is the smallest legal type, we either need a no-op
4275 SDValue Shift = DAG.getNode(ISD::TRUNCATE, DL, MVT::i32,
4276 VSNOp0.getOperand(Index));
4277 return DAG.getNode(ByScalar, DL, VT, Op0, Shift);
4282 // Otherwise just treat the current form as legal.
4286 SDValue SystemZTargetLowering::LowerOperation(SDValue Op,
4287 SelectionDAG &DAG) const {
4288 switch (Op.getOpcode()) {
4290 return lowerBR_CC(Op, DAG);
4291 case ISD::SELECT_CC:
4292 return lowerSELECT_CC(Op, DAG);
4294 return lowerSETCC(Op, DAG);
4295 case ISD::GlobalAddress:
4296 return lowerGlobalAddress(cast<GlobalAddressSDNode>(Op), DAG);
4297 case ISD::GlobalTLSAddress:
4298 return lowerGlobalTLSAddress(cast<GlobalAddressSDNode>(Op), DAG);
4299 case ISD::BlockAddress:
4300 return lowerBlockAddress(cast<BlockAddressSDNode>(Op), DAG);
4301 case ISD::JumpTable:
4302 return lowerJumpTable(cast<JumpTableSDNode>(Op), DAG);
4303 case ISD::ConstantPool:
4304 return lowerConstantPool(cast<ConstantPoolSDNode>(Op), DAG);
4306 return lowerBITCAST(Op, DAG);
4308 return lowerVASTART(Op, DAG);
4310 return lowerVACOPY(Op, DAG);
4311 case ISD::DYNAMIC_STACKALLOC:
4312 return lowerDYNAMIC_STACKALLOC(Op, DAG);
4313 case ISD::SMUL_LOHI:
4314 return lowerSMUL_LOHI(Op, DAG);
4315 case ISD::UMUL_LOHI:
4316 return lowerUMUL_LOHI(Op, DAG);
4318 return lowerSDIVREM(Op, DAG);
4320 return lowerUDIVREM(Op, DAG);
4322 return lowerOR(Op, DAG);
4324 return lowerCTPOP(Op, DAG);
4325 case ISD::CTLZ_ZERO_UNDEF:
4326 return DAG.getNode(ISD::CTLZ, SDLoc(Op),
4327 Op.getValueType(), Op.getOperand(0));
4328 case ISD::CTTZ_ZERO_UNDEF:
4329 return DAG.getNode(ISD::CTTZ, SDLoc(Op),
4330 Op.getValueType(), Op.getOperand(0));
4331 case ISD::ATOMIC_SWAP:
4332 return lowerATOMIC_LOAD_OP(Op, DAG, SystemZISD::ATOMIC_SWAPW);
4333 case ISD::ATOMIC_STORE:
4334 return lowerATOMIC_STORE(Op, DAG);
4335 case ISD::ATOMIC_LOAD:
4336 return lowerATOMIC_LOAD(Op, DAG);
4337 case ISD::ATOMIC_LOAD_ADD:
4338 return lowerATOMIC_LOAD_OP(Op, DAG, SystemZISD::ATOMIC_LOADW_ADD);
4339 case ISD::ATOMIC_LOAD_SUB:
4340 return lowerATOMIC_LOAD_SUB(Op, DAG);
4341 case ISD::ATOMIC_LOAD_AND:
4342 return lowerATOMIC_LOAD_OP(Op, DAG, SystemZISD::ATOMIC_LOADW_AND);
4343 case ISD::ATOMIC_LOAD_OR:
4344 return lowerATOMIC_LOAD_OP(Op, DAG, SystemZISD::ATOMIC_LOADW_OR);
4345 case ISD::ATOMIC_LOAD_XOR:
4346 return lowerATOMIC_LOAD_OP(Op, DAG, SystemZISD::ATOMIC_LOADW_XOR);
4347 case ISD::ATOMIC_LOAD_NAND:
4348 return lowerATOMIC_LOAD_OP(Op, DAG, SystemZISD::ATOMIC_LOADW_NAND);
4349 case ISD::ATOMIC_LOAD_MIN:
4350 return lowerATOMIC_LOAD_OP(Op, DAG, SystemZISD::ATOMIC_LOADW_MIN);
4351 case ISD::ATOMIC_LOAD_MAX:
4352 return lowerATOMIC_LOAD_OP(Op, DAG, SystemZISD::ATOMIC_LOADW_MAX);
4353 case ISD::ATOMIC_LOAD_UMIN:
4354 return lowerATOMIC_LOAD_OP(Op, DAG, SystemZISD::ATOMIC_LOADW_UMIN);
4355 case ISD::ATOMIC_LOAD_UMAX:
4356 return lowerATOMIC_LOAD_OP(Op, DAG, SystemZISD::ATOMIC_LOADW_UMAX);
4357 case ISD::ATOMIC_CMP_SWAP:
4358 return lowerATOMIC_CMP_SWAP(Op, DAG);
4359 case ISD::STACKSAVE:
4360 return lowerSTACKSAVE(Op, DAG);
4361 case ISD::STACKRESTORE:
4362 return lowerSTACKRESTORE(Op, DAG);
4364 return lowerPREFETCH(Op, DAG);
4365 case ISD::INTRINSIC_W_CHAIN:
4366 return lowerINTRINSIC_W_CHAIN(Op, DAG);
4367 case ISD::INTRINSIC_WO_CHAIN:
4368 return lowerINTRINSIC_WO_CHAIN(Op, DAG);
4369 case ISD::BUILD_VECTOR:
4370 return lowerBUILD_VECTOR(Op, DAG);
4371 case ISD::VECTOR_SHUFFLE:
4372 return lowerVECTOR_SHUFFLE(Op, DAG);
4373 case ISD::SCALAR_TO_VECTOR:
4374 return lowerSCALAR_TO_VECTOR(Op, DAG);
4375 case ISD::INSERT_VECTOR_ELT:
4376 return lowerINSERT_VECTOR_ELT(Op, DAG);
4377 case ISD::EXTRACT_VECTOR_ELT:
4378 return lowerEXTRACT_VECTOR_ELT(Op, DAG);
4379 case ISD::SIGN_EXTEND_VECTOR_INREG:
4380 return lowerExtendVectorInreg(Op, DAG, SystemZISD::UNPACK_HIGH);
4381 case ISD::ZERO_EXTEND_VECTOR_INREG:
4382 return lowerExtendVectorInreg(Op, DAG, SystemZISD::UNPACKL_HIGH);
4384 return lowerShift(Op, DAG, SystemZISD::VSHL_BY_SCALAR);
4386 return lowerShift(Op, DAG, SystemZISD::VSRL_BY_SCALAR);
4388 return lowerShift(Op, DAG, SystemZISD::VSRA_BY_SCALAR);
4390 llvm_unreachable("Unexpected node to lower");
4394 const char *SystemZTargetLowering::getTargetNodeName(unsigned Opcode) const {
4395 #define OPCODE(NAME) case SystemZISD::NAME: return "SystemZISD::" #NAME
4396 switch ((SystemZISD::NodeType)Opcode) {
4397 case SystemZISD::FIRST_NUMBER: break;
4403 OPCODE(PCREL_WRAPPER);
4404 OPCODE(PCREL_OFFSET);
4410 OPCODE(SELECT_CCMASK);
4411 OPCODE(ADJDYNALLOC);
4412 OPCODE(EXTRACT_ACCESS);
4414 OPCODE(UMUL_LOHI64);
4431 OPCODE(SEARCH_STRING);
4435 OPCODE(TBEGIN_NOFLOAT);
4438 OPCODE(ROTATE_MASK);
4440 OPCODE(JOIN_DWORDS);
4445 OPCODE(PERMUTE_DWORDS);
4450 OPCODE(UNPACK_HIGH);
4451 OPCODE(UNPACKL_HIGH);
4453 OPCODE(UNPACKL_LOW);
4454 OPCODE(VSHL_BY_SCALAR);
4455 OPCODE(VSRL_BY_SCALAR);
4456 OPCODE(VSRA_BY_SCALAR);
4483 OPCODE(ATOMIC_SWAPW);
4484 OPCODE(ATOMIC_LOADW_ADD);
4485 OPCODE(ATOMIC_LOADW_SUB);
4486 OPCODE(ATOMIC_LOADW_AND);
4487 OPCODE(ATOMIC_LOADW_OR);
4488 OPCODE(ATOMIC_LOADW_XOR);
4489 OPCODE(ATOMIC_LOADW_NAND);
4490 OPCODE(ATOMIC_LOADW_MIN);
4491 OPCODE(ATOMIC_LOADW_MAX);
4492 OPCODE(ATOMIC_LOADW_UMIN);
4493 OPCODE(ATOMIC_LOADW_UMAX);
4494 OPCODE(ATOMIC_CMP_SWAPW);
4501 // Return true if VT is a vector whose elements are a whole number of bytes
4503 static bool canTreatAsByteVector(EVT VT) {
4504 return VT.isVector() && VT.getVectorElementType().getSizeInBits() % 8 == 0;
4507 // Try to simplify an EXTRACT_VECTOR_ELT from a vector of type VecVT
4508 // producing a result of type ResVT. Op is a possibly bitcast version
4509 // of the input vector and Index is the index (based on type VecVT) that
4510 // should be extracted. Return the new extraction if a simplification
4511 // was possible or if Force is true.
4512 SDValue SystemZTargetLowering::combineExtract(SDLoc DL, EVT ResVT, EVT VecVT,
4513 SDValue Op, unsigned Index,
4514 DAGCombinerInfo &DCI,
4516 SelectionDAG &DAG = DCI.DAG;
4518 // The number of bytes being extracted.
4519 unsigned BytesPerElement = VecVT.getVectorElementType().getStoreSize();
4522 unsigned Opcode = Op.getOpcode();
4523 if (Opcode == ISD::BITCAST)
4524 // Look through bitcasts.
4525 Op = Op.getOperand(0);
4526 else if (Opcode == ISD::VECTOR_SHUFFLE &&
4527 canTreatAsByteVector(Op.getValueType())) {
4528 // Get a VPERM-like permute mask and see whether the bytes covered
4529 // by the extracted element are a contiguous sequence from one
4531 SmallVector<int, SystemZ::VectorBytes> Bytes;
4532 getVPermMask(cast<ShuffleVectorSDNode>(Op), Bytes);
4534 if (!getShuffleInput(Bytes, Index * BytesPerElement,
4535 BytesPerElement, First))
4538 return DAG.getUNDEF(ResVT);
4539 // Make sure the contiguous sequence starts at a multiple of the
4540 // original element size.
4541 unsigned Byte = unsigned(First) % Bytes.size();
4542 if (Byte % BytesPerElement != 0)
4544 // We can get the extracted value directly from an input.
4545 Index = Byte / BytesPerElement;
4546 Op = Op.getOperand(unsigned(First) / Bytes.size());
4548 } else if (Opcode == ISD::BUILD_VECTOR &&
4549 canTreatAsByteVector(Op.getValueType())) {
4550 // We can only optimize this case if the BUILD_VECTOR elements are
4551 // at least as wide as the extracted value.
4552 EVT OpVT = Op.getValueType();
4553 unsigned OpBytesPerElement = OpVT.getVectorElementType().getStoreSize();
4554 if (OpBytesPerElement < BytesPerElement)
4556 // Make sure that the least-significant bit of the extracted value
4557 // is the least significant bit of an input.
4558 unsigned End = (Index + 1) * BytesPerElement;
4559 if (End % OpBytesPerElement != 0)
4561 // We're extracting the low part of one operand of the BUILD_VECTOR.
4562 Op = Op.getOperand(End / OpBytesPerElement - 1);
4563 if (!Op.getValueType().isInteger()) {
4564 EVT VT = MVT::getIntegerVT(Op.getValueType().getSizeInBits());
4565 Op = DAG.getNode(ISD::BITCAST, DL, VT, Op);
4566 DCI.AddToWorklist(Op.getNode());
4568 EVT VT = MVT::getIntegerVT(ResVT.getSizeInBits());
4569 Op = DAG.getNode(ISD::TRUNCATE, DL, VT, Op);
4571 DCI.AddToWorklist(Op.getNode());
4572 Op = DAG.getNode(ISD::BITCAST, DL, ResVT, Op);
4575 } else if ((Opcode == ISD::SIGN_EXTEND_VECTOR_INREG ||
4576 Opcode == ISD::ZERO_EXTEND_VECTOR_INREG ||
4577 Opcode == ISD::ANY_EXTEND_VECTOR_INREG) &&
4578 canTreatAsByteVector(Op.getValueType()) &&
4579 canTreatAsByteVector(Op.getOperand(0).getValueType())) {
4580 // Make sure that only the unextended bits are significant.
4581 EVT ExtVT = Op.getValueType();
4582 EVT OpVT = Op.getOperand(0).getValueType();
4583 unsigned ExtBytesPerElement = ExtVT.getVectorElementType().getStoreSize();
4584 unsigned OpBytesPerElement = OpVT.getVectorElementType().getStoreSize();
4585 unsigned Byte = Index * BytesPerElement;
4586 unsigned SubByte = Byte % ExtBytesPerElement;
4587 unsigned MinSubByte = ExtBytesPerElement - OpBytesPerElement;
4588 if (SubByte < MinSubByte ||
4589 SubByte + BytesPerElement > ExtBytesPerElement)
4591 // Get the byte offset of the unextended element
4592 Byte = Byte / ExtBytesPerElement * OpBytesPerElement;
4593 // ...then add the byte offset relative to that element.
4594 Byte += SubByte - MinSubByte;
4595 if (Byte % BytesPerElement != 0)
4597 Op = Op.getOperand(0);
4598 Index = Byte / BytesPerElement;
4604 if (Op.getValueType() != VecVT) {
4605 Op = DAG.getNode(ISD::BITCAST, DL, VecVT, Op);
4606 DCI.AddToWorklist(Op.getNode());
4608 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, ResVT, Op,
4609 DAG.getConstant(Index, DL, MVT::i32));
4614 // Optimize vector operations in scalar value Op on the basis that Op
4615 // is truncated to TruncVT.
4617 SystemZTargetLowering::combineTruncateExtract(SDLoc DL, EVT TruncVT, SDValue Op,
4618 DAGCombinerInfo &DCI) const {
4619 // If we have (trunc (extract_vector_elt X, Y)), try to turn it into
4620 // (extract_vector_elt (bitcast X), Y'), where (bitcast X) has elements
4622 if (Op.getOpcode() == ISD::EXTRACT_VECTOR_ELT &&
4623 TruncVT.getSizeInBits() % 8 == 0) {
4624 SDValue Vec = Op.getOperand(0);
4625 EVT VecVT = Vec.getValueType();
4626 if (canTreatAsByteVector(VecVT)) {
4627 if (auto *IndexN = dyn_cast<ConstantSDNode>(Op.getOperand(1))) {
4628 unsigned BytesPerElement = VecVT.getVectorElementType().getStoreSize();
4629 unsigned TruncBytes = TruncVT.getStoreSize();
4630 if (BytesPerElement % TruncBytes == 0) {
4631 // Calculate the value of Y' in the above description. We are
4632 // splitting the original elements into Scale equal-sized pieces
4633 // and for truncation purposes want the last (least-significant)
4634 // of these pieces for IndexN. This is easiest to do by calculating
4635 // the start index of the following element and then subtracting 1.
4636 unsigned Scale = BytesPerElement / TruncBytes;
4637 unsigned NewIndex = (IndexN->getZExtValue() + 1) * Scale - 1;
4639 // Defer the creation of the bitcast from X to combineExtract,
4640 // which might be able to optimize the extraction.
4641 VecVT = MVT::getVectorVT(MVT::getIntegerVT(TruncBytes * 8),
4642 VecVT.getStoreSize() / TruncBytes);
4643 EVT ResVT = (TruncBytes < 4 ? MVT::i32 : TruncVT);
4644 return combineExtract(DL, ResVT, VecVT, Vec, NewIndex, DCI, true);
4652 SDValue SystemZTargetLowering::PerformDAGCombine(SDNode *N,
4653 DAGCombinerInfo &DCI) const {
4654 SelectionDAG &DAG = DCI.DAG;
4655 unsigned Opcode = N->getOpcode();
4656 if (Opcode == ISD::SIGN_EXTEND) {
4657 // Convert (sext (ashr (shl X, C1), C2)) to
4658 // (ashr (shl (anyext X), C1'), C2')), since wider shifts are as
4659 // cheap as narrower ones.
4660 SDValue N0 = N->getOperand(0);
4661 EVT VT = N->getValueType(0);
4662 if (N0.hasOneUse() && N0.getOpcode() == ISD::SRA) {
4663 auto *SraAmt = dyn_cast<ConstantSDNode>(N0.getOperand(1));
4664 SDValue Inner = N0.getOperand(0);
4665 if (SraAmt && Inner.hasOneUse() && Inner.getOpcode() == ISD::SHL) {
4666 if (auto *ShlAmt = dyn_cast<ConstantSDNode>(Inner.getOperand(1))) {
4667 unsigned Extra = (VT.getSizeInBits() -
4668 N0.getValueType().getSizeInBits());
4669 unsigned NewShlAmt = ShlAmt->getZExtValue() + Extra;
4670 unsigned NewSraAmt = SraAmt->getZExtValue() + Extra;
4671 EVT ShiftVT = N0.getOperand(1).getValueType();
4672 SDValue Ext = DAG.getNode(ISD::ANY_EXTEND, SDLoc(Inner), VT,
4673 Inner.getOperand(0));
4674 SDValue Shl = DAG.getNode(ISD::SHL, SDLoc(Inner), VT, Ext,
4675 DAG.getConstant(NewShlAmt, SDLoc(Inner),
4677 return DAG.getNode(ISD::SRA, SDLoc(N0), VT, Shl,
4678 DAG.getConstant(NewSraAmt, SDLoc(N0), ShiftVT));
4683 if (Opcode == SystemZISD::MERGE_HIGH ||
4684 Opcode == SystemZISD::MERGE_LOW) {
4685 SDValue Op0 = N->getOperand(0);
4686 SDValue Op1 = N->getOperand(1);
4687 if (Op0.getOpcode() == ISD::BITCAST)
4688 Op0 = Op0.getOperand(0);
4689 if (Op0.getOpcode() == SystemZISD::BYTE_MASK &&
4690 cast<ConstantSDNode>(Op0.getOperand(0))->getZExtValue() == 0) {
4691 // (z_merge_* 0, 0) -> 0. This is mostly useful for using VLLEZF
4693 if (Op1 == N->getOperand(0))
4695 // (z_merge_? 0, X) -> (z_unpackl_? 0, X).
4696 EVT VT = Op1.getValueType();
4697 unsigned ElemBytes = VT.getVectorElementType().getStoreSize();
4698 if (ElemBytes <= 4) {
4699 Opcode = (Opcode == SystemZISD::MERGE_HIGH ?
4700 SystemZISD::UNPACKL_HIGH : SystemZISD::UNPACKL_LOW);
4701 EVT InVT = VT.changeVectorElementTypeToInteger();
4702 EVT OutVT = MVT::getVectorVT(MVT::getIntegerVT(ElemBytes * 16),
4703 SystemZ::VectorBytes / ElemBytes / 2);
4705 Op1 = DAG.getNode(ISD::BITCAST, SDLoc(N), InVT, Op1);
4706 DCI.AddToWorklist(Op1.getNode());
4708 SDValue Op = DAG.getNode(Opcode, SDLoc(N), OutVT, Op1);
4709 DCI.AddToWorklist(Op.getNode());
4710 return DAG.getNode(ISD::BITCAST, SDLoc(N), VT, Op);
4714 // If we have (truncstoreiN (extract_vector_elt X, Y), Z) then it is better
4715 // for the extraction to be done on a vMiN value, so that we can use VSTE.
4716 // If X has wider elements then convert it to:
4717 // (truncstoreiN (extract_vector_elt (bitcast X), Y2), Z).
4718 if (Opcode == ISD::STORE) {
4719 auto *SN = cast<StoreSDNode>(N);
4720 EVT MemVT = SN->getMemoryVT();
4721 if (MemVT.isInteger()) {
4722 SDValue Value = combineTruncateExtract(SDLoc(N), MemVT,
4723 SN->getValue(), DCI);
4724 if (Value.getNode()) {
4725 DCI.AddToWorklist(Value.getNode());
4727 // Rewrite the store with the new form of stored value.
4728 return DAG.getTruncStore(SN->getChain(), SDLoc(SN), Value,
4729 SN->getBasePtr(), SN->getMemoryVT(),
4730 SN->getMemOperand());
4734 // Try to simplify a vector extraction.
4735 if (Opcode == ISD::EXTRACT_VECTOR_ELT) {
4736 if (auto *IndexN = dyn_cast<ConstantSDNode>(N->getOperand(1))) {
4737 SDValue Op0 = N->getOperand(0);
4738 EVT VecVT = Op0.getValueType();
4739 return combineExtract(SDLoc(N), N->getValueType(0), VecVT, Op0,
4740 IndexN->getZExtValue(), DCI, false);
4743 // (join_dwords X, X) == (replicate X)
4744 if (Opcode == SystemZISD::JOIN_DWORDS &&
4745 N->getOperand(0) == N->getOperand(1))
4746 return DAG.getNode(SystemZISD::REPLICATE, SDLoc(N), N->getValueType(0),
4748 // (fround (extract_vector_elt X 0))
4749 // (fround (extract_vector_elt X 1)) ->
4750 // (extract_vector_elt (VROUND X) 0)
4751 // (extract_vector_elt (VROUND X) 1)
4753 // This is a special case since the target doesn't really support v2f32s.
4754 if (Opcode == ISD::FP_ROUND) {
4755 SDValue Op0 = N->getOperand(0);
4756 if (N->getValueType(0) == MVT::f32 &&
4758 Op0.getOpcode() == ISD::EXTRACT_VECTOR_ELT &&
4759 Op0.getOperand(0).getValueType() == MVT::v2f64 &&
4760 Op0.getOperand(1).getOpcode() == ISD::Constant &&
4761 cast<ConstantSDNode>(Op0.getOperand(1))->getZExtValue() == 0) {
4762 SDValue Vec = Op0.getOperand(0);
4763 for (auto *U : Vec->uses()) {
4764 if (U != Op0.getNode() &&
4766 U->getOpcode() == ISD::EXTRACT_VECTOR_ELT &&
4767 U->getOperand(0) == Vec &&
4768 U->getOperand(1).getOpcode() == ISD::Constant &&
4769 cast<ConstantSDNode>(U->getOperand(1))->getZExtValue() == 1) {
4770 SDValue OtherRound = SDValue(*U->use_begin(), 0);
4771 if (OtherRound.getOpcode() == ISD::FP_ROUND &&
4772 OtherRound.getOperand(0) == SDValue(U, 0) &&
4773 OtherRound.getValueType() == MVT::f32) {
4774 SDValue VRound = DAG.getNode(SystemZISD::VROUND, SDLoc(N),
4776 DCI.AddToWorklist(VRound.getNode());
4778 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, SDLoc(U), MVT::f32,
4779 VRound, DAG.getConstant(2, SDLoc(U), MVT::i32));
4780 DCI.AddToWorklist(Extract1.getNode());
4781 DAG.ReplaceAllUsesOfValueWith(OtherRound, Extract1);
4783 DAG.getNode(ISD::EXTRACT_VECTOR_ELT, SDLoc(Op0), MVT::f32,
4784 VRound, DAG.getConstant(0, SDLoc(Op0), MVT::i32));
4794 //===----------------------------------------------------------------------===//
4796 //===----------------------------------------------------------------------===//
4798 // Create a new basic block after MBB.
4799 static MachineBasicBlock *emitBlockAfter(MachineBasicBlock *MBB) {
4800 MachineFunction &MF = *MBB->getParent();
4801 MachineBasicBlock *NewMBB = MF.CreateMachineBasicBlock(MBB->getBasicBlock());
4802 MF.insert(std::next(MachineFunction::iterator(MBB)), NewMBB);
4806 // Split MBB after MI and return the new block (the one that contains
4807 // instructions after MI).
4808 static MachineBasicBlock *splitBlockAfter(MachineInstr *MI,
4809 MachineBasicBlock *MBB) {
4810 MachineBasicBlock *NewMBB = emitBlockAfter(MBB);
4811 NewMBB->splice(NewMBB->begin(), MBB,
4812 std::next(MachineBasicBlock::iterator(MI)), MBB->end());
4813 NewMBB->transferSuccessorsAndUpdatePHIs(MBB);
4817 // Split MBB before MI and return the new block (the one that contains MI).
4818 static MachineBasicBlock *splitBlockBefore(MachineInstr *MI,
4819 MachineBasicBlock *MBB) {
4820 MachineBasicBlock *NewMBB = emitBlockAfter(MBB);
4821 NewMBB->splice(NewMBB->begin(), MBB, MI, MBB->end());
4822 NewMBB->transferSuccessorsAndUpdatePHIs(MBB);
4826 // Force base value Base into a register before MI. Return the register.
4827 static unsigned forceReg(MachineInstr *MI, MachineOperand &Base,
4828 const SystemZInstrInfo *TII) {
4830 return Base.getReg();
4832 MachineBasicBlock *MBB = MI->getParent();
4833 MachineFunction &MF = *MBB->getParent();
4834 MachineRegisterInfo &MRI = MF.getRegInfo();
4836 unsigned Reg = MRI.createVirtualRegister(&SystemZ::ADDR64BitRegClass);
4837 BuildMI(*MBB, MI, MI->getDebugLoc(), TII->get(SystemZ::LA), Reg)
4838 .addOperand(Base).addImm(0).addReg(0);
4842 // Implement EmitInstrWithCustomInserter for pseudo Select* instruction MI.
4844 SystemZTargetLowering::emitSelect(MachineInstr *MI,
4845 MachineBasicBlock *MBB) const {
4846 const SystemZInstrInfo *TII =
4847 static_cast<const SystemZInstrInfo *>(Subtarget.getInstrInfo());
4849 unsigned DestReg = MI->getOperand(0).getReg();
4850 unsigned TrueReg = MI->getOperand(1).getReg();
4851 unsigned FalseReg = MI->getOperand(2).getReg();
4852 unsigned CCValid = MI->getOperand(3).getImm();
4853 unsigned CCMask = MI->getOperand(4).getImm();
4854 DebugLoc DL = MI->getDebugLoc();
4856 MachineBasicBlock *StartMBB = MBB;
4857 MachineBasicBlock *JoinMBB = splitBlockBefore(MI, MBB);
4858 MachineBasicBlock *FalseMBB = emitBlockAfter(StartMBB);
4861 // BRC CCMask, JoinMBB
4862 // # fallthrough to FalseMBB
4864 BuildMI(MBB, DL, TII->get(SystemZ::BRC))
4865 .addImm(CCValid).addImm(CCMask).addMBB(JoinMBB);
4866 MBB->addSuccessor(JoinMBB);
4867 MBB->addSuccessor(FalseMBB);
4870 // # fallthrough to JoinMBB
4872 MBB->addSuccessor(JoinMBB);
4875 // %Result = phi [ %FalseReg, FalseMBB ], [ %TrueReg, StartMBB ]
4878 BuildMI(*MBB, MI, DL, TII->get(SystemZ::PHI), DestReg)
4879 .addReg(TrueReg).addMBB(StartMBB)
4880 .addReg(FalseReg).addMBB(FalseMBB);
4882 MI->eraseFromParent();
4886 // Implement EmitInstrWithCustomInserter for pseudo CondStore* instruction MI.
4887 // StoreOpcode is the store to use and Invert says whether the store should
4888 // happen when the condition is false rather than true. If a STORE ON
4889 // CONDITION is available, STOCOpcode is its opcode, otherwise it is 0.
4891 SystemZTargetLowering::emitCondStore(MachineInstr *MI,
4892 MachineBasicBlock *MBB,
4893 unsigned StoreOpcode, unsigned STOCOpcode,
4894 bool Invert) const {
4895 const SystemZInstrInfo *TII =
4896 static_cast<const SystemZInstrInfo *>(Subtarget.getInstrInfo());
4898 unsigned SrcReg = MI->getOperand(0).getReg();
4899 MachineOperand Base = MI->getOperand(1);
4900 int64_t Disp = MI->getOperand(2).getImm();
4901 unsigned IndexReg = MI->getOperand(3).getReg();
4902 unsigned CCValid = MI->getOperand(4).getImm();
4903 unsigned CCMask = MI->getOperand(5).getImm();
4904 DebugLoc DL = MI->getDebugLoc();
4906 StoreOpcode = TII->getOpcodeForOffset(StoreOpcode, Disp);
4908 // Use STOCOpcode if possible. We could use different store patterns in
4909 // order to avoid matching the index register, but the performance trade-offs
4910 // might be more complicated in that case.
4911 if (STOCOpcode && !IndexReg && Subtarget.hasLoadStoreOnCond()) {
4914 BuildMI(*MBB, MI, DL, TII->get(STOCOpcode))
4915 .addReg(SrcReg).addOperand(Base).addImm(Disp)
4916 .addImm(CCValid).addImm(CCMask);
4917 MI->eraseFromParent();
4921 // Get the condition needed to branch around the store.
4925 MachineBasicBlock *StartMBB = MBB;
4926 MachineBasicBlock *JoinMBB = splitBlockBefore(MI, MBB);
4927 MachineBasicBlock *FalseMBB = emitBlockAfter(StartMBB);
4930 // BRC CCMask, JoinMBB
4931 // # fallthrough to FalseMBB
4933 BuildMI(MBB, DL, TII->get(SystemZ::BRC))
4934 .addImm(CCValid).addImm(CCMask).addMBB(JoinMBB);
4935 MBB->addSuccessor(JoinMBB);
4936 MBB->addSuccessor(FalseMBB);
4939 // store %SrcReg, %Disp(%Index,%Base)
4940 // # fallthrough to JoinMBB
4942 BuildMI(MBB, DL, TII->get(StoreOpcode))
4943 .addReg(SrcReg).addOperand(Base).addImm(Disp).addReg(IndexReg);
4944 MBB->addSuccessor(JoinMBB);
4946 MI->eraseFromParent();
4950 // Implement EmitInstrWithCustomInserter for pseudo ATOMIC_LOAD{,W}_*
4951 // or ATOMIC_SWAP{,W} instruction MI. BinOpcode is the instruction that
4952 // performs the binary operation elided by "*", or 0 for ATOMIC_SWAP{,W}.
4953 // BitSize is the width of the field in bits, or 0 if this is a partword
4954 // ATOMIC_LOADW_* or ATOMIC_SWAPW instruction, in which case the bitsize
4955 // is one of the operands. Invert says whether the field should be
4956 // inverted after performing BinOpcode (e.g. for NAND).
4958 SystemZTargetLowering::emitAtomicLoadBinary(MachineInstr *MI,
4959 MachineBasicBlock *MBB,
4962 bool Invert) const {
4963 MachineFunction &MF = *MBB->getParent();
4964 const SystemZInstrInfo *TII =
4965 static_cast<const SystemZInstrInfo *>(Subtarget.getInstrInfo());
4966 MachineRegisterInfo &MRI = MF.getRegInfo();
4967 bool IsSubWord = (BitSize < 32);
4969 // Extract the operands. Base can be a register or a frame index.
4970 // Src2 can be a register or immediate.
4971 unsigned Dest = MI->getOperand(0).getReg();
4972 MachineOperand Base = earlyUseOperand(MI->getOperand(1));
4973 int64_t Disp = MI->getOperand(2).getImm();
4974 MachineOperand Src2 = earlyUseOperand(MI->getOperand(3));
4975 unsigned BitShift = (IsSubWord ? MI->getOperand(4).getReg() : 0);
4976 unsigned NegBitShift = (IsSubWord ? MI->getOperand(5).getReg() : 0);
4977 DebugLoc DL = MI->getDebugLoc();
4979 BitSize = MI->getOperand(6).getImm();
4981 // Subword operations use 32-bit registers.
4982 const TargetRegisterClass *RC = (BitSize <= 32 ?
4983 &SystemZ::GR32BitRegClass :
4984 &SystemZ::GR64BitRegClass);
4985 unsigned LOpcode = BitSize <= 32 ? SystemZ::L : SystemZ::LG;
4986 unsigned CSOpcode = BitSize <= 32 ? SystemZ::CS : SystemZ::CSG;
4988 // Get the right opcodes for the displacement.
4989 LOpcode = TII->getOpcodeForOffset(LOpcode, Disp);
4990 CSOpcode = TII->getOpcodeForOffset(CSOpcode, Disp);
4991 assert(LOpcode && CSOpcode && "Displacement out of range");
4993 // Create virtual registers for temporary results.
4994 unsigned OrigVal = MRI.createVirtualRegister(RC);
4995 unsigned OldVal = MRI.createVirtualRegister(RC);
4996 unsigned NewVal = (BinOpcode || IsSubWord ?
4997 MRI.createVirtualRegister(RC) : Src2.getReg());
4998 unsigned RotatedOldVal = (IsSubWord ? MRI.createVirtualRegister(RC) : OldVal);
4999 unsigned RotatedNewVal = (IsSubWord ? MRI.createVirtualRegister(RC) : NewVal);
5001 // Insert a basic block for the main loop.
5002 MachineBasicBlock *StartMBB = MBB;
5003 MachineBasicBlock *DoneMBB = splitBlockBefore(MI, MBB);
5004 MachineBasicBlock *LoopMBB = emitBlockAfter(StartMBB);
5008 // %OrigVal = L Disp(%Base)
5009 // # fall through to LoopMMB
5011 BuildMI(MBB, DL, TII->get(LOpcode), OrigVal)
5012 .addOperand(Base).addImm(Disp).addReg(0);
5013 MBB->addSuccessor(LoopMBB);
5016 // %OldVal = phi [ %OrigVal, StartMBB ], [ %Dest, LoopMBB ]
5017 // %RotatedOldVal = RLL %OldVal, 0(%BitShift)
5018 // %RotatedNewVal = OP %RotatedOldVal, %Src2
5019 // %NewVal = RLL %RotatedNewVal, 0(%NegBitShift)
5020 // %Dest = CS %OldVal, %NewVal, Disp(%Base)
5022 // # fall through to DoneMMB
5024 BuildMI(MBB, DL, TII->get(SystemZ::PHI), OldVal)
5025 .addReg(OrigVal).addMBB(StartMBB)
5026 .addReg(Dest).addMBB(LoopMBB);
5028 BuildMI(MBB, DL, TII->get(SystemZ::RLL), RotatedOldVal)
5029 .addReg(OldVal).addReg(BitShift).addImm(0);
5031 // Perform the operation normally and then invert every bit of the field.
5032 unsigned Tmp = MRI.createVirtualRegister(RC);
5033 BuildMI(MBB, DL, TII->get(BinOpcode), Tmp)
5034 .addReg(RotatedOldVal).addOperand(Src2);
5036 // XILF with the upper BitSize bits set.
5037 BuildMI(MBB, DL, TII->get(SystemZ::XILF), RotatedNewVal)
5038 .addReg(Tmp).addImm(-1U << (32 - BitSize));
5040 // Use LCGR and add -1 to the result, which is more compact than
5041 // an XILF, XILH pair.
5042 unsigned Tmp2 = MRI.createVirtualRegister(RC);
5043 BuildMI(MBB, DL, TII->get(SystemZ::LCGR), Tmp2).addReg(Tmp);
5044 BuildMI(MBB, DL, TII->get(SystemZ::AGHI), RotatedNewVal)
5045 .addReg(Tmp2).addImm(-1);
5047 } else if (BinOpcode)
5048 // A simply binary operation.
5049 BuildMI(MBB, DL, TII->get(BinOpcode), RotatedNewVal)
5050 .addReg(RotatedOldVal).addOperand(Src2);
5052 // Use RISBG to rotate Src2 into position and use it to replace the
5053 // field in RotatedOldVal.
5054 BuildMI(MBB, DL, TII->get(SystemZ::RISBG32), RotatedNewVal)
5055 .addReg(RotatedOldVal).addReg(Src2.getReg())
5056 .addImm(32).addImm(31 + BitSize).addImm(32 - BitSize);
5058 BuildMI(MBB, DL, TII->get(SystemZ::RLL), NewVal)
5059 .addReg(RotatedNewVal).addReg(NegBitShift).addImm(0);
5060 BuildMI(MBB, DL, TII->get(CSOpcode), Dest)
5061 .addReg(OldVal).addReg(NewVal).addOperand(Base).addImm(Disp);
5062 BuildMI(MBB, DL, TII->get(SystemZ::BRC))
5063 .addImm(SystemZ::CCMASK_CS).addImm(SystemZ::CCMASK_CS_NE).addMBB(LoopMBB);
5064 MBB->addSuccessor(LoopMBB);
5065 MBB->addSuccessor(DoneMBB);
5067 MI->eraseFromParent();
5071 // Implement EmitInstrWithCustomInserter for pseudo
5072 // ATOMIC_LOAD{,W}_{,U}{MIN,MAX} instruction MI. CompareOpcode is the
5073 // instruction that should be used to compare the current field with the
5074 // minimum or maximum value. KeepOldMask is the BRC condition-code mask
5075 // for when the current field should be kept. BitSize is the width of
5076 // the field in bits, or 0 if this is a partword ATOMIC_LOADW_* instruction.
5078 SystemZTargetLowering::emitAtomicLoadMinMax(MachineInstr *MI,
5079 MachineBasicBlock *MBB,
5080 unsigned CompareOpcode,
5081 unsigned KeepOldMask,
5082 unsigned BitSize) const {
5083 MachineFunction &MF = *MBB->getParent();
5084 const SystemZInstrInfo *TII =
5085 static_cast<const SystemZInstrInfo *>(Subtarget.getInstrInfo());
5086 MachineRegisterInfo &MRI = MF.getRegInfo();
5087 bool IsSubWord = (BitSize < 32);
5089 // Extract the operands. Base can be a register or a frame index.
5090 unsigned Dest = MI->getOperand(0).getReg();
5091 MachineOperand Base = earlyUseOperand(MI->getOperand(1));
5092 int64_t Disp = MI->getOperand(2).getImm();
5093 unsigned Src2 = MI->getOperand(3).getReg();
5094 unsigned BitShift = (IsSubWord ? MI->getOperand(4).getReg() : 0);
5095 unsigned NegBitShift = (IsSubWord ? MI->getOperand(5).getReg() : 0);
5096 DebugLoc DL = MI->getDebugLoc();
5098 BitSize = MI->getOperand(6).getImm();
5100 // Subword operations use 32-bit registers.
5101 const TargetRegisterClass *RC = (BitSize <= 32 ?
5102 &SystemZ::GR32BitRegClass :
5103 &SystemZ::GR64BitRegClass);
5104 unsigned LOpcode = BitSize <= 32 ? SystemZ::L : SystemZ::LG;
5105 unsigned CSOpcode = BitSize <= 32 ? SystemZ::CS : SystemZ::CSG;
5107 // Get the right opcodes for the displacement.
5108 LOpcode = TII->getOpcodeForOffset(LOpcode, Disp);
5109 CSOpcode = TII->getOpcodeForOffset(CSOpcode, Disp);
5110 assert(LOpcode && CSOpcode && "Displacement out of range");
5112 // Create virtual registers for temporary results.
5113 unsigned OrigVal = MRI.createVirtualRegister(RC);
5114 unsigned OldVal = MRI.createVirtualRegister(RC);
5115 unsigned NewVal = MRI.createVirtualRegister(RC);
5116 unsigned RotatedOldVal = (IsSubWord ? MRI.createVirtualRegister(RC) : OldVal);
5117 unsigned RotatedAltVal = (IsSubWord ? MRI.createVirtualRegister(RC) : Src2);
5118 unsigned RotatedNewVal = (IsSubWord ? MRI.createVirtualRegister(RC) : NewVal);
5120 // Insert 3 basic blocks for the loop.
5121 MachineBasicBlock *StartMBB = MBB;
5122 MachineBasicBlock *DoneMBB = splitBlockBefore(MI, MBB);
5123 MachineBasicBlock *LoopMBB = emitBlockAfter(StartMBB);
5124 MachineBasicBlock *UseAltMBB = emitBlockAfter(LoopMBB);
5125 MachineBasicBlock *UpdateMBB = emitBlockAfter(UseAltMBB);
5129 // %OrigVal = L Disp(%Base)
5130 // # fall through to LoopMMB
5132 BuildMI(MBB, DL, TII->get(LOpcode), OrigVal)
5133 .addOperand(Base).addImm(Disp).addReg(0);
5134 MBB->addSuccessor(LoopMBB);
5137 // %OldVal = phi [ %OrigVal, StartMBB ], [ %Dest, UpdateMBB ]
5138 // %RotatedOldVal = RLL %OldVal, 0(%BitShift)
5139 // CompareOpcode %RotatedOldVal, %Src2
5140 // BRC KeepOldMask, UpdateMBB
5142 BuildMI(MBB, DL, TII->get(SystemZ::PHI), OldVal)
5143 .addReg(OrigVal).addMBB(StartMBB)
5144 .addReg(Dest).addMBB(UpdateMBB);
5146 BuildMI(MBB, DL, TII->get(SystemZ::RLL), RotatedOldVal)
5147 .addReg(OldVal).addReg(BitShift).addImm(0);
5148 BuildMI(MBB, DL, TII->get(CompareOpcode))
5149 .addReg(RotatedOldVal).addReg(Src2);
5150 BuildMI(MBB, DL, TII->get(SystemZ::BRC))
5151 .addImm(SystemZ::CCMASK_ICMP).addImm(KeepOldMask).addMBB(UpdateMBB);
5152 MBB->addSuccessor(UpdateMBB);
5153 MBB->addSuccessor(UseAltMBB);
5156 // %RotatedAltVal = RISBG %RotatedOldVal, %Src2, 32, 31 + BitSize, 0
5157 // # fall through to UpdateMMB
5160 BuildMI(MBB, DL, TII->get(SystemZ::RISBG32), RotatedAltVal)
5161 .addReg(RotatedOldVal).addReg(Src2)
5162 .addImm(32).addImm(31 + BitSize).addImm(0);
5163 MBB->addSuccessor(UpdateMBB);
5166 // %RotatedNewVal = PHI [ %RotatedOldVal, LoopMBB ],
5167 // [ %RotatedAltVal, UseAltMBB ]
5168 // %NewVal = RLL %RotatedNewVal, 0(%NegBitShift)
5169 // %Dest = CS %OldVal, %NewVal, Disp(%Base)
5171 // # fall through to DoneMMB
5173 BuildMI(MBB, DL, TII->get(SystemZ::PHI), RotatedNewVal)
5174 .addReg(RotatedOldVal).addMBB(LoopMBB)
5175 .addReg(RotatedAltVal).addMBB(UseAltMBB);
5177 BuildMI(MBB, DL, TII->get(SystemZ::RLL), NewVal)
5178 .addReg(RotatedNewVal).addReg(NegBitShift).addImm(0);
5179 BuildMI(MBB, DL, TII->get(CSOpcode), Dest)
5180 .addReg(OldVal).addReg(NewVal).addOperand(Base).addImm(Disp);
5181 BuildMI(MBB, DL, TII->get(SystemZ::BRC))
5182 .addImm(SystemZ::CCMASK_CS).addImm(SystemZ::CCMASK_CS_NE).addMBB(LoopMBB);
5183 MBB->addSuccessor(LoopMBB);
5184 MBB->addSuccessor(DoneMBB);
5186 MI->eraseFromParent();
5190 // Implement EmitInstrWithCustomInserter for pseudo ATOMIC_CMP_SWAPW
5193 SystemZTargetLowering::emitAtomicCmpSwapW(MachineInstr *MI,
5194 MachineBasicBlock *MBB) const {
5195 MachineFunction &MF = *MBB->getParent();
5196 const SystemZInstrInfo *TII =
5197 static_cast<const SystemZInstrInfo *>(Subtarget.getInstrInfo());
5198 MachineRegisterInfo &MRI = MF.getRegInfo();
5200 // Extract the operands. Base can be a register or a frame index.
5201 unsigned Dest = MI->getOperand(0).getReg();
5202 MachineOperand Base = earlyUseOperand(MI->getOperand(1));
5203 int64_t Disp = MI->getOperand(2).getImm();
5204 unsigned OrigCmpVal = MI->getOperand(3).getReg();
5205 unsigned OrigSwapVal = MI->getOperand(4).getReg();
5206 unsigned BitShift = MI->getOperand(5).getReg();
5207 unsigned NegBitShift = MI->getOperand(6).getReg();
5208 int64_t BitSize = MI->getOperand(7).getImm();
5209 DebugLoc DL = MI->getDebugLoc();
5211 const TargetRegisterClass *RC = &SystemZ::GR32BitRegClass;
5213 // Get the right opcodes for the displacement.
5214 unsigned LOpcode = TII->getOpcodeForOffset(SystemZ::L, Disp);
5215 unsigned CSOpcode = TII->getOpcodeForOffset(SystemZ::CS, Disp);
5216 assert(LOpcode && CSOpcode && "Displacement out of range");
5218 // Create virtual registers for temporary results.
5219 unsigned OrigOldVal = MRI.createVirtualRegister(RC);
5220 unsigned OldVal = MRI.createVirtualRegister(RC);
5221 unsigned CmpVal = MRI.createVirtualRegister(RC);
5222 unsigned SwapVal = MRI.createVirtualRegister(RC);
5223 unsigned StoreVal = MRI.createVirtualRegister(RC);
5224 unsigned RetryOldVal = MRI.createVirtualRegister(RC);
5225 unsigned RetryCmpVal = MRI.createVirtualRegister(RC);
5226 unsigned RetrySwapVal = MRI.createVirtualRegister(RC);
5228 // Insert 2 basic blocks for the loop.
5229 MachineBasicBlock *StartMBB = MBB;
5230 MachineBasicBlock *DoneMBB = splitBlockBefore(MI, MBB);
5231 MachineBasicBlock *LoopMBB = emitBlockAfter(StartMBB);
5232 MachineBasicBlock *SetMBB = emitBlockAfter(LoopMBB);
5236 // %OrigOldVal = L Disp(%Base)
5237 // # fall through to LoopMMB
5239 BuildMI(MBB, DL, TII->get(LOpcode), OrigOldVal)
5240 .addOperand(Base).addImm(Disp).addReg(0);
5241 MBB->addSuccessor(LoopMBB);
5244 // %OldVal = phi [ %OrigOldVal, EntryBB ], [ %RetryOldVal, SetMBB ]
5245 // %CmpVal = phi [ %OrigCmpVal, EntryBB ], [ %RetryCmpVal, SetMBB ]
5246 // %SwapVal = phi [ %OrigSwapVal, EntryBB ], [ %RetrySwapVal, SetMBB ]
5247 // %Dest = RLL %OldVal, BitSize(%BitShift)
5248 // ^^ The low BitSize bits contain the field
5250 // %RetryCmpVal = RISBG32 %CmpVal, %Dest, 32, 63-BitSize, 0
5251 // ^^ Replace the upper 32-BitSize bits of the
5252 // comparison value with those that we loaded,
5253 // so that we can use a full word comparison.
5254 // CR %Dest, %RetryCmpVal
5256 // # Fall through to SetMBB
5258 BuildMI(MBB, DL, TII->get(SystemZ::PHI), OldVal)
5259 .addReg(OrigOldVal).addMBB(StartMBB)
5260 .addReg(RetryOldVal).addMBB(SetMBB);
5261 BuildMI(MBB, DL, TII->get(SystemZ::PHI), CmpVal)
5262 .addReg(OrigCmpVal).addMBB(StartMBB)
5263 .addReg(RetryCmpVal).addMBB(SetMBB);
5264 BuildMI(MBB, DL, TII->get(SystemZ::PHI), SwapVal)
5265 .addReg(OrigSwapVal).addMBB(StartMBB)
5266 .addReg(RetrySwapVal).addMBB(SetMBB);
5267 BuildMI(MBB, DL, TII->get(SystemZ::RLL), Dest)
5268 .addReg(OldVal).addReg(BitShift).addImm(BitSize);
5269 BuildMI(MBB, DL, TII->get(SystemZ::RISBG32), RetryCmpVal)
5270 .addReg(CmpVal).addReg(Dest).addImm(32).addImm(63 - BitSize).addImm(0);
5271 BuildMI(MBB, DL, TII->get(SystemZ::CR))
5272 .addReg(Dest).addReg(RetryCmpVal);
5273 BuildMI(MBB, DL, TII->get(SystemZ::BRC))
5274 .addImm(SystemZ::CCMASK_ICMP)
5275 .addImm(SystemZ::CCMASK_CMP_NE).addMBB(DoneMBB);
5276 MBB->addSuccessor(DoneMBB);
5277 MBB->addSuccessor(SetMBB);
5280 // %RetrySwapVal = RISBG32 %SwapVal, %Dest, 32, 63-BitSize, 0
5281 // ^^ Replace the upper 32-BitSize bits of the new
5282 // value with those that we loaded.
5283 // %StoreVal = RLL %RetrySwapVal, -BitSize(%NegBitShift)
5284 // ^^ Rotate the new field to its proper position.
5285 // %RetryOldVal = CS %Dest, %StoreVal, Disp(%Base)
5287 // # fall through to ExitMMB
5289 BuildMI(MBB, DL, TII->get(SystemZ::RISBG32), RetrySwapVal)
5290 .addReg(SwapVal).addReg(Dest).addImm(32).addImm(63 - BitSize).addImm(0);
5291 BuildMI(MBB, DL, TII->get(SystemZ::RLL), StoreVal)
5292 .addReg(RetrySwapVal).addReg(NegBitShift).addImm(-BitSize);
5293 BuildMI(MBB, DL, TII->get(CSOpcode), RetryOldVal)
5294 .addReg(OldVal).addReg(StoreVal).addOperand(Base).addImm(Disp);
5295 BuildMI(MBB, DL, TII->get(SystemZ::BRC))
5296 .addImm(SystemZ::CCMASK_CS).addImm(SystemZ::CCMASK_CS_NE).addMBB(LoopMBB);
5297 MBB->addSuccessor(LoopMBB);
5298 MBB->addSuccessor(DoneMBB);
5300 MI->eraseFromParent();
5304 // Emit an extension from a GR32 or GR64 to a GR128. ClearEven is true
5305 // if the high register of the GR128 value must be cleared or false if
5306 // it's "don't care". SubReg is subreg_l32 when extending a GR32
5307 // and subreg_l64 when extending a GR64.
5309 SystemZTargetLowering::emitExt128(MachineInstr *MI,
5310 MachineBasicBlock *MBB,
5311 bool ClearEven, unsigned SubReg) const {
5312 MachineFunction &MF = *MBB->getParent();
5313 const SystemZInstrInfo *TII =
5314 static_cast<const SystemZInstrInfo *>(Subtarget.getInstrInfo());
5315 MachineRegisterInfo &MRI = MF.getRegInfo();
5316 DebugLoc DL = MI->getDebugLoc();
5318 unsigned Dest = MI->getOperand(0).getReg();
5319 unsigned Src = MI->getOperand(1).getReg();
5320 unsigned In128 = MRI.createVirtualRegister(&SystemZ::GR128BitRegClass);
5322 BuildMI(*MBB, MI, DL, TII->get(TargetOpcode::IMPLICIT_DEF), In128);
5324 unsigned NewIn128 = MRI.createVirtualRegister(&SystemZ::GR128BitRegClass);
5325 unsigned Zero64 = MRI.createVirtualRegister(&SystemZ::GR64BitRegClass);
5327 BuildMI(*MBB, MI, DL, TII->get(SystemZ::LLILL), Zero64)
5329 BuildMI(*MBB, MI, DL, TII->get(TargetOpcode::INSERT_SUBREG), NewIn128)
5330 .addReg(In128).addReg(Zero64).addImm(SystemZ::subreg_h64);
5333 BuildMI(*MBB, MI, DL, TII->get(TargetOpcode::INSERT_SUBREG), Dest)
5334 .addReg(In128).addReg(Src).addImm(SubReg);
5336 MI->eraseFromParent();
5341 SystemZTargetLowering::emitMemMemWrapper(MachineInstr *MI,
5342 MachineBasicBlock *MBB,
5343 unsigned Opcode) const {
5344 MachineFunction &MF = *MBB->getParent();
5345 const SystemZInstrInfo *TII =
5346 static_cast<const SystemZInstrInfo *>(Subtarget.getInstrInfo());
5347 MachineRegisterInfo &MRI = MF.getRegInfo();
5348 DebugLoc DL = MI->getDebugLoc();
5350 MachineOperand DestBase = earlyUseOperand(MI->getOperand(0));
5351 uint64_t DestDisp = MI->getOperand(1).getImm();
5352 MachineOperand SrcBase = earlyUseOperand(MI->getOperand(2));
5353 uint64_t SrcDisp = MI->getOperand(3).getImm();
5354 uint64_t Length = MI->getOperand(4).getImm();
5356 // When generating more than one CLC, all but the last will need to
5357 // branch to the end when a difference is found.
5358 MachineBasicBlock *EndMBB = (Length > 256 && Opcode == SystemZ::CLC ?
5359 splitBlockAfter(MI, MBB) : nullptr);
5361 // Check for the loop form, in which operand 5 is the trip count.
5362 if (MI->getNumExplicitOperands() > 5) {
5363 bool HaveSingleBase = DestBase.isIdenticalTo(SrcBase);
5365 uint64_t StartCountReg = MI->getOperand(5).getReg();
5366 uint64_t StartSrcReg = forceReg(MI, SrcBase, TII);
5367 uint64_t StartDestReg = (HaveSingleBase ? StartSrcReg :
5368 forceReg(MI, DestBase, TII));
5370 const TargetRegisterClass *RC = &SystemZ::ADDR64BitRegClass;
5371 uint64_t ThisSrcReg = MRI.createVirtualRegister(RC);
5372 uint64_t ThisDestReg = (HaveSingleBase ? ThisSrcReg :
5373 MRI.createVirtualRegister(RC));
5374 uint64_t NextSrcReg = MRI.createVirtualRegister(RC);
5375 uint64_t NextDestReg = (HaveSingleBase ? NextSrcReg :
5376 MRI.createVirtualRegister(RC));
5378 RC = &SystemZ::GR64BitRegClass;
5379 uint64_t ThisCountReg = MRI.createVirtualRegister(RC);
5380 uint64_t NextCountReg = MRI.createVirtualRegister(RC);
5382 MachineBasicBlock *StartMBB = MBB;
5383 MachineBasicBlock *DoneMBB = splitBlockBefore(MI, MBB);
5384 MachineBasicBlock *LoopMBB = emitBlockAfter(StartMBB);
5385 MachineBasicBlock *NextMBB = (EndMBB ? emitBlockAfter(LoopMBB) : LoopMBB);
5388 // # fall through to LoopMMB
5389 MBB->addSuccessor(LoopMBB);
5392 // %ThisDestReg = phi [ %StartDestReg, StartMBB ],
5393 // [ %NextDestReg, NextMBB ]
5394 // %ThisSrcReg = phi [ %StartSrcReg, StartMBB ],
5395 // [ %NextSrcReg, NextMBB ]
5396 // %ThisCountReg = phi [ %StartCountReg, StartMBB ],
5397 // [ %NextCountReg, NextMBB ]
5398 // ( PFD 2, 768+DestDisp(%ThisDestReg) )
5399 // Opcode DestDisp(256,%ThisDestReg), SrcDisp(%ThisSrcReg)
5402 // The prefetch is used only for MVC. The JLH is used only for CLC.
5405 BuildMI(MBB, DL, TII->get(SystemZ::PHI), ThisDestReg)
5406 .addReg(StartDestReg).addMBB(StartMBB)
5407 .addReg(NextDestReg).addMBB(NextMBB);
5408 if (!HaveSingleBase)
5409 BuildMI(MBB, DL, TII->get(SystemZ::PHI), ThisSrcReg)
5410 .addReg(StartSrcReg).addMBB(StartMBB)
5411 .addReg(NextSrcReg).addMBB(NextMBB);
5412 BuildMI(MBB, DL, TII->get(SystemZ::PHI), ThisCountReg)
5413 .addReg(StartCountReg).addMBB(StartMBB)
5414 .addReg(NextCountReg).addMBB(NextMBB);
5415 if (Opcode == SystemZ::MVC)
5416 BuildMI(MBB, DL, TII->get(SystemZ::PFD))
5417 .addImm(SystemZ::PFD_WRITE)
5418 .addReg(ThisDestReg).addImm(DestDisp + 768).addReg(0);
5419 BuildMI(MBB, DL, TII->get(Opcode))
5420 .addReg(ThisDestReg).addImm(DestDisp).addImm(256)
5421 .addReg(ThisSrcReg).addImm(SrcDisp);
5423 BuildMI(MBB, DL, TII->get(SystemZ::BRC))
5424 .addImm(SystemZ::CCMASK_ICMP).addImm(SystemZ::CCMASK_CMP_NE)
5426 MBB->addSuccessor(EndMBB);
5427 MBB->addSuccessor(NextMBB);
5431 // %NextDestReg = LA 256(%ThisDestReg)
5432 // %NextSrcReg = LA 256(%ThisSrcReg)
5433 // %NextCountReg = AGHI %ThisCountReg, -1
5434 // CGHI %NextCountReg, 0
5436 // # fall through to DoneMMB
5438 // The AGHI, CGHI and JLH should be converted to BRCTG by later passes.
5441 BuildMI(MBB, DL, TII->get(SystemZ::LA), NextDestReg)
5442 .addReg(ThisDestReg).addImm(256).addReg(0);
5443 if (!HaveSingleBase)
5444 BuildMI(MBB, DL, TII->get(SystemZ::LA), NextSrcReg)
5445 .addReg(ThisSrcReg).addImm(256).addReg(0);
5446 BuildMI(MBB, DL, TII->get(SystemZ::AGHI), NextCountReg)
5447 .addReg(ThisCountReg).addImm(-1);
5448 BuildMI(MBB, DL, TII->get(SystemZ::CGHI))
5449 .addReg(NextCountReg).addImm(0);
5450 BuildMI(MBB, DL, TII->get(SystemZ::BRC))
5451 .addImm(SystemZ::CCMASK_ICMP).addImm(SystemZ::CCMASK_CMP_NE)
5453 MBB->addSuccessor(LoopMBB);
5454 MBB->addSuccessor(DoneMBB);
5456 DestBase = MachineOperand::CreateReg(NextDestReg, false);
5457 SrcBase = MachineOperand::CreateReg(NextSrcReg, false);
5461 // Handle any remaining bytes with straight-line code.
5462 while (Length > 0) {
5463 uint64_t ThisLength = std::min(Length, uint64_t(256));
5464 // The previous iteration might have created out-of-range displacements.
5465 // Apply them using LAY if so.
5466 if (!isUInt<12>(DestDisp)) {
5467 unsigned Reg = MRI.createVirtualRegister(&SystemZ::ADDR64BitRegClass);
5468 BuildMI(*MBB, MI, MI->getDebugLoc(), TII->get(SystemZ::LAY), Reg)
5469 .addOperand(DestBase).addImm(DestDisp).addReg(0);
5470 DestBase = MachineOperand::CreateReg(Reg, false);
5473 if (!isUInt<12>(SrcDisp)) {
5474 unsigned Reg = MRI.createVirtualRegister(&SystemZ::ADDR64BitRegClass);
5475 BuildMI(*MBB, MI, MI->getDebugLoc(), TII->get(SystemZ::LAY), Reg)
5476 .addOperand(SrcBase).addImm(SrcDisp).addReg(0);
5477 SrcBase = MachineOperand::CreateReg(Reg, false);
5480 BuildMI(*MBB, MI, DL, TII->get(Opcode))
5481 .addOperand(DestBase).addImm(DestDisp).addImm(ThisLength)
5482 .addOperand(SrcBase).addImm(SrcDisp);
5483 DestDisp += ThisLength;
5484 SrcDisp += ThisLength;
5485 Length -= ThisLength;
5486 // If there's another CLC to go, branch to the end if a difference
5488 if (EndMBB && Length > 0) {
5489 MachineBasicBlock *NextMBB = splitBlockBefore(MI, MBB);
5490 BuildMI(MBB, DL, TII->get(SystemZ::BRC))
5491 .addImm(SystemZ::CCMASK_ICMP).addImm(SystemZ::CCMASK_CMP_NE)
5493 MBB->addSuccessor(EndMBB);
5494 MBB->addSuccessor(NextMBB);
5499 MBB->addSuccessor(EndMBB);
5501 MBB->addLiveIn(SystemZ::CC);
5504 MI->eraseFromParent();
5508 // Decompose string pseudo-instruction MI into a loop that continually performs
5509 // Opcode until CC != 3.
5511 SystemZTargetLowering::emitStringWrapper(MachineInstr *MI,
5512 MachineBasicBlock *MBB,
5513 unsigned Opcode) const {
5514 MachineFunction &MF = *MBB->getParent();
5515 const SystemZInstrInfo *TII =
5516 static_cast<const SystemZInstrInfo *>(Subtarget.getInstrInfo());
5517 MachineRegisterInfo &MRI = MF.getRegInfo();
5518 DebugLoc DL = MI->getDebugLoc();
5520 uint64_t End1Reg = MI->getOperand(0).getReg();
5521 uint64_t Start1Reg = MI->getOperand(1).getReg();
5522 uint64_t Start2Reg = MI->getOperand(2).getReg();
5523 uint64_t CharReg = MI->getOperand(3).getReg();
5525 const TargetRegisterClass *RC = &SystemZ::GR64BitRegClass;
5526 uint64_t This1Reg = MRI.createVirtualRegister(RC);
5527 uint64_t This2Reg = MRI.createVirtualRegister(RC);
5528 uint64_t End2Reg = MRI.createVirtualRegister(RC);
5530 MachineBasicBlock *StartMBB = MBB;
5531 MachineBasicBlock *DoneMBB = splitBlockBefore(MI, MBB);
5532 MachineBasicBlock *LoopMBB = emitBlockAfter(StartMBB);
5535 // # fall through to LoopMMB
5536 MBB->addSuccessor(LoopMBB);
5539 // %This1Reg = phi [ %Start1Reg, StartMBB ], [ %End1Reg, LoopMBB ]
5540 // %This2Reg = phi [ %Start2Reg, StartMBB ], [ %End2Reg, LoopMBB ]
5542 // %End1Reg, %End2Reg = CLST %This1Reg, %This2Reg -- uses R0L
5544 // # fall through to DoneMMB
5546 // The load of R0L can be hoisted by post-RA LICM.
5549 BuildMI(MBB, DL, TII->get(SystemZ::PHI), This1Reg)
5550 .addReg(Start1Reg).addMBB(StartMBB)
5551 .addReg(End1Reg).addMBB(LoopMBB);
5552 BuildMI(MBB, DL, TII->get(SystemZ::PHI), This2Reg)
5553 .addReg(Start2Reg).addMBB(StartMBB)
5554 .addReg(End2Reg).addMBB(LoopMBB);
5555 BuildMI(MBB, DL, TII->get(TargetOpcode::COPY), SystemZ::R0L).addReg(CharReg);
5556 BuildMI(MBB, DL, TII->get(Opcode))
5557 .addReg(End1Reg, RegState::Define).addReg(End2Reg, RegState::Define)
5558 .addReg(This1Reg).addReg(This2Reg);
5559 BuildMI(MBB, DL, TII->get(SystemZ::BRC))
5560 .addImm(SystemZ::CCMASK_ANY).addImm(SystemZ::CCMASK_3).addMBB(LoopMBB);
5561 MBB->addSuccessor(LoopMBB);
5562 MBB->addSuccessor(DoneMBB);
5564 DoneMBB->addLiveIn(SystemZ::CC);
5566 MI->eraseFromParent();
5570 // Update TBEGIN instruction with final opcode and register clobbers.
5572 SystemZTargetLowering::emitTransactionBegin(MachineInstr *MI,
5573 MachineBasicBlock *MBB,
5575 bool NoFloat) const {
5576 MachineFunction &MF = *MBB->getParent();
5577 const TargetFrameLowering *TFI = Subtarget.getFrameLowering();
5578 const SystemZInstrInfo *TII = Subtarget.getInstrInfo();
5581 MI->setDesc(TII->get(Opcode));
5583 // We cannot handle a TBEGIN that clobbers the stack or frame pointer.
5584 // Make sure to add the corresponding GRSM bits if they are missing.
5585 uint64_t Control = MI->getOperand(2).getImm();
5586 static const unsigned GPRControlBit[16] = {
5587 0x8000, 0x8000, 0x4000, 0x4000, 0x2000, 0x2000, 0x1000, 0x1000,
5588 0x0800, 0x0800, 0x0400, 0x0400, 0x0200, 0x0200, 0x0100, 0x0100
5590 Control |= GPRControlBit[15];
5592 Control |= GPRControlBit[11];
5593 MI->getOperand(2).setImm(Control);
5595 // Add GPR clobbers.
5596 for (int I = 0; I < 16; I++) {
5597 if ((Control & GPRControlBit[I]) == 0) {
5598 unsigned Reg = SystemZMC::GR64Regs[I];
5599 MI->addOperand(MachineOperand::CreateReg(Reg, true, true));
5603 // Add FPR/VR clobbers.
5604 if (!NoFloat && (Control & 4) != 0) {
5605 if (Subtarget.hasVector()) {
5606 for (int I = 0; I < 32; I++) {
5607 unsigned Reg = SystemZMC::VR128Regs[I];
5608 MI->addOperand(MachineOperand::CreateReg(Reg, true, true));
5611 for (int I = 0; I < 16; I++) {
5612 unsigned Reg = SystemZMC::FP64Regs[I];
5613 MI->addOperand(MachineOperand::CreateReg(Reg, true, true));
5622 SystemZTargetLowering::emitLoadAndTestCmp0(MachineInstr *MI,
5623 MachineBasicBlock *MBB,
5624 unsigned Opcode) const {
5625 MachineFunction &MF = *MBB->getParent();
5626 MachineRegisterInfo *MRI = &MF.getRegInfo();
5627 const SystemZInstrInfo *TII =
5628 static_cast<const SystemZInstrInfo *>(Subtarget.getInstrInfo());
5629 DebugLoc DL = MI->getDebugLoc();
5631 unsigned SrcReg = MI->getOperand(0).getReg();
5633 // Create new virtual register of the same class as source.
5634 const TargetRegisterClass *RC = MRI->getRegClass(SrcReg);
5635 unsigned DstReg = MRI->createVirtualRegister(RC);
5637 // Replace pseudo with a normal load-and-test that models the def as
5639 BuildMI(*MBB, MI, DL, TII->get(Opcode), DstReg)
5641 MI->eraseFromParent();
5646 MachineBasicBlock *SystemZTargetLowering::
5647 EmitInstrWithCustomInserter(MachineInstr *MI, MachineBasicBlock *MBB) const {
5648 switch (MI->getOpcode()) {
5649 case SystemZ::Select32Mux:
5650 case SystemZ::Select32:
5651 case SystemZ::SelectF32:
5652 case SystemZ::Select64:
5653 case SystemZ::SelectF64:
5654 case SystemZ::SelectF128:
5655 return emitSelect(MI, MBB);
5657 case SystemZ::CondStore8Mux:
5658 return emitCondStore(MI, MBB, SystemZ::STCMux, 0, false);
5659 case SystemZ::CondStore8MuxInv:
5660 return emitCondStore(MI, MBB, SystemZ::STCMux, 0, true);
5661 case SystemZ::CondStore16Mux:
5662 return emitCondStore(MI, MBB, SystemZ::STHMux, 0, false);
5663 case SystemZ::CondStore16MuxInv:
5664 return emitCondStore(MI, MBB, SystemZ::STHMux, 0, true);
5665 case SystemZ::CondStore8:
5666 return emitCondStore(MI, MBB, SystemZ::STC, 0, false);
5667 case SystemZ::CondStore8Inv:
5668 return emitCondStore(MI, MBB, SystemZ::STC, 0, true);
5669 case SystemZ::CondStore16:
5670 return emitCondStore(MI, MBB, SystemZ::STH, 0, false);
5671 case SystemZ::CondStore16Inv:
5672 return emitCondStore(MI, MBB, SystemZ::STH, 0, true);
5673 case SystemZ::CondStore32:
5674 return emitCondStore(MI, MBB, SystemZ::ST, SystemZ::STOC, false);
5675 case SystemZ::CondStore32Inv:
5676 return emitCondStore(MI, MBB, SystemZ::ST, SystemZ::STOC, true);
5677 case SystemZ::CondStore64:
5678 return emitCondStore(MI, MBB, SystemZ::STG, SystemZ::STOCG, false);
5679 case SystemZ::CondStore64Inv:
5680 return emitCondStore(MI, MBB, SystemZ::STG, SystemZ::STOCG, true);
5681 case SystemZ::CondStoreF32:
5682 return emitCondStore(MI, MBB, SystemZ::STE, 0, false);
5683 case SystemZ::CondStoreF32Inv:
5684 return emitCondStore(MI, MBB, SystemZ::STE, 0, true);
5685 case SystemZ::CondStoreF64:
5686 return emitCondStore(MI, MBB, SystemZ::STD, 0, false);
5687 case SystemZ::CondStoreF64Inv:
5688 return emitCondStore(MI, MBB, SystemZ::STD, 0, true);
5690 case SystemZ::AEXT128_64:
5691 return emitExt128(MI, MBB, false, SystemZ::subreg_l64);
5692 case SystemZ::ZEXT128_32:
5693 return emitExt128(MI, MBB, true, SystemZ::subreg_l32);
5694 case SystemZ::ZEXT128_64:
5695 return emitExt128(MI, MBB, true, SystemZ::subreg_l64);
5697 case SystemZ::ATOMIC_SWAPW:
5698 return emitAtomicLoadBinary(MI, MBB, 0, 0);
5699 case SystemZ::ATOMIC_SWAP_32:
5700 return emitAtomicLoadBinary(MI, MBB, 0, 32);
5701 case SystemZ::ATOMIC_SWAP_64:
5702 return emitAtomicLoadBinary(MI, MBB, 0, 64);
5704 case SystemZ::ATOMIC_LOADW_AR:
5705 return emitAtomicLoadBinary(MI, MBB, SystemZ::AR, 0);
5706 case SystemZ::ATOMIC_LOADW_AFI:
5707 return emitAtomicLoadBinary(MI, MBB, SystemZ::AFI, 0);
5708 case SystemZ::ATOMIC_LOAD_AR:
5709 return emitAtomicLoadBinary(MI, MBB, SystemZ::AR, 32);
5710 case SystemZ::ATOMIC_LOAD_AHI:
5711 return emitAtomicLoadBinary(MI, MBB, SystemZ::AHI, 32);
5712 case SystemZ::ATOMIC_LOAD_AFI:
5713 return emitAtomicLoadBinary(MI, MBB, SystemZ::AFI, 32);
5714 case SystemZ::ATOMIC_LOAD_AGR:
5715 return emitAtomicLoadBinary(MI, MBB, SystemZ::AGR, 64);
5716 case SystemZ::ATOMIC_LOAD_AGHI:
5717 return emitAtomicLoadBinary(MI, MBB, SystemZ::AGHI, 64);
5718 case SystemZ::ATOMIC_LOAD_AGFI:
5719 return emitAtomicLoadBinary(MI, MBB, SystemZ::AGFI, 64);
5721 case SystemZ::ATOMIC_LOADW_SR:
5722 return emitAtomicLoadBinary(MI, MBB, SystemZ::SR, 0);
5723 case SystemZ::ATOMIC_LOAD_SR:
5724 return emitAtomicLoadBinary(MI, MBB, SystemZ::SR, 32);
5725 case SystemZ::ATOMIC_LOAD_SGR:
5726 return emitAtomicLoadBinary(MI, MBB, SystemZ::SGR, 64);
5728 case SystemZ::ATOMIC_LOADW_NR:
5729 return emitAtomicLoadBinary(MI, MBB, SystemZ::NR, 0);
5730 case SystemZ::ATOMIC_LOADW_NILH:
5731 return emitAtomicLoadBinary(MI, MBB, SystemZ::NILH, 0);
5732 case SystemZ::ATOMIC_LOAD_NR:
5733 return emitAtomicLoadBinary(MI, MBB, SystemZ::NR, 32);
5734 case SystemZ::ATOMIC_LOAD_NILL:
5735 return emitAtomicLoadBinary(MI, MBB, SystemZ::NILL, 32);
5736 case SystemZ::ATOMIC_LOAD_NILH:
5737 return emitAtomicLoadBinary(MI, MBB, SystemZ::NILH, 32);
5738 case SystemZ::ATOMIC_LOAD_NILF:
5739 return emitAtomicLoadBinary(MI, MBB, SystemZ::NILF, 32);
5740 case SystemZ::ATOMIC_LOAD_NGR:
5741 return emitAtomicLoadBinary(MI, MBB, SystemZ::NGR, 64);
5742 case SystemZ::ATOMIC_LOAD_NILL64:
5743 return emitAtomicLoadBinary(MI, MBB, SystemZ::NILL64, 64);
5744 case SystemZ::ATOMIC_LOAD_NILH64:
5745 return emitAtomicLoadBinary(MI, MBB, SystemZ::NILH64, 64);
5746 case SystemZ::ATOMIC_LOAD_NIHL64:
5747 return emitAtomicLoadBinary(MI, MBB, SystemZ::NIHL64, 64);
5748 case SystemZ::ATOMIC_LOAD_NIHH64:
5749 return emitAtomicLoadBinary(MI, MBB, SystemZ::NIHH64, 64);
5750 case SystemZ::ATOMIC_LOAD_NILF64:
5751 return emitAtomicLoadBinary(MI, MBB, SystemZ::NILF64, 64);
5752 case SystemZ::ATOMIC_LOAD_NIHF64:
5753 return emitAtomicLoadBinary(MI, MBB, SystemZ::NIHF64, 64);
5755 case SystemZ::ATOMIC_LOADW_OR:
5756 return emitAtomicLoadBinary(MI, MBB, SystemZ::OR, 0);
5757 case SystemZ::ATOMIC_LOADW_OILH:
5758 return emitAtomicLoadBinary(MI, MBB, SystemZ::OILH, 0);
5759 case SystemZ::ATOMIC_LOAD_OR:
5760 return emitAtomicLoadBinary(MI, MBB, SystemZ::OR, 32);
5761 case SystemZ::ATOMIC_LOAD_OILL:
5762 return emitAtomicLoadBinary(MI, MBB, SystemZ::OILL, 32);
5763 case SystemZ::ATOMIC_LOAD_OILH:
5764 return emitAtomicLoadBinary(MI, MBB, SystemZ::OILH, 32);
5765 case SystemZ::ATOMIC_LOAD_OILF:
5766 return emitAtomicLoadBinary(MI, MBB, SystemZ::OILF, 32);
5767 case SystemZ::ATOMIC_LOAD_OGR:
5768 return emitAtomicLoadBinary(MI, MBB, SystemZ::OGR, 64);
5769 case SystemZ::ATOMIC_LOAD_OILL64:
5770 return emitAtomicLoadBinary(MI, MBB, SystemZ::OILL64, 64);
5771 case SystemZ::ATOMIC_LOAD_OILH64:
5772 return emitAtomicLoadBinary(MI, MBB, SystemZ::OILH64, 64);
5773 case SystemZ::ATOMIC_LOAD_OIHL64:
5774 return emitAtomicLoadBinary(MI, MBB, SystemZ::OIHL64, 64);
5775 case SystemZ::ATOMIC_LOAD_OIHH64:
5776 return emitAtomicLoadBinary(MI, MBB, SystemZ::OIHH64, 64);
5777 case SystemZ::ATOMIC_LOAD_OILF64:
5778 return emitAtomicLoadBinary(MI, MBB, SystemZ::OILF64, 64);
5779 case SystemZ::ATOMIC_LOAD_OIHF64:
5780 return emitAtomicLoadBinary(MI, MBB, SystemZ::OIHF64, 64);
5782 case SystemZ::ATOMIC_LOADW_XR:
5783 return emitAtomicLoadBinary(MI, MBB, SystemZ::XR, 0);
5784 case SystemZ::ATOMIC_LOADW_XILF:
5785 return emitAtomicLoadBinary(MI, MBB, SystemZ::XILF, 0);
5786 case SystemZ::ATOMIC_LOAD_XR:
5787 return emitAtomicLoadBinary(MI, MBB, SystemZ::XR, 32);
5788 case SystemZ::ATOMIC_LOAD_XILF:
5789 return emitAtomicLoadBinary(MI, MBB, SystemZ::XILF, 32);
5790 case SystemZ::ATOMIC_LOAD_XGR:
5791 return emitAtomicLoadBinary(MI, MBB, SystemZ::XGR, 64);
5792 case SystemZ::ATOMIC_LOAD_XILF64:
5793 return emitAtomicLoadBinary(MI, MBB, SystemZ::XILF64, 64);
5794 case SystemZ::ATOMIC_LOAD_XIHF64:
5795 return emitAtomicLoadBinary(MI, MBB, SystemZ::XIHF64, 64);
5797 case SystemZ::ATOMIC_LOADW_NRi:
5798 return emitAtomicLoadBinary(MI, MBB, SystemZ::NR, 0, true);
5799 case SystemZ::ATOMIC_LOADW_NILHi:
5800 return emitAtomicLoadBinary(MI, MBB, SystemZ::NILH, 0, true);
5801 case SystemZ::ATOMIC_LOAD_NRi:
5802 return emitAtomicLoadBinary(MI, MBB, SystemZ::NR, 32, true);
5803 case SystemZ::ATOMIC_LOAD_NILLi:
5804 return emitAtomicLoadBinary(MI, MBB, SystemZ::NILL, 32, true);
5805 case SystemZ::ATOMIC_LOAD_NILHi:
5806 return emitAtomicLoadBinary(MI, MBB, SystemZ::NILH, 32, true);
5807 case SystemZ::ATOMIC_LOAD_NILFi:
5808 return emitAtomicLoadBinary(MI, MBB, SystemZ::NILF, 32, true);
5809 case SystemZ::ATOMIC_LOAD_NGRi:
5810 return emitAtomicLoadBinary(MI, MBB, SystemZ::NGR, 64, true);
5811 case SystemZ::ATOMIC_LOAD_NILL64i:
5812 return emitAtomicLoadBinary(MI, MBB, SystemZ::NILL64, 64, true);
5813 case SystemZ::ATOMIC_LOAD_NILH64i:
5814 return emitAtomicLoadBinary(MI, MBB, SystemZ::NILH64, 64, true);
5815 case SystemZ::ATOMIC_LOAD_NIHL64i:
5816 return emitAtomicLoadBinary(MI, MBB, SystemZ::NIHL64, 64, true);
5817 case SystemZ::ATOMIC_LOAD_NIHH64i:
5818 return emitAtomicLoadBinary(MI, MBB, SystemZ::NIHH64, 64, true);
5819 case SystemZ::ATOMIC_LOAD_NILF64i:
5820 return emitAtomicLoadBinary(MI, MBB, SystemZ::NILF64, 64, true);
5821 case SystemZ::ATOMIC_LOAD_NIHF64i:
5822 return emitAtomicLoadBinary(MI, MBB, SystemZ::NIHF64, 64, true);
5824 case SystemZ::ATOMIC_LOADW_MIN:
5825 return emitAtomicLoadMinMax(MI, MBB, SystemZ::CR,
5826 SystemZ::CCMASK_CMP_LE, 0);
5827 case SystemZ::ATOMIC_LOAD_MIN_32:
5828 return emitAtomicLoadMinMax(MI, MBB, SystemZ::CR,
5829 SystemZ::CCMASK_CMP_LE, 32);
5830 case SystemZ::ATOMIC_LOAD_MIN_64:
5831 return emitAtomicLoadMinMax(MI, MBB, SystemZ::CGR,
5832 SystemZ::CCMASK_CMP_LE, 64);
5834 case SystemZ::ATOMIC_LOADW_MAX:
5835 return emitAtomicLoadMinMax(MI, MBB, SystemZ::CR,
5836 SystemZ::CCMASK_CMP_GE, 0);
5837 case SystemZ::ATOMIC_LOAD_MAX_32:
5838 return emitAtomicLoadMinMax(MI, MBB, SystemZ::CR,
5839 SystemZ::CCMASK_CMP_GE, 32);
5840 case SystemZ::ATOMIC_LOAD_MAX_64:
5841 return emitAtomicLoadMinMax(MI, MBB, SystemZ::CGR,
5842 SystemZ::CCMASK_CMP_GE, 64);
5844 case SystemZ::ATOMIC_LOADW_UMIN:
5845 return emitAtomicLoadMinMax(MI, MBB, SystemZ::CLR,
5846 SystemZ::CCMASK_CMP_LE, 0);
5847 case SystemZ::ATOMIC_LOAD_UMIN_32:
5848 return emitAtomicLoadMinMax(MI, MBB, SystemZ::CLR,
5849 SystemZ::CCMASK_CMP_LE, 32);
5850 case SystemZ::ATOMIC_LOAD_UMIN_64:
5851 return emitAtomicLoadMinMax(MI, MBB, SystemZ::CLGR,
5852 SystemZ::CCMASK_CMP_LE, 64);
5854 case SystemZ::ATOMIC_LOADW_UMAX:
5855 return emitAtomicLoadMinMax(MI, MBB, SystemZ::CLR,
5856 SystemZ::CCMASK_CMP_GE, 0);
5857 case SystemZ::ATOMIC_LOAD_UMAX_32:
5858 return emitAtomicLoadMinMax(MI, MBB, SystemZ::CLR,
5859 SystemZ::CCMASK_CMP_GE, 32);
5860 case SystemZ::ATOMIC_LOAD_UMAX_64:
5861 return emitAtomicLoadMinMax(MI, MBB, SystemZ::CLGR,
5862 SystemZ::CCMASK_CMP_GE, 64);
5864 case SystemZ::ATOMIC_CMP_SWAPW:
5865 return emitAtomicCmpSwapW(MI, MBB);
5866 case SystemZ::MVCSequence:
5867 case SystemZ::MVCLoop:
5868 return emitMemMemWrapper(MI, MBB, SystemZ::MVC);
5869 case SystemZ::NCSequence:
5870 case SystemZ::NCLoop:
5871 return emitMemMemWrapper(MI, MBB, SystemZ::NC);
5872 case SystemZ::OCSequence:
5873 case SystemZ::OCLoop:
5874 return emitMemMemWrapper(MI, MBB, SystemZ::OC);
5875 case SystemZ::XCSequence:
5876 case SystemZ::XCLoop:
5877 return emitMemMemWrapper(MI, MBB, SystemZ::XC);
5878 case SystemZ::CLCSequence:
5879 case SystemZ::CLCLoop:
5880 return emitMemMemWrapper(MI, MBB, SystemZ::CLC);
5881 case SystemZ::CLSTLoop:
5882 return emitStringWrapper(MI, MBB, SystemZ::CLST);
5883 case SystemZ::MVSTLoop:
5884 return emitStringWrapper(MI, MBB, SystemZ::MVST);
5885 case SystemZ::SRSTLoop:
5886 return emitStringWrapper(MI, MBB, SystemZ::SRST);
5887 case SystemZ::TBEGIN:
5888 return emitTransactionBegin(MI, MBB, SystemZ::TBEGIN, false);
5889 case SystemZ::TBEGIN_nofloat:
5890 return emitTransactionBegin(MI, MBB, SystemZ::TBEGIN, true);
5891 case SystemZ::TBEGINC:
5892 return emitTransactionBegin(MI, MBB, SystemZ::TBEGINC, true);
5893 case SystemZ::LTEBRCompare_VecPseudo:
5894 return emitLoadAndTestCmp0(MI, MBB, SystemZ::LTEBR);
5895 case SystemZ::LTDBRCompare_VecPseudo:
5896 return emitLoadAndTestCmp0(MI, MBB, SystemZ::LTDBR);
5897 case SystemZ::LTXBRCompare_VecPseudo:
5898 return emitLoadAndTestCmp0(MI, MBB, SystemZ::LTXBR);
5901 llvm_unreachable("Unexpected instr type to insert");