1 //===-- SystemZISelDAGToDAG.cpp - A dag to dag inst selector for SystemZ --===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines an instruction selector for the SystemZ target.
12 //===----------------------------------------------------------------------===//
14 #include "SystemZTargetMachine.h"
15 #include "llvm/Analysis/AliasAnalysis.h"
16 #include "llvm/CodeGen/SelectionDAGISel.h"
17 #include "llvm/Support/Debug.h"
18 #include "llvm/Support/raw_ostream.h"
23 // Used to build addressing modes.
24 struct SystemZAddressingMode {
25 // The shape of the address.
30 // base+displacement+index for load and store operands
33 // base+displacement+index for load address operands
36 // base+displacement+index+ADJDYNALLOC
41 // The type of displacement. The enum names here correspond directly
42 // to the definitions in SystemZOperand.td. We could split them into
43 // flags -- single/pair, 128-bit, etc. -- but it hardly seems worth it.
53 // The parts of the address. The address is equivalent to:
55 // Base + Disp + Index + (IncludesDynAlloc ? ADJDYNALLOC : 0)
59 bool IncludesDynAlloc;
61 SystemZAddressingMode(AddrForm form, DispRange dr)
62 : Form(form), DR(dr), Base(), Disp(0), Index(),
63 IncludesDynAlloc(false) {}
65 // True if the address can have an index register.
66 bool hasIndexField() { return Form != FormBD; }
68 // True if the address can (and must) include ADJDYNALLOC.
69 bool isDynAlloc() { return Form == FormBDXDynAlloc; }
72 errs() << "SystemZAddressingMode " << this << '\n';
75 if (Base.getNode() != 0)
76 Base.getNode()->dump();
80 if (hasIndexField()) {
82 if (Index.getNode() != 0)
83 Index.getNode()->dump();
88 errs() << " Disp " << Disp;
90 errs() << " + ADJDYNALLOC";
95 // Return a mask with Count low bits set.
96 static uint64_t allOnes(unsigned int Count) {
97 return Count == 0 ? 0 : (uint64_t(1) << (Count - 1) << 1) - 1;
100 // Represents operands 2 to 5 of the ROTATE AND ... SELECTED BITS operation
101 // given by Opcode. The operands are: Input (R2), Start (I3), End (I4) and
102 // Rotate (I5). The combined operand value is effectively:
104 // (or (rotl Input, Rotate), ~Mask)
108 // (and (rotl Input, Rotate), Mask)
110 // otherwise. The value has BitSize bits.
111 struct RxSBGOperands {
112 RxSBGOperands(unsigned Op, SDValue N)
113 : Opcode(Op), BitSize(N.getValueType().getSizeInBits()),
114 Mask(allOnes(BitSize)), Input(N), Start(64 - BitSize), End(63),
126 class SystemZDAGToDAGISel : public SelectionDAGISel {
127 const SystemZTargetLowering &Lowering;
128 const SystemZSubtarget &Subtarget;
130 // Used by SystemZOperands.td to create integer constants.
131 inline SDValue getImm(const SDNode *Node, uint64_t Imm) {
132 return CurDAG->getTargetConstant(Imm, Node->getValueType(0));
135 const SystemZTargetMachine &getTargetMachine() const {
136 return static_cast<const SystemZTargetMachine &>(TM);
139 const SystemZInstrInfo *getInstrInfo() const {
140 return getTargetMachine().getInstrInfo();
143 // Try to fold more of the base or index of AM into AM, where IsBase
144 // selects between the base and index.
145 bool expandAddress(SystemZAddressingMode &AM, bool IsBase);
147 // Try to describe N in AM, returning true on success.
148 bool selectAddress(SDValue N, SystemZAddressingMode &AM);
150 // Extract individual target operands from matched address AM.
151 void getAddressOperands(const SystemZAddressingMode &AM, EVT VT,
152 SDValue &Base, SDValue &Disp);
153 void getAddressOperands(const SystemZAddressingMode &AM, EVT VT,
154 SDValue &Base, SDValue &Disp, SDValue &Index);
156 // Try to match Addr as a FormBD address with displacement type DR.
157 // Return true on success, storing the base and displacement in
158 // Base and Disp respectively.
159 bool selectBDAddr(SystemZAddressingMode::DispRange DR, SDValue Addr,
160 SDValue &Base, SDValue &Disp);
162 // Try to match Addr as a FormBDX* address of form Form with
163 // displacement type DR. Return true on success, storing the base,
164 // displacement and index in Base, Disp and Index respectively.
165 bool selectBDXAddr(SystemZAddressingMode::AddrForm Form,
166 SystemZAddressingMode::DispRange DR, SDValue Addr,
167 SDValue &Base, SDValue &Disp, SDValue &Index);
169 // PC-relative address matching routines used by SystemZOperands.td.
170 bool selectPCRelAddress(SDValue Addr, SDValue &Target) {
171 if (Addr.getOpcode() == SystemZISD::PCREL_WRAPPER) {
172 Target = Addr.getOperand(0);
178 // BD matching routines used by SystemZOperands.td.
179 bool selectBDAddr12Only(SDValue Addr, SDValue &Base, SDValue &Disp) {
180 return selectBDAddr(SystemZAddressingMode::Disp12Only, Addr, Base, Disp);
182 bool selectBDAddr12Pair(SDValue Addr, SDValue &Base, SDValue &Disp) {
183 return selectBDAddr(SystemZAddressingMode::Disp12Pair, Addr, Base, Disp);
185 bool selectBDAddr20Only(SDValue Addr, SDValue &Base, SDValue &Disp) {
186 return selectBDAddr(SystemZAddressingMode::Disp20Only, Addr, Base, Disp);
188 bool selectBDAddr20Pair(SDValue Addr, SDValue &Base, SDValue &Disp) {
189 return selectBDAddr(SystemZAddressingMode::Disp20Pair, Addr, Base, Disp);
192 // BDX matching routines used by SystemZOperands.td.
193 bool selectBDXAddr12Only(SDValue Addr, SDValue &Base, SDValue &Disp,
195 return selectBDXAddr(SystemZAddressingMode::FormBDXNormal,
196 SystemZAddressingMode::Disp12Only,
197 Addr, Base, Disp, Index);
199 bool selectBDXAddr12Pair(SDValue Addr, SDValue &Base, SDValue &Disp,
201 return selectBDXAddr(SystemZAddressingMode::FormBDXNormal,
202 SystemZAddressingMode::Disp12Pair,
203 Addr, Base, Disp, Index);
205 bool selectDynAlloc12Only(SDValue Addr, SDValue &Base, SDValue &Disp,
207 return selectBDXAddr(SystemZAddressingMode::FormBDXDynAlloc,
208 SystemZAddressingMode::Disp12Only,
209 Addr, Base, Disp, Index);
211 bool selectBDXAddr20Only(SDValue Addr, SDValue &Base, SDValue &Disp,
213 return selectBDXAddr(SystemZAddressingMode::FormBDXNormal,
214 SystemZAddressingMode::Disp20Only,
215 Addr, Base, Disp, Index);
217 bool selectBDXAddr20Only128(SDValue Addr, SDValue &Base, SDValue &Disp,
219 return selectBDXAddr(SystemZAddressingMode::FormBDXNormal,
220 SystemZAddressingMode::Disp20Only128,
221 Addr, Base, Disp, Index);
223 bool selectBDXAddr20Pair(SDValue Addr, SDValue &Base, SDValue &Disp,
225 return selectBDXAddr(SystemZAddressingMode::FormBDXNormal,
226 SystemZAddressingMode::Disp20Pair,
227 Addr, Base, Disp, Index);
229 bool selectLAAddr12Pair(SDValue Addr, SDValue &Base, SDValue &Disp,
231 return selectBDXAddr(SystemZAddressingMode::FormBDXLA,
232 SystemZAddressingMode::Disp12Pair,
233 Addr, Base, Disp, Index);
235 bool selectLAAddr20Pair(SDValue Addr, SDValue &Base, SDValue &Disp,
237 return selectBDXAddr(SystemZAddressingMode::FormBDXLA,
238 SystemZAddressingMode::Disp20Pair,
239 Addr, Base, Disp, Index);
242 // Check whether (or Op (and X InsertMask)) is effectively an insertion
243 // of X into bits InsertMask of some Y != Op. Return true if so and
245 bool detectOrAndInsertion(SDValue &Op, uint64_t InsertMask);
247 // Try to update RxSBG so that only the bits of RxSBG.Input in Mask are used.
248 // Return true on success.
249 bool refineRxSBGMask(RxSBGOperands &RxSBG, uint64_t Mask);
251 // Try to fold some of RxSBG.Input into other fields of RxSBG.
252 // Return true on success.
253 bool expandRxSBG(RxSBGOperands &RxSBG);
255 // Return an undefined i64 value.
256 SDValue getUNDEF64(SDLoc DL);
258 // Convert N to VT, if it isn't already.
259 SDValue convertTo(SDLoc DL, EVT VT, SDValue N);
261 // Try to implement AND or shift node N using RISBG with the zero flag set.
262 // Return the selected node on success, otherwise return null.
263 SDNode *tryRISBGZero(SDNode *N);
265 // Try to use RISBG or Opcode to implement OR or XOR node N.
266 // Return the selected node on success, otherwise return null.
267 SDNode *tryRxSBG(SDNode *N, unsigned Opcode);
269 // If Op0 is null, then Node is a constant that can be loaded using:
271 // (Opcode UpperVal LowerVal)
273 // If Op0 is nonnull, then Node can be implemented using:
275 // (Opcode (Opcode Op0 UpperVal) LowerVal)
276 SDNode *splitLargeImmediate(unsigned Opcode, SDNode *Node, SDValue Op0,
277 uint64_t UpperVal, uint64_t LowerVal);
279 bool storeLoadCanUseMVC(SDNode *N) const;
282 SystemZDAGToDAGISel(SystemZTargetMachine &TM, CodeGenOpt::Level OptLevel)
283 : SelectionDAGISel(TM, OptLevel),
284 Lowering(*TM.getTargetLowering()),
285 Subtarget(*TM.getSubtargetImpl()) { }
287 // Override MachineFunctionPass.
288 virtual const char *getPassName() const LLVM_OVERRIDE {
289 return "SystemZ DAG->DAG Pattern Instruction Selection";
292 // Override SelectionDAGISel.
293 virtual SDNode *Select(SDNode *Node) LLVM_OVERRIDE;
294 virtual bool SelectInlineAsmMemoryOperand(const SDValue &Op,
296 std::vector<SDValue> &OutOps)
299 // Include the pieces autogenerated from the target description.
300 #include "SystemZGenDAGISel.inc"
302 } // end anonymous namespace
304 FunctionPass *llvm::createSystemZISelDag(SystemZTargetMachine &TM,
305 CodeGenOpt::Level OptLevel) {
306 return new SystemZDAGToDAGISel(TM, OptLevel);
309 // Return true if Val should be selected as a displacement for an address
310 // with range DR. Here we're interested in the range of both the instruction
311 // described by DR and of any pairing instruction.
312 static bool selectDisp(SystemZAddressingMode::DispRange DR, int64_t Val) {
314 case SystemZAddressingMode::Disp12Only:
315 return isUInt<12>(Val);
317 case SystemZAddressingMode::Disp12Pair:
318 case SystemZAddressingMode::Disp20Only:
319 case SystemZAddressingMode::Disp20Pair:
320 return isInt<20>(Val);
322 case SystemZAddressingMode::Disp20Only128:
323 return isInt<20>(Val) && isInt<20>(Val + 8);
325 llvm_unreachable("Unhandled displacement range");
328 // Change the base or index in AM to Value, where IsBase selects
329 // between the base and index.
330 static void changeComponent(SystemZAddressingMode &AM, bool IsBase,
338 // The base or index of AM is equivalent to Value + ADJDYNALLOC,
339 // where IsBase selects between the base and index. Try to fold the
340 // ADJDYNALLOC into AM.
341 static bool expandAdjDynAlloc(SystemZAddressingMode &AM, bool IsBase,
343 if (AM.isDynAlloc() && !AM.IncludesDynAlloc) {
344 changeComponent(AM, IsBase, Value);
345 AM.IncludesDynAlloc = true;
351 // The base of AM is equivalent to Base + Index. Try to use Index as
352 // the index register.
353 static bool expandIndex(SystemZAddressingMode &AM, SDValue Base,
355 if (AM.hasIndexField() && !AM.Index.getNode()) {
363 // The base or index of AM is equivalent to Op0 + Op1, where IsBase selects
364 // between the base and index. Try to fold Op1 into AM's displacement.
365 static bool expandDisp(SystemZAddressingMode &AM, bool IsBase,
366 SDValue Op0, ConstantSDNode *Op1) {
367 // First try adjusting the displacement.
368 int64_t TestDisp = AM.Disp + Op1->getSExtValue();
369 if (selectDisp(AM.DR, TestDisp)) {
370 changeComponent(AM, IsBase, Op0);
375 // We could consider forcing the displacement into a register and
376 // using it as an index, but it would need to be carefully tuned.
380 bool SystemZDAGToDAGISel::expandAddress(SystemZAddressingMode &AM,
382 SDValue N = IsBase ? AM.Base : AM.Index;
383 unsigned Opcode = N.getOpcode();
384 if (Opcode == ISD::TRUNCATE) {
386 Opcode = N.getOpcode();
388 if (Opcode == ISD::ADD || CurDAG->isBaseWithConstantOffset(N)) {
389 SDValue Op0 = N.getOperand(0);
390 SDValue Op1 = N.getOperand(1);
392 unsigned Op0Code = Op0->getOpcode();
393 unsigned Op1Code = Op1->getOpcode();
395 if (Op0Code == SystemZISD::ADJDYNALLOC)
396 return expandAdjDynAlloc(AM, IsBase, Op1);
397 if (Op1Code == SystemZISD::ADJDYNALLOC)
398 return expandAdjDynAlloc(AM, IsBase, Op0);
400 if (Op0Code == ISD::Constant)
401 return expandDisp(AM, IsBase, Op1, cast<ConstantSDNode>(Op0));
402 if (Op1Code == ISD::Constant)
403 return expandDisp(AM, IsBase, Op0, cast<ConstantSDNode>(Op1));
405 if (IsBase && expandIndex(AM, Op0, Op1))
411 // Return true if an instruction with displacement range DR should be
412 // used for displacement value Val. selectDisp(DR, Val) must already hold.
413 static bool isValidDisp(SystemZAddressingMode::DispRange DR, int64_t Val) {
414 assert(selectDisp(DR, Val) && "Invalid displacement");
416 case SystemZAddressingMode::Disp12Only:
417 case SystemZAddressingMode::Disp20Only:
418 case SystemZAddressingMode::Disp20Only128:
421 case SystemZAddressingMode::Disp12Pair:
422 // Use the other instruction if the displacement is too large.
423 return isUInt<12>(Val);
425 case SystemZAddressingMode::Disp20Pair:
426 // Use the other instruction if the displacement is small enough.
427 return !isUInt<12>(Val);
429 llvm_unreachable("Unhandled displacement range");
432 // Return true if Base + Disp + Index should be performed by LA(Y).
433 static bool shouldUseLA(SDNode *Base, int64_t Disp, SDNode *Index) {
434 // Don't use LA(Y) for constants.
438 // Always use LA(Y) for frame addresses, since we know that the destination
439 // register is almost always (perhaps always) going to be different from
440 // the frame register.
441 if (Base->getOpcode() == ISD::FrameIndex)
445 // Always use LA(Y) if there is a base, displacement and index.
449 // Always use LA if the displacement is small enough. It should always
450 // be no worse than AGHI (and better if it avoids a move).
451 if (isUInt<12>(Disp))
454 // For similar reasons, always use LAY if the constant is too big for AGHI.
455 // LAY should be no worse than AGFI.
456 if (!isInt<16>(Disp))
459 // Don't use LA for plain registers.
463 // Don't use LA for plain addition if the index operand is only used
464 // once. It should be a natural two-operand addition in that case.
465 if (Index->hasOneUse())
468 // Prefer addition if the second operation is sign-extended, in the
469 // hope of using AGF.
470 unsigned IndexOpcode = Index->getOpcode();
471 if (IndexOpcode == ISD::SIGN_EXTEND ||
472 IndexOpcode == ISD::SIGN_EXTEND_INREG)
476 // Don't use LA for two-operand addition if either operand is only
477 // used once. The addition instructions are better in that case.
478 if (Base->hasOneUse())
484 // Return true if Addr is suitable for AM, updating AM if so.
485 bool SystemZDAGToDAGISel::selectAddress(SDValue Addr,
486 SystemZAddressingMode &AM) {
487 // Start out assuming that the address will need to be loaded separately,
488 // then try to extend it as much as we can.
491 // First try treating the address as a constant.
492 if (Addr.getOpcode() == ISD::Constant &&
493 expandDisp(AM, true, SDValue(), cast<ConstantSDNode>(Addr)))
496 // Otherwise try expanding each component.
497 while (expandAddress(AM, true) ||
498 (AM.Index.getNode() && expandAddress(AM, false)))
501 // Reject cases where it isn't profitable to use LA(Y).
502 if (AM.Form == SystemZAddressingMode::FormBDXLA &&
503 !shouldUseLA(AM.Base.getNode(), AM.Disp, AM.Index.getNode()))
506 // Reject cases where the other instruction in a pair should be used.
507 if (!isValidDisp(AM.DR, AM.Disp))
510 // Make sure that ADJDYNALLOC is included where necessary.
511 if (AM.isDynAlloc() && !AM.IncludesDynAlloc)
518 // Insert a node into the DAG at least before Pos. This will reposition
519 // the node as needed, and will assign it a node ID that is <= Pos's ID.
520 // Note that this does *not* preserve the uniqueness of node IDs!
521 // The selection DAG must no longer depend on their uniqueness when this
523 static void insertDAGNode(SelectionDAG *DAG, SDNode *Pos, SDValue N) {
524 if (N.getNode()->getNodeId() == -1 ||
525 N.getNode()->getNodeId() > Pos->getNodeId()) {
526 DAG->RepositionNode(Pos, N.getNode());
527 N.getNode()->setNodeId(Pos->getNodeId());
531 void SystemZDAGToDAGISel::getAddressOperands(const SystemZAddressingMode &AM,
532 EVT VT, SDValue &Base,
536 // Register 0 means "no base". This is mostly useful for shifts.
537 Base = CurDAG->getRegister(0, VT);
538 else if (Base.getOpcode() == ISD::FrameIndex) {
539 // Lower a FrameIndex to a TargetFrameIndex.
540 int64_t FrameIndex = cast<FrameIndexSDNode>(Base)->getIndex();
541 Base = CurDAG->getTargetFrameIndex(FrameIndex, VT);
542 } else if (Base.getValueType() != VT) {
543 // Truncate values from i64 to i32, for shifts.
544 assert(VT == MVT::i32 && Base.getValueType() == MVT::i64 &&
545 "Unexpected truncation");
547 SDValue Trunc = CurDAG->getNode(ISD::TRUNCATE, DL, VT, Base);
548 insertDAGNode(CurDAG, Base.getNode(), Trunc);
552 // Lower the displacement to a TargetConstant.
553 Disp = CurDAG->getTargetConstant(AM.Disp, VT);
556 void SystemZDAGToDAGISel::getAddressOperands(const SystemZAddressingMode &AM,
557 EVT VT, SDValue &Base,
558 SDValue &Disp, SDValue &Index) {
559 getAddressOperands(AM, VT, Base, Disp);
562 if (!Index.getNode())
563 // Register 0 means "no index".
564 Index = CurDAG->getRegister(0, VT);
567 bool SystemZDAGToDAGISel::selectBDAddr(SystemZAddressingMode::DispRange DR,
568 SDValue Addr, SDValue &Base,
570 SystemZAddressingMode AM(SystemZAddressingMode::FormBD, DR);
571 if (!selectAddress(Addr, AM))
574 getAddressOperands(AM, Addr.getValueType(), Base, Disp);
578 bool SystemZDAGToDAGISel::selectBDXAddr(SystemZAddressingMode::AddrForm Form,
579 SystemZAddressingMode::DispRange DR,
580 SDValue Addr, SDValue &Base,
581 SDValue &Disp, SDValue &Index) {
582 SystemZAddressingMode AM(Form, DR);
583 if (!selectAddress(Addr, AM))
586 getAddressOperands(AM, Addr.getValueType(), Base, Disp, Index);
590 bool SystemZDAGToDAGISel::detectOrAndInsertion(SDValue &Op,
591 uint64_t InsertMask) {
592 // We're only interested in cases where the insertion is into some operand
593 // of Op, rather than into Op itself. The only useful case is an AND.
594 if (Op.getOpcode() != ISD::AND)
597 // We need a constant mask.
598 ConstantSDNode *MaskNode =
599 dyn_cast<ConstantSDNode>(Op.getOperand(1).getNode());
603 // It's not an insertion of Op.getOperand(0) if the two masks overlap.
604 uint64_t AndMask = MaskNode->getZExtValue();
605 if (InsertMask & AndMask)
608 // It's only an insertion if all bits are covered or are known to be zero.
609 // The inner check covers all cases but is more expensive.
610 uint64_t Used = allOnes(Op.getValueType().getSizeInBits());
611 if (Used != (AndMask | InsertMask)) {
612 APInt KnownZero, KnownOne;
613 CurDAG->ComputeMaskedBits(Op.getOperand(0), KnownZero, KnownOne);
614 if (Used != (AndMask | InsertMask | KnownZero.getZExtValue()))
618 Op = Op.getOperand(0);
622 bool SystemZDAGToDAGISel::refineRxSBGMask(RxSBGOperands &RxSBG, uint64_t Mask) {
623 const SystemZInstrInfo *TII = getInstrInfo();
624 if (RxSBG.Rotate != 0)
625 Mask = (Mask << RxSBG.Rotate) | (Mask >> (64 - RxSBG.Rotate));
627 if (TII->isRxSBGMask(Mask, RxSBG.BitSize, RxSBG.Start, RxSBG.End)) {
634 // RxSBG.Input is a shift of Count bits in the direction given by IsLeft.
635 // Return true if the result depends on the signs or zeros that are
637 static bool shiftedInBitsMatter(RxSBGOperands &RxSBG, uint64_t Count,
639 // Work out which bits of the shift result are zeros or sign copies.
640 uint64_t ShiftedIn = allOnes(Count);
642 ShiftedIn <<= RxSBG.BitSize - Count;
644 // Rotate that mask in the same way as RxSBG.Input is rotated.
645 if (RxSBG.Rotate != 0)
646 ShiftedIn = ((ShiftedIn << RxSBG.Rotate) |
647 (ShiftedIn >> (64 - RxSBG.Rotate)));
649 // Fail if any of the zero or sign bits are used.
650 return (ShiftedIn & RxSBG.Mask) != 0;
653 bool SystemZDAGToDAGISel::expandRxSBG(RxSBGOperands &RxSBG) {
654 SDValue N = RxSBG.Input;
655 unsigned Opcode = N.getOpcode();
658 if (RxSBG.Opcode == SystemZ::RNSBG)
661 ConstantSDNode *MaskNode =
662 dyn_cast<ConstantSDNode>(N.getOperand(1).getNode());
666 SDValue Input = N.getOperand(0);
667 uint64_t Mask = MaskNode->getZExtValue();
668 if (!refineRxSBGMask(RxSBG, Mask)) {
669 // If some bits of Input are already known zeros, those bits will have
670 // been removed from the mask. See if adding them back in makes the
672 APInt KnownZero, KnownOne;
673 CurDAG->ComputeMaskedBits(Input, KnownZero, KnownOne);
674 Mask |= KnownZero.getZExtValue();
675 if (!refineRxSBGMask(RxSBG, Mask))
683 if (RxSBG.Opcode != SystemZ::RNSBG)
686 ConstantSDNode *MaskNode =
687 dyn_cast<ConstantSDNode>(N.getOperand(1).getNode());
691 SDValue Input = N.getOperand(0);
692 uint64_t Mask = ~MaskNode->getZExtValue();
693 if (!refineRxSBGMask(RxSBG, Mask)) {
694 // If some bits of Input are already known ones, those bits will have
695 // been removed from the mask. See if adding them back in makes the
697 APInt KnownZero, KnownOne;
698 CurDAG->ComputeMaskedBits(Input, KnownZero, KnownOne);
699 Mask &= ~KnownOne.getZExtValue();
700 if (!refineRxSBGMask(RxSBG, Mask))
708 // Any 64-bit rotate left can be merged into the RxSBG.
709 if (RxSBG.BitSize != 64)
711 ConstantSDNode *CountNode
712 = dyn_cast<ConstantSDNode>(N.getOperand(1).getNode());
716 RxSBG.Rotate = (RxSBG.Rotate + CountNode->getZExtValue()) & 63;
717 RxSBG.Input = N.getOperand(0);
722 ConstantSDNode *CountNode =
723 dyn_cast<ConstantSDNode>(N.getOperand(1).getNode());
727 uint64_t Count = CountNode->getZExtValue();
728 if (Count < 1 || Count >= RxSBG.BitSize)
731 if (RxSBG.Opcode == SystemZ::RNSBG) {
732 // Treat (shl X, count) as (rotl X, size-count) as long as the bottom
733 // count bits from RxSBG.Input are ignored.
734 if (shiftedInBitsMatter(RxSBG, Count, true))
737 // Treat (shl X, count) as (and (rotl X, count), ~0<<count).
738 if (!refineRxSBGMask(RxSBG, allOnes(RxSBG.BitSize - Count) << Count))
742 RxSBG.Rotate = (RxSBG.Rotate + Count) & 63;
743 RxSBG.Input = N.getOperand(0);
749 ConstantSDNode *CountNode =
750 dyn_cast<ConstantSDNode>(N.getOperand(1).getNode());
754 uint64_t Count = CountNode->getZExtValue();
755 if (Count < 1 || Count >= RxSBG.BitSize)
758 if (RxSBG.Opcode == SystemZ::RNSBG || Opcode == ISD::SRA) {
759 // Treat (srl|sra X, count) as (rotl X, size-count) as long as the top
760 // count bits from RxSBG.Input are ignored.
761 if (shiftedInBitsMatter(RxSBG, Count, false))
764 // Treat (srl X, count), mask) as (and (rotl X, size-count), ~0>>count),
765 // which is similar to SLL above.
766 if (!refineRxSBGMask(RxSBG, allOnes(RxSBG.BitSize - Count)))
770 RxSBG.Rotate = (RxSBG.Rotate - Count) & 63;
771 RxSBG.Input = N.getOperand(0);
779 SDValue SystemZDAGToDAGISel::getUNDEF64(SDLoc DL) {
780 SDNode *N = CurDAG->getMachineNode(TargetOpcode::IMPLICIT_DEF, DL, MVT::i64);
781 return SDValue(N, 0);
784 SDValue SystemZDAGToDAGISel::convertTo(SDLoc DL, EVT VT, SDValue N) {
785 if (N.getValueType() == MVT::i32 && VT == MVT::i64) {
786 SDValue Index = CurDAG->getTargetConstant(SystemZ::subreg_32bit, MVT::i64);
787 SDNode *Insert = CurDAG->getMachineNode(TargetOpcode::INSERT_SUBREG,
788 DL, VT, getUNDEF64(DL), N, Index);
789 return SDValue(Insert, 0);
791 if (N.getValueType() == MVT::i64 && VT == MVT::i32) {
792 SDValue Index = CurDAG->getTargetConstant(SystemZ::subreg_32bit, MVT::i64);
793 SDNode *Extract = CurDAG->getMachineNode(TargetOpcode::EXTRACT_SUBREG,
795 return SDValue(Extract, 0);
797 assert(N.getValueType() == VT && "Unexpected value types");
801 SDNode *SystemZDAGToDAGISel::tryRISBGZero(SDNode *N) {
802 EVT VT = N->getValueType(0);
803 RxSBGOperands RISBG(SystemZ::RISBG, SDValue(N, 0));
805 while (expandRxSBG(RISBG))
810 // Prefer to use normal shift instructions over RISBG, since they can handle
811 // all cases and are sometimes shorter.
812 if (N->getOpcode() != ISD::AND)
815 // Prefer register extensions like LLC over RISBG. Also prefer to start
816 // out with normal ANDs if one instruction would be enough. We can convert
817 // these ANDs into an RISBG later if a three-address instruction is useful.
818 if (VT == MVT::i32 ||
819 RISBG.Mask == 0xff ||
820 RISBG.Mask == 0xffff ||
821 SystemZ::isImmLF(~RISBG.Mask) ||
822 SystemZ::isImmHF(~RISBG.Mask)) {
823 // Force the new mask into the DAG, since it may include known-one bits.
824 ConstantSDNode *MaskN = cast<ConstantSDNode>(N->getOperand(1).getNode());
825 if (MaskN->getZExtValue() != RISBG.Mask) {
826 SDValue NewMask = CurDAG->getConstant(RISBG.Mask, VT);
827 N = CurDAG->UpdateNodeOperands(N, N->getOperand(0), NewMask);
828 return SelectCode(N);
835 getUNDEF64(SDLoc(N)),
836 convertTo(SDLoc(N), MVT::i64, RISBG.Input),
837 CurDAG->getTargetConstant(RISBG.Start, MVT::i32),
838 CurDAG->getTargetConstant(RISBG.End | 128, MVT::i32),
839 CurDAG->getTargetConstant(RISBG.Rotate, MVT::i32)
841 N = CurDAG->getMachineNode(SystemZ::RISBG, SDLoc(N), MVT::i64, Ops);
842 return convertTo(SDLoc(N), VT, SDValue(N, 0)).getNode();
845 SDNode *SystemZDAGToDAGISel::tryRxSBG(SDNode *N, unsigned Opcode) {
846 // Try treating each operand of N as the second operand of the RxSBG
847 // and see which goes deepest.
848 RxSBGOperands RxSBG[] = {
849 RxSBGOperands(Opcode, N->getOperand(0)),
850 RxSBGOperands(Opcode, N->getOperand(1))
852 unsigned Count[] = { 0, 0 };
853 for (unsigned I = 0; I < 2; ++I)
854 while (expandRxSBG(RxSBG[I]))
857 // Do nothing if neither operand is suitable.
858 if (Count[0] == 0 && Count[1] == 0)
861 // Pick the deepest second operand.
862 unsigned I = Count[0] > Count[1] ? 0 : 1;
863 SDValue Op0 = N->getOperand(I ^ 1);
865 // Prefer IC for character insertions from memory.
866 if (Opcode == SystemZ::ROSBG && (RxSBG[I].Mask & 0xff) == 0)
867 if (LoadSDNode *Load = dyn_cast<LoadSDNode>(Op0.getNode()))
868 if (Load->getMemoryVT() == MVT::i8)
871 // See whether we can avoid an AND in the first operand by converting
873 if (Opcode == SystemZ::ROSBG && detectOrAndInsertion(Op0, RxSBG[I].Mask))
874 Opcode = SystemZ::RISBG;
876 EVT VT = N->getValueType(0);
878 convertTo(SDLoc(N), MVT::i64, Op0),
879 convertTo(SDLoc(N), MVT::i64, RxSBG[I].Input),
880 CurDAG->getTargetConstant(RxSBG[I].Start, MVT::i32),
881 CurDAG->getTargetConstant(RxSBG[I].End, MVT::i32),
882 CurDAG->getTargetConstant(RxSBG[I].Rotate, MVT::i32)
884 N = CurDAG->getMachineNode(Opcode, SDLoc(N), MVT::i64, Ops);
885 return convertTo(SDLoc(N), VT, SDValue(N, 0)).getNode();
888 SDNode *SystemZDAGToDAGISel::splitLargeImmediate(unsigned Opcode, SDNode *Node,
889 SDValue Op0, uint64_t UpperVal,
891 EVT VT = Node->getValueType(0);
893 SDValue Upper = CurDAG->getConstant(UpperVal, VT);
895 Upper = CurDAG->getNode(Opcode, DL, VT, Op0, Upper);
896 Upper = SDValue(Select(Upper.getNode()), 0);
898 SDValue Lower = CurDAG->getConstant(LowerVal, VT);
899 SDValue Or = CurDAG->getNode(Opcode, DL, VT, Upper, Lower);
903 // N is a (store (load ...), ...) pattern. Return true if it can use MVC.
904 bool SystemZDAGToDAGISel::storeLoadCanUseMVC(SDNode *N) const {
905 StoreSDNode *Store = cast<StoreSDNode>(N);
906 LoadSDNode *Load = cast<LoadSDNode>(Store->getValue().getNode());
908 // MVC is logically a bytewise copy, so can't be used for volatile accesses.
909 if (Load->isVolatile() || Store->isVolatile())
912 // Prefer not to use MVC if either address can use ... RELATIVE LONG
914 assert(Load->getMemoryVT() == Store->getMemoryVT() &&
915 "Should already have checked that the types match");
916 uint64_t Size = Load->getMemoryVT().getStoreSize();
917 if (Size > 1 && Size <= 8) {
918 // Prefer LHRL, LRL and LGRL.
919 if (Load->getBasePtr().getOpcode() == SystemZISD::PCREL_WRAPPER)
921 // Prefer STHRL, STRL and STGRL.
922 if (Store->getBasePtr().getOpcode() == SystemZISD::PCREL_WRAPPER)
926 // There's no chance of overlap if the load is invariant.
927 if (Load->isInvariant())
930 // If both operands are aligned, they must be equal or not overlap.
931 if (Load->getAlignment() >= Size && Store->getAlignment() >= Size)
934 // Otherwise we need to check whether there's an alias.
935 const Value *V1 = Load->getSrcValue();
936 const Value *V2 = Store->getSrcValue();
940 int64_t End1 = Load->getSrcValueOffset() + Size;
941 int64_t End2 = Store->getSrcValueOffset() + Size;
942 return !AA->alias(AliasAnalysis::Location(V1, End1, Load->getTBAAInfo()),
943 AliasAnalysis::Location(V2, End2, Store->getTBAAInfo()));
946 SDNode *SystemZDAGToDAGISel::Select(SDNode *Node) {
947 // Dump information about the Node being selected
948 DEBUG(errs() << "Selecting: "; Node->dump(CurDAG); errs() << "\n");
950 // If we have a custom node, we already have selected!
951 if (Node->isMachineOpcode()) {
952 DEBUG(errs() << "== "; Node->dump(CurDAG); errs() << "\n");
956 unsigned Opcode = Node->getOpcode();
960 if (Node->getOperand(1).getOpcode() != ISD::Constant)
961 ResNode = tryRxSBG(Node, SystemZ::ROSBG);
965 if (Node->getOperand(1).getOpcode() != ISD::Constant)
966 ResNode = tryRxSBG(Node, SystemZ::RXSBG);
969 // If this is a 64-bit operation in which both 32-bit halves are nonzero,
970 // split the operation into two.
971 if (!ResNode && Node->getValueType(0) == MVT::i64)
972 if (ConstantSDNode *Op1 = dyn_cast<ConstantSDNode>(Node->getOperand(1))) {
973 uint64_t Val = Op1->getZExtValue();
974 if (!SystemZ::isImmLF(Val) && !SystemZ::isImmHF(Val))
975 Node = splitLargeImmediate(Opcode, Node, Node->getOperand(0),
976 Val - uint32_t(Val), uint32_t(Val));
981 if (Node->getOperand(1).getOpcode() != ISD::Constant)
982 ResNode = tryRxSBG(Node, SystemZ::RNSBG);
988 ResNode = tryRISBGZero(Node);
992 // If this is a 64-bit constant that is out of the range of LLILF,
993 // LLIHF and LGFI, split it into two 32-bit pieces.
994 if (Node->getValueType(0) == MVT::i64) {
995 uint64_t Val = cast<ConstantSDNode>(Node)->getZExtValue();
996 if (!SystemZ::isImmLF(Val) && !SystemZ::isImmHF(Val) && !isInt<32>(Val))
997 Node = splitLargeImmediate(ISD::OR, Node, SDValue(),
998 Val - uint32_t(Val), uint32_t(Val));
1002 case ISD::ATOMIC_LOAD_SUB:
1003 // Try to convert subtractions of constants to additions.
1004 if (ConstantSDNode *Op2 = dyn_cast<ConstantSDNode>(Node->getOperand(2))) {
1005 uint64_t Value = -Op2->getZExtValue();
1006 EVT VT = Node->getValueType(0);
1007 if (VT == MVT::i32 || isInt<32>(Value)) {
1008 SDValue Ops[] = { Node->getOperand(0), Node->getOperand(1),
1009 CurDAG->getConstant(int32_t(Value), VT) };
1010 Node = CurDAG->MorphNodeTo(Node, ISD::ATOMIC_LOAD_ADD,
1011 Node->getVTList(), Ops, array_lengthof(Ops));
1017 // Select the default instruction
1019 ResNode = SelectCode(Node);
1021 DEBUG(errs() << "=> ";
1022 if (ResNode == NULL || ResNode == Node)
1025 ResNode->dump(CurDAG);
1031 bool SystemZDAGToDAGISel::
1032 SelectInlineAsmMemoryOperand(const SDValue &Op,
1033 char ConstraintCode,
1034 std::vector<SDValue> &OutOps) {
1035 assert(ConstraintCode == 'm' && "Unexpected constraint code");
1036 // Accept addresses with short displacements, which are compatible
1037 // with Q, R, S and T. But keep the index operand for future expansion.
1038 SDValue Base, Disp, Index;
1039 if (!selectBDXAddr(SystemZAddressingMode::FormBD,
1040 SystemZAddressingMode::Disp12Only,
1041 Op, Base, Disp, Index))
1043 OutOps.push_back(Base);
1044 OutOps.push_back(Disp);
1045 OutOps.push_back(Index);