1 //===-- SystemZMCCodeEmitter.cpp - Convert SystemZ code to machine code ---===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements the SystemZMCCodeEmitter class.
12 //===----------------------------------------------------------------------===//
14 #define DEBUG_TYPE "mccodeemitter"
15 #include "MCTargetDesc/SystemZMCTargetDesc.h"
16 #include "MCTargetDesc/SystemZMCFixups.h"
17 #include "llvm/MC/MCCodeEmitter.h"
18 #include "llvm/MC/MCContext.h"
19 #include "llvm/MC/MCExpr.h"
20 #include "llvm/MC/MCInstrInfo.h"
25 class SystemZMCCodeEmitter : public MCCodeEmitter {
26 const MCInstrInfo &MCII;
30 SystemZMCCodeEmitter(const MCInstrInfo &mcii, MCContext &ctx)
31 : MCII(mcii), Ctx(ctx) {
34 ~SystemZMCCodeEmitter() {}
36 // OVerride MCCodeEmitter.
37 virtual void EncodeInstruction(const MCInst &MI, raw_ostream &OS,
38 SmallVectorImpl<MCFixup> &Fixups,
39 const MCSubtargetInfo &STI) const
43 // Automatically generated by TableGen.
44 uint64_t getBinaryCodeForInstr(const MCInst &MI,
45 SmallVectorImpl<MCFixup> &Fixups) const;
47 // Called by the TableGen code to get the binary encoding of operand
48 // MO in MI. Fixups is the list of fixups against MI.
49 uint64_t getMachineOpValue(const MCInst &MI, const MCOperand &MO,
50 SmallVectorImpl<MCFixup> &Fixups) const;
52 // Called by the TableGen code to get the binary encoding of an address.
53 // The index or length, if any, is encoded first, followed by the base,
54 // followed by the displacement. In a 20-bit displacement,
55 // the low 12 bits are encoded before the high 8 bits.
56 uint64_t getBDAddr12Encoding(const MCInst &MI, unsigned OpNum,
57 SmallVectorImpl<MCFixup> &Fixups) const;
58 uint64_t getBDAddr20Encoding(const MCInst &MI, unsigned OpNum,
59 SmallVectorImpl<MCFixup> &Fixups) const;
60 uint64_t getBDXAddr12Encoding(const MCInst &MI, unsigned OpNum,
61 SmallVectorImpl<MCFixup> &Fixups) const;
62 uint64_t getBDXAddr20Encoding(const MCInst &MI, unsigned OpNum,
63 SmallVectorImpl<MCFixup> &Fixups) const;
64 uint64_t getBDLAddr12Len8Encoding(const MCInst &MI, unsigned OpNum,
65 SmallVectorImpl<MCFixup> &Fixups) const;
67 // Operand OpNum of MI needs a PC-relative fixup of kind Kind at
68 // Offset bytes from the start of MI. Add the fixup to Fixups
69 // and return the in-place addend, which since we're a RELA target
71 uint64_t getPCRelEncoding(const MCInst &MI, unsigned OpNum,
72 SmallVectorImpl<MCFixup> &Fixups,
73 unsigned Kind, int64_t Offset) const;
75 uint64_t getPC16DBLEncoding(const MCInst &MI, unsigned OpNum,
76 SmallVectorImpl<MCFixup> &Fixups) const {
77 return getPCRelEncoding(MI, OpNum, Fixups, SystemZ::FK_390_PC16DBL, 2);
79 uint64_t getPC32DBLEncoding(const MCInst &MI, unsigned OpNum,
80 SmallVectorImpl<MCFixup> &Fixups) const {
81 return getPCRelEncoding(MI, OpNum, Fixups, SystemZ::FK_390_PC32DBL, 2);
86 MCCodeEmitter *llvm::createSystemZMCCodeEmitter(const MCInstrInfo &MCII,
87 const MCRegisterInfo &MRI,
88 const MCSubtargetInfo &MCSTI,
90 return new SystemZMCCodeEmitter(MCII, Ctx);
93 void SystemZMCCodeEmitter::
94 EncodeInstruction(const MCInst &MI, raw_ostream &OS,
95 SmallVectorImpl<MCFixup> &Fixups,
96 const MCSubtargetInfo &STI) const {
97 uint64_t Bits = getBinaryCodeForInstr(MI, Fixups);
98 unsigned Size = MCII.get(MI.getOpcode()).getSize();
99 // Big-endian insertion of Size bytes.
100 unsigned ShiftValue = (Size * 8) - 8;
101 for (unsigned I = 0; I != Size; ++I) {
102 OS << uint8_t(Bits >> ShiftValue);
107 uint64_t SystemZMCCodeEmitter::
108 getMachineOpValue(const MCInst &MI, const MCOperand &MO,
109 SmallVectorImpl<MCFixup> &Fixups) const {
111 return Ctx.getRegisterInfo()->getEncodingValue(MO.getReg());
113 return static_cast<uint64_t>(MO.getImm());
114 llvm_unreachable("Unexpected operand type!");
117 uint64_t SystemZMCCodeEmitter::
118 getBDAddr12Encoding(const MCInst &MI, unsigned OpNum,
119 SmallVectorImpl<MCFixup> &Fixups) const {
120 uint64_t Base = getMachineOpValue(MI, MI.getOperand(OpNum), Fixups);
121 uint64_t Disp = getMachineOpValue(MI, MI.getOperand(OpNum + 1), Fixups);
122 assert(isUInt<4>(Base) && isUInt<12>(Disp));
123 return (Base << 12) | Disp;
126 uint64_t SystemZMCCodeEmitter::
127 getBDAddr20Encoding(const MCInst &MI, unsigned OpNum,
128 SmallVectorImpl<MCFixup> &Fixups) const {
129 uint64_t Base = getMachineOpValue(MI, MI.getOperand(OpNum), Fixups);
130 uint64_t Disp = getMachineOpValue(MI, MI.getOperand(OpNum + 1), Fixups);
131 assert(isUInt<4>(Base) && isInt<20>(Disp));
132 return (Base << 20) | ((Disp & 0xfff) << 8) | ((Disp & 0xff000) >> 12);
135 uint64_t SystemZMCCodeEmitter::
136 getBDXAddr12Encoding(const MCInst &MI, unsigned OpNum,
137 SmallVectorImpl<MCFixup> &Fixups) const {
138 uint64_t Base = getMachineOpValue(MI, MI.getOperand(OpNum), Fixups);
139 uint64_t Disp = getMachineOpValue(MI, MI.getOperand(OpNum + 1), Fixups);
140 uint64_t Index = getMachineOpValue(MI, MI.getOperand(OpNum + 2), Fixups);
141 assert(isUInt<4>(Base) && isUInt<12>(Disp) && isUInt<4>(Index));
142 return (Index << 16) | (Base << 12) | Disp;
145 uint64_t SystemZMCCodeEmitter::
146 getBDXAddr20Encoding(const MCInst &MI, unsigned OpNum,
147 SmallVectorImpl<MCFixup> &Fixups) const {
148 uint64_t Base = getMachineOpValue(MI, MI.getOperand(OpNum), Fixups);
149 uint64_t Disp = getMachineOpValue(MI, MI.getOperand(OpNum + 1), Fixups);
150 uint64_t Index = getMachineOpValue(MI, MI.getOperand(OpNum + 2), Fixups);
151 assert(isUInt<4>(Base) && isInt<20>(Disp) && isUInt<4>(Index));
152 return (Index << 24) | (Base << 20) | ((Disp & 0xfff) << 8)
153 | ((Disp & 0xff000) >> 12);
156 uint64_t SystemZMCCodeEmitter::
157 getBDLAddr12Len8Encoding(const MCInst &MI, unsigned OpNum,
158 SmallVectorImpl<MCFixup> &Fixups) const {
159 uint64_t Base = getMachineOpValue(MI, MI.getOperand(OpNum), Fixups);
160 uint64_t Disp = getMachineOpValue(MI, MI.getOperand(OpNum + 1), Fixups);
161 uint64_t Len = getMachineOpValue(MI, MI.getOperand(OpNum + 2), Fixups) - 1;
162 assert(isUInt<4>(Base) && isUInt<12>(Disp) && isUInt<8>(Len));
163 return (Len << 16) | (Base << 12) | Disp;
167 SystemZMCCodeEmitter::getPCRelEncoding(const MCInst &MI, unsigned OpNum,
168 SmallVectorImpl<MCFixup> &Fixups,
169 unsigned Kind, int64_t Offset) const {
170 const MCOperand &MO = MI.getOperand(OpNum);
173 Expr = MCConstantExpr::Create(MO.getImm() + Offset, Ctx);
177 // The operand value is relative to the start of MI, but the fixup
178 // is relative to the operand field itself, which is Offset bytes
179 // into MI. Add Offset to the relocation value to cancel out
181 const MCExpr *OffsetExpr = MCConstantExpr::Create(Offset, Ctx);
182 Expr = MCBinaryExpr::CreateAdd(Expr, OffsetExpr, Ctx);
185 Fixups.push_back(MCFixup::Create(Offset, Expr, (MCFixupKind)Kind));
189 #include "SystemZGenMCCodeEmitter.inc"