1 //===-- SystemZAsmParser.cpp - Parse SystemZ assembly instructions --------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 #include "MCTargetDesc/SystemZMCTargetDesc.h"
11 #include "llvm/ADT/STLExtras.h"
12 #include "llvm/MC/MCContext.h"
13 #include "llvm/MC/MCExpr.h"
14 #include "llvm/MC/MCInst.h"
15 #include "llvm/MC/MCParser/MCParsedAsmOperand.h"
16 #include "llvm/MC/MCStreamer.h"
17 #include "llvm/MC/MCSubtargetInfo.h"
18 #include "llvm/MC/MCTargetAsmParser.h"
19 #include "llvm/Support/TargetRegistry.h"
23 // Return true if Expr is in the range [MinValue, MaxValue].
24 static bool inRange(const MCExpr *Expr, int64_t MinValue, int64_t MaxValue) {
25 if (auto *CE = dyn_cast<MCConstantExpr>(Expr)) {
26 int64_t Value = CE->getValue();
27 return Value >= MinValue && Value <= MaxValue;
51 class SystemZOperand : public MCParsedAsmOperand {
64 SMLoc StartLoc, EndLoc;
66 // A string of length Length, starting at Data.
72 // LLVM register Num, which has kind Kind. In some ways it might be
73 // easier for this class to have a register bank (general, floating-point
74 // or access) and a raw register number (0-15). This would postpone the
75 // interpretation of the operand to the add*() methods and avoid the need
76 // for context-dependent parsing. However, we do things the current way
77 // because of the virtual getReg() method, which needs to distinguish
78 // between (say) %r0 used as a single register and %r0 used as a pair.
79 // Context-dependent parsing can also give us slightly better error
80 // messages when invalid pairs like %r1 are used.
86 // Base + Disp + Index, where Base and Index are LLVM registers or 0.
87 // RegKind says what type the registers have (ADDR32Reg or ADDR64Reg).
88 // Length is the operand length for D(L,B)-style operands, otherwise
107 void addExpr(MCInst &Inst, const MCExpr *Expr) const {
108 // Add as immediates when possible. Null MCExpr = 0.
110 Inst.addOperand(MCOperand::CreateImm(0));
111 else if (auto *CE = dyn_cast<MCConstantExpr>(Expr))
112 Inst.addOperand(MCOperand::CreateImm(CE->getValue()));
114 Inst.addOperand(MCOperand::CreateExpr(Expr));
118 SystemZOperand(OperandKind kind, SMLoc startLoc, SMLoc endLoc)
119 : Kind(kind), StartLoc(startLoc), EndLoc(endLoc) {}
121 // Create particular kinds of operand.
122 static std::unique_ptr<SystemZOperand> createInvalid(SMLoc StartLoc,
124 return make_unique<SystemZOperand>(KindInvalid, StartLoc, EndLoc);
126 static std::unique_ptr<SystemZOperand> createToken(StringRef Str, SMLoc Loc) {
127 auto Op = make_unique<SystemZOperand>(KindToken, Loc, Loc);
128 Op->Token.Data = Str.data();
129 Op->Token.Length = Str.size();
132 static std::unique_ptr<SystemZOperand>
133 createReg(RegisterKind Kind, unsigned Num, SMLoc StartLoc, SMLoc EndLoc) {
134 auto Op = make_unique<SystemZOperand>(KindReg, StartLoc, EndLoc);
139 static std::unique_ptr<SystemZOperand>
140 createAccessReg(unsigned Num, SMLoc StartLoc, SMLoc EndLoc) {
141 auto Op = make_unique<SystemZOperand>(KindAccessReg, StartLoc, EndLoc);
145 static std::unique_ptr<SystemZOperand>
146 createImm(const MCExpr *Expr, SMLoc StartLoc, SMLoc EndLoc) {
147 auto Op = make_unique<SystemZOperand>(KindImm, StartLoc, EndLoc);
151 static std::unique_ptr<SystemZOperand>
152 createMem(RegisterKind RegKind, unsigned Base, const MCExpr *Disp,
153 unsigned Index, const MCExpr *Length, SMLoc StartLoc,
155 auto Op = make_unique<SystemZOperand>(KindMem, StartLoc, EndLoc);
156 Op->Mem.RegKind = RegKind;
158 Op->Mem.Index = Index;
160 Op->Mem.Length = Length;
165 bool isToken() const override {
166 return Kind == KindToken;
168 StringRef getToken() const {
169 assert(Kind == KindToken && "Not a token");
170 return StringRef(Token.Data, Token.Length);
173 // Register operands.
174 bool isReg() const override {
175 return Kind == KindReg;
177 bool isReg(RegisterKind RegKind) const {
178 return Kind == KindReg && Reg.Kind == RegKind;
180 unsigned getReg() const override {
181 assert(Kind == KindReg && "Not a register");
185 // Access register operands. Access registers aren't exposed to LLVM
187 bool isAccessReg() const {
188 return Kind == KindAccessReg;
191 // Immediate operands.
192 bool isImm() const override {
193 return Kind == KindImm;
195 bool isImm(int64_t MinValue, int64_t MaxValue) const {
196 return Kind == KindImm && inRange(Imm, MinValue, MaxValue);
198 const MCExpr *getImm() const {
199 assert(Kind == KindImm && "Not an immediate");
204 bool isMem() const override {
205 return Kind == KindMem;
207 bool isMem(RegisterKind RegKind, MemoryKind MemKind) const {
208 return (Kind == KindMem &&
209 Mem.RegKind == RegKind &&
210 (MemKind == BDXMem || !Mem.Index) &&
211 (MemKind == BDLMem) == (Mem.Length != nullptr));
213 bool isMemDisp12(RegisterKind RegKind, MemoryKind MemKind) const {
214 return isMem(RegKind, MemKind) && inRange(Mem.Disp, 0, 0xfff);
216 bool isMemDisp20(RegisterKind RegKind, MemoryKind MemKind) const {
217 return isMem(RegKind, MemKind) && inRange(Mem.Disp, -524288, 524287);
219 bool isMemDisp12Len8(RegisterKind RegKind) const {
220 return isMemDisp12(RegKind, BDLMem) && inRange(Mem.Length, 1, 0x100);
223 // Override MCParsedAsmOperand.
224 SMLoc getStartLoc() const override { return StartLoc; }
225 SMLoc getEndLoc() const override { return EndLoc; }
226 void print(raw_ostream &OS) const override;
228 // Used by the TableGen code to add particular types of operand
229 // to an instruction.
230 void addRegOperands(MCInst &Inst, unsigned N) const {
231 assert(N == 1 && "Invalid number of operands");
232 Inst.addOperand(MCOperand::CreateReg(getReg()));
234 void addAccessRegOperands(MCInst &Inst, unsigned N) const {
235 assert(N == 1 && "Invalid number of operands");
236 assert(Kind == KindAccessReg && "Invalid operand type");
237 Inst.addOperand(MCOperand::CreateImm(AccessReg));
239 void addImmOperands(MCInst &Inst, unsigned N) const {
240 assert(N == 1 && "Invalid number of operands");
241 addExpr(Inst, getImm());
243 void addBDAddrOperands(MCInst &Inst, unsigned N) const {
244 assert(N == 2 && "Invalid number of operands");
245 assert(Kind == KindMem && Mem.Index == 0 && "Invalid operand type");
246 Inst.addOperand(MCOperand::CreateReg(Mem.Base));
247 addExpr(Inst, Mem.Disp);
249 void addBDXAddrOperands(MCInst &Inst, unsigned N) const {
250 assert(N == 3 && "Invalid number of operands");
251 assert(Kind == KindMem && "Invalid operand type");
252 Inst.addOperand(MCOperand::CreateReg(Mem.Base));
253 addExpr(Inst, Mem.Disp);
254 Inst.addOperand(MCOperand::CreateReg(Mem.Index));
256 void addBDLAddrOperands(MCInst &Inst, unsigned N) const {
257 assert(N == 3 && "Invalid number of operands");
258 assert(Kind == KindMem && "Invalid operand type");
259 Inst.addOperand(MCOperand::CreateReg(Mem.Base));
260 addExpr(Inst, Mem.Disp);
261 addExpr(Inst, Mem.Length);
264 // Used by the TableGen code to check for particular operand types.
265 bool isGR32() const { return isReg(GR32Reg); }
266 bool isGRH32() const { return isReg(GRH32Reg); }
267 bool isGRX32() const { return false; }
268 bool isGR64() const { return isReg(GR64Reg); }
269 bool isGR128() const { return isReg(GR128Reg); }
270 bool isADDR32() const { return isReg(ADDR32Reg); }
271 bool isADDR64() const { return isReg(ADDR64Reg); }
272 bool isADDR128() const { return false; }
273 bool isFP32() const { return isReg(FP32Reg); }
274 bool isFP64() const { return isReg(FP64Reg); }
275 bool isFP128() const { return isReg(FP128Reg); }
276 bool isBDAddr32Disp12() const { return isMemDisp12(ADDR32Reg, BDMem); }
277 bool isBDAddr32Disp20() const { return isMemDisp20(ADDR32Reg, BDMem); }
278 bool isBDAddr64Disp12() const { return isMemDisp12(ADDR64Reg, BDMem); }
279 bool isBDAddr64Disp20() const { return isMemDisp20(ADDR64Reg, BDMem); }
280 bool isBDXAddr64Disp12() const { return isMemDisp12(ADDR64Reg, BDXMem); }
281 bool isBDXAddr64Disp20() const { return isMemDisp20(ADDR64Reg, BDXMem); }
282 bool isBDLAddr64Disp12Len8() const { return isMemDisp12Len8(ADDR64Reg); }
283 bool isU4Imm() const { return isImm(0, 15); }
284 bool isU6Imm() const { return isImm(0, 63); }
285 bool isU8Imm() const { return isImm(0, 255); }
286 bool isS8Imm() const { return isImm(-128, 127); }
287 bool isU16Imm() const { return isImm(0, 65535); }
288 bool isS16Imm() const { return isImm(-32768, 32767); }
289 bool isU32Imm() const { return isImm(0, (1LL << 32) - 1); }
290 bool isS32Imm() const { return isImm(-(1LL << 31), (1LL << 31) - 1); }
293 class SystemZAsmParser : public MCTargetAsmParser {
294 #define GET_ASSEMBLER_HEADER
295 #include "SystemZGenAsmMatcher.inc"
298 MCSubtargetInfo &STI;
308 SMLoc StartLoc, EndLoc;
311 bool parseRegister(Register &Reg);
313 bool parseRegister(Register &Reg, RegisterGroup Group, const unsigned *Regs,
314 bool IsAddress = false);
316 OperandMatchResultTy parseRegister(OperandVector &Operands,
317 RegisterGroup Group, const unsigned *Regs,
320 bool parseAddress(unsigned &Base, const MCExpr *&Disp,
321 unsigned &Index, const MCExpr *&Length,
322 const unsigned *Regs, RegisterKind RegKind);
324 OperandMatchResultTy parseAddress(OperandVector &Operands,
325 const unsigned *Regs, RegisterKind RegKind,
328 bool parseOperand(OperandVector &Operands, StringRef Mnemonic);
331 SystemZAsmParser(MCSubtargetInfo &sti, MCAsmParser &parser,
332 const MCInstrInfo &MII,
333 const MCTargetOptions &Options)
334 : MCTargetAsmParser(), STI(sti), Parser(parser) {
335 MCAsmParserExtension::Initialize(Parser);
337 // Initialize the set of available features.
338 setAvailableFeatures(ComputeAvailableFeatures(STI.getFeatureBits()));
341 // Override MCTargetAsmParser.
342 bool ParseDirective(AsmToken DirectiveID) override;
343 bool ParseRegister(unsigned &RegNo, SMLoc &StartLoc, SMLoc &EndLoc) override;
344 bool ParseInstruction(ParseInstructionInfo &Info, StringRef Name,
345 SMLoc NameLoc, OperandVector &Operands) override;
346 bool MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
347 OperandVector &Operands, MCStreamer &Out,
349 bool MatchingInlineAsm) override;
351 // Used by the TableGen code to parse particular operand types.
352 OperandMatchResultTy parseGR32(OperandVector &Operands) {
353 return parseRegister(Operands, RegGR, SystemZMC::GR32Regs, GR32Reg);
355 OperandMatchResultTy parseGRH32(OperandVector &Operands) {
356 return parseRegister(Operands, RegGR, SystemZMC::GRH32Regs, GRH32Reg);
358 OperandMatchResultTy parseGRX32(OperandVector &Operands) {
359 llvm_unreachable("GRX32 should only be used for pseudo instructions");
361 OperandMatchResultTy parseGR64(OperandVector &Operands) {
362 return parseRegister(Operands, RegGR, SystemZMC::GR64Regs, GR64Reg);
364 OperandMatchResultTy parseGR128(OperandVector &Operands) {
365 return parseRegister(Operands, RegGR, SystemZMC::GR128Regs, GR128Reg);
367 OperandMatchResultTy parseADDR32(OperandVector &Operands) {
368 return parseRegister(Operands, RegGR, SystemZMC::GR32Regs, ADDR32Reg);
370 OperandMatchResultTy parseADDR64(OperandVector &Operands) {
371 return parseRegister(Operands, RegGR, SystemZMC::GR64Regs, ADDR64Reg);
373 OperandMatchResultTy parseADDR128(OperandVector &Operands) {
374 llvm_unreachable("Shouldn't be used as an operand");
376 OperandMatchResultTy parseFP32(OperandVector &Operands) {
377 return parseRegister(Operands, RegFP, SystemZMC::FP32Regs, FP32Reg);
379 OperandMatchResultTy parseFP64(OperandVector &Operands) {
380 return parseRegister(Operands, RegFP, SystemZMC::FP64Regs, FP64Reg);
382 OperandMatchResultTy parseFP128(OperandVector &Operands) {
383 return parseRegister(Operands, RegFP, SystemZMC::FP128Regs, FP128Reg);
385 OperandMatchResultTy parseBDAddr32(OperandVector &Operands) {
386 return parseAddress(Operands, SystemZMC::GR32Regs, ADDR32Reg, BDMem);
388 OperandMatchResultTy parseBDAddr64(OperandVector &Operands) {
389 return parseAddress(Operands, SystemZMC::GR64Regs, ADDR64Reg, BDMem);
391 OperandMatchResultTy parseBDXAddr64(OperandVector &Operands) {
392 return parseAddress(Operands, SystemZMC::GR64Regs, ADDR64Reg, BDXMem);
394 OperandMatchResultTy parseBDLAddr64(OperandVector &Operands) {
395 return parseAddress(Operands, SystemZMC::GR64Regs, ADDR64Reg, BDLMem);
397 OperandMatchResultTy parseAccessReg(OperandVector &Operands);
398 OperandMatchResultTy parsePCRel(OperandVector &Operands, int64_t MinVal,
400 OperandMatchResultTy parsePCRel16(OperandVector &Operands) {
401 return parsePCRel(Operands, -(1LL << 16), (1LL << 16) - 1);
403 OperandMatchResultTy parsePCRel32(OperandVector &Operands) {
404 return parsePCRel(Operands, -(1LL << 32), (1LL << 32) - 1);
407 } // end anonymous namespace
409 #define GET_REGISTER_MATCHER
410 #define GET_SUBTARGET_FEATURE_NAME
411 #define GET_MATCHER_IMPLEMENTATION
412 #include "SystemZGenAsmMatcher.inc"
414 void SystemZOperand::print(raw_ostream &OS) const {
415 llvm_unreachable("Not implemented");
418 // Parse one register of the form %<prefix><number>.
419 bool SystemZAsmParser::parseRegister(Register &Reg) {
420 Reg.StartLoc = Parser.getTok().getLoc();
423 if (Parser.getTok().isNot(AsmToken::Percent))
424 return Error(Parser.getTok().getLoc(), "register expected");
427 // Expect a register name.
428 if (Parser.getTok().isNot(AsmToken::Identifier))
429 return Error(Reg.StartLoc, "invalid register");
431 // Check that there's a prefix.
432 StringRef Name = Parser.getTok().getString();
434 return Error(Reg.StartLoc, "invalid register");
435 char Prefix = Name[0];
437 // Treat the rest of the register name as a register number.
438 if (Name.substr(1).getAsInteger(10, Reg.Num))
439 return Error(Reg.StartLoc, "invalid register");
441 // Look for valid combinations of prefix and number.
442 if (Prefix == 'r' && Reg.Num < 16)
444 else if (Prefix == 'f' && Reg.Num < 16)
446 else if (Prefix == 'a' && Reg.Num < 16)
447 Reg.Group = RegAccess;
449 return Error(Reg.StartLoc, "invalid register");
451 Reg.EndLoc = Parser.getTok().getLoc();
456 // Parse a register of group Group. If Regs is nonnull, use it to map
457 // the raw register number to LLVM numbering, with zero entries indicating
458 // an invalid register. IsAddress says whether the register appears in an
460 bool SystemZAsmParser::parseRegister(Register &Reg, RegisterGroup Group,
461 const unsigned *Regs, bool IsAddress) {
462 if (parseRegister(Reg))
464 if (Reg.Group != Group)
465 return Error(Reg.StartLoc, "invalid operand for instruction");
466 if (Regs && Regs[Reg.Num] == 0)
467 return Error(Reg.StartLoc, "invalid register pair");
468 if (Reg.Num == 0 && IsAddress)
469 return Error(Reg.StartLoc, "%r0 used in an address");
471 Reg.Num = Regs[Reg.Num];
475 // Parse a register and add it to Operands. The other arguments are as above.
476 SystemZAsmParser::OperandMatchResultTy
477 SystemZAsmParser::parseRegister(OperandVector &Operands, RegisterGroup Group,
478 const unsigned *Regs, RegisterKind Kind) {
479 if (Parser.getTok().isNot(AsmToken::Percent))
480 return MatchOperand_NoMatch;
483 bool IsAddress = (Kind == ADDR32Reg || Kind == ADDR64Reg);
484 if (parseRegister(Reg, Group, Regs, IsAddress))
485 return MatchOperand_ParseFail;
487 Operands.push_back(SystemZOperand::createReg(Kind, Reg.Num,
488 Reg.StartLoc, Reg.EndLoc));
489 return MatchOperand_Success;
492 // Parse a memory operand into Base, Disp, Index and Length.
493 // Regs maps asm register numbers to LLVM register numbers and RegKind
494 // says what kind of address register we're using (ADDR32Reg or ADDR64Reg).
495 bool SystemZAsmParser::parseAddress(unsigned &Base, const MCExpr *&Disp,
496 unsigned &Index, const MCExpr *&Length,
497 const unsigned *Regs,
498 RegisterKind RegKind) {
499 // Parse the displacement, which must always be present.
500 if (getParser().parseExpression(Disp))
503 // Parse the optional base and index.
507 if (getLexer().is(AsmToken::LParen)) {
510 if (getLexer().is(AsmToken::Percent)) {
511 // Parse the first register and decide whether it's a base or an index.
513 if (parseRegister(Reg, RegGR, Regs, RegKind))
515 if (getLexer().is(AsmToken::Comma))
521 if (getParser().parseExpression(Length))
525 // Check whether there's a second register. It's the base if so.
526 if (getLexer().is(AsmToken::Comma)) {
529 if (parseRegister(Reg, RegGR, Regs, RegKind))
534 // Consume the closing bracket.
535 if (getLexer().isNot(AsmToken::RParen))
536 return Error(Parser.getTok().getLoc(), "unexpected token in address");
542 // Parse a memory operand and add it to Operands. The other arguments
544 SystemZAsmParser::OperandMatchResultTy
545 SystemZAsmParser::parseAddress(OperandVector &Operands, const unsigned *Regs,
546 RegisterKind RegKind, MemoryKind MemKind) {
547 SMLoc StartLoc = Parser.getTok().getLoc();
548 unsigned Base, Index;
550 const MCExpr *Length;
551 if (parseAddress(Base, Disp, Index, Length, Regs, RegKind))
552 return MatchOperand_ParseFail;
554 if (Index && MemKind != BDXMem)
556 Error(StartLoc, "invalid use of indexed addressing");
557 return MatchOperand_ParseFail;
560 if (Length && MemKind != BDLMem)
562 Error(StartLoc, "invalid use of length addressing");
563 return MatchOperand_ParseFail;
566 if (!Length && MemKind == BDLMem)
568 Error(StartLoc, "missing length in address");
569 return MatchOperand_ParseFail;
573 SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
574 Operands.push_back(SystemZOperand::createMem(RegKind, Base, Disp, Index,
575 Length, StartLoc, EndLoc));
576 return MatchOperand_Success;
579 bool SystemZAsmParser::ParseDirective(AsmToken DirectiveID) {
583 bool SystemZAsmParser::ParseRegister(unsigned &RegNo, SMLoc &StartLoc,
586 if (parseRegister(Reg))
588 if (Reg.Group == RegGR)
589 RegNo = SystemZMC::GR64Regs[Reg.Num];
590 else if (Reg.Group == RegFP)
591 RegNo = SystemZMC::FP64Regs[Reg.Num];
593 // FIXME: Access registers aren't modelled as LLVM registers yet.
594 return Error(Reg.StartLoc, "invalid operand for instruction");
595 StartLoc = Reg.StartLoc;
600 bool SystemZAsmParser::ParseInstruction(ParseInstructionInfo &Info,
601 StringRef Name, SMLoc NameLoc,
602 OperandVector &Operands) {
603 Operands.push_back(SystemZOperand::createToken(Name, NameLoc));
605 // Read the remaining operands.
606 if (getLexer().isNot(AsmToken::EndOfStatement)) {
607 // Read the first operand.
608 if (parseOperand(Operands, Name)) {
609 Parser.eatToEndOfStatement();
613 // Read any subsequent operands.
614 while (getLexer().is(AsmToken::Comma)) {
616 if (parseOperand(Operands, Name)) {
617 Parser.eatToEndOfStatement();
621 if (getLexer().isNot(AsmToken::EndOfStatement)) {
622 SMLoc Loc = getLexer().getLoc();
623 Parser.eatToEndOfStatement();
624 return Error(Loc, "unexpected token in argument list");
628 // Consume the EndOfStatement.
633 bool SystemZAsmParser::parseOperand(OperandVector &Operands,
634 StringRef Mnemonic) {
635 // Check if the current operand has a custom associated parser, if so, try to
636 // custom parse the operand, or fallback to the general approach.
637 OperandMatchResultTy ResTy = MatchOperandParserImpl(Operands, Mnemonic);
638 if (ResTy == MatchOperand_Success)
641 // If there wasn't a custom match, try the generic matcher below. Otherwise,
642 // there was a match, but an error occurred, in which case, just return that
643 // the operand parsing failed.
644 if (ResTy == MatchOperand_ParseFail)
647 // Check for a register. All real register operands should have used
648 // a context-dependent parse routine, which gives the required register
649 // class. The code is here to mop up other cases, like those where
650 // the instruction isn't recognized.
651 if (Parser.getTok().is(AsmToken::Percent)) {
653 if (parseRegister(Reg))
655 Operands.push_back(SystemZOperand::createInvalid(Reg.StartLoc, Reg.EndLoc));
659 // The only other type of operand is an immediate or address. As above,
660 // real address operands should have used a context-dependent parse routine,
661 // so we treat any plain expression as an immediate.
662 SMLoc StartLoc = Parser.getTok().getLoc();
663 unsigned Base, Index;
664 const MCExpr *Expr, *Length;
665 if (parseAddress(Base, Expr, Index, Length, SystemZMC::GR64Regs, ADDR64Reg))
669 SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
670 if (Base || Index || Length)
671 Operands.push_back(SystemZOperand::createInvalid(StartLoc, EndLoc));
673 Operands.push_back(SystemZOperand::createImm(Expr, StartLoc, EndLoc));
677 bool SystemZAsmParser::MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
678 OperandVector &Operands,
681 bool MatchingInlineAsm) {
683 unsigned MatchResult;
685 MatchResult = MatchInstructionImpl(Operands, Inst, ErrorInfo,
687 switch (MatchResult) {
691 Out.EmitInstruction(Inst, STI);
694 case Match_MissingFeature: {
695 assert(ErrorInfo && "Unknown missing feature!");
696 // Special case the error message for the very common case where only
697 // a single subtarget feature is missing
698 std::string Msg = "instruction requires:";
700 for (unsigned I = 0; I < sizeof(ErrorInfo) * 8 - 1; ++I) {
701 if (ErrorInfo & Mask) {
703 Msg += getSubtargetFeatureName(ErrorInfo & Mask);
707 return Error(IDLoc, Msg);
710 case Match_InvalidOperand: {
711 SMLoc ErrorLoc = IDLoc;
712 if (ErrorInfo != ~0ULL) {
713 if (ErrorInfo >= Operands.size())
714 return Error(IDLoc, "too few operands for instruction");
716 ErrorLoc = ((SystemZOperand &)*Operands[ErrorInfo]).getStartLoc();
717 if (ErrorLoc == SMLoc())
720 return Error(ErrorLoc, "invalid operand for instruction");
723 case Match_MnemonicFail:
724 return Error(IDLoc, "invalid instruction");
727 llvm_unreachable("Unexpected match type");
730 SystemZAsmParser::OperandMatchResultTy
731 SystemZAsmParser::parseAccessReg(OperandVector &Operands) {
732 if (Parser.getTok().isNot(AsmToken::Percent))
733 return MatchOperand_NoMatch;
736 if (parseRegister(Reg, RegAccess, nullptr))
737 return MatchOperand_ParseFail;
739 Operands.push_back(SystemZOperand::createAccessReg(Reg.Num,
742 return MatchOperand_Success;
745 SystemZAsmParser::OperandMatchResultTy
746 SystemZAsmParser::parsePCRel(OperandVector &Operands, int64_t MinVal,
748 MCContext &Ctx = getContext();
749 MCStreamer &Out = getStreamer();
751 SMLoc StartLoc = Parser.getTok().getLoc();
752 if (getParser().parseExpression(Expr))
753 return MatchOperand_NoMatch;
755 // For consistency with the GNU assembler, treat immediates as offsets
757 if (auto *CE = dyn_cast<MCConstantExpr>(Expr)) {
758 int64_t Value = CE->getValue();
759 if ((Value & 1) || Value < MinVal || Value > MaxVal) {
760 Error(StartLoc, "offset out of range");
761 return MatchOperand_ParseFail;
763 MCSymbol *Sym = Ctx.CreateTempSymbol();
765 const MCExpr *Base = MCSymbolRefExpr::Create(Sym, MCSymbolRefExpr::VK_None,
767 Expr = Value == 0 ? Base : MCBinaryExpr::CreateAdd(Base, Expr, Ctx);
771 SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
772 Operands.push_back(SystemZOperand::createImm(Expr, StartLoc, EndLoc));
773 return MatchOperand_Success;
776 // Force static initialization.
777 extern "C" void LLVMInitializeSystemZAsmParser() {
778 RegisterMCAsmParser<SystemZAsmParser> X(TheSystemZTarget);