1 //===- SparcV9_Reg.td - Sparc V9 Register definitions ---------------------===//
3 //===----------------------------------------------------------------------===//
5 //===----------------------------------------------------------------------===//
6 // Declarations that describe the Sparc register file
7 //===----------------------------------------------------------------------===//
9 // Ri - One of the 32 64 bit integer registers
10 class Ri<bits<5> num> : Register {
11 field bits<5> Num = num; // Numbers are identified with a 5 bit ID
14 let Namespace = "SparcV9" in {
15 def G0 : Ri< 0>; def G1 : Ri< 1>; def G2 : Ri< 2>; def G3 : Ri< 3>;
16 def G4 : Ri< 4>; def G5 : Ri< 5>; def G6 : Ri< 6>; def G7 : Ri< 7>;
17 def O0 : Ri< 8>; def O1 : Ri< 9>; def O2 : Ri<10>; def O3 : Ri<11>;
18 def O4 : Ri<12>; def O5 : Ri<13>; def O6 : Ri<14>; def O7 : Ri<15>;
19 def L0 : Ri<16>; def L1 : Ri<17>; def L2 : Ri<18>; def L3 : Ri<19>;
20 def L4 : Ri<20>; def L5 : Ri<21>; def L6 : Ri<22>; def L7 : Ri<23>;
21 def I0 : Ri<24>; def I1 : Ri<25>; def I2 : Ri<26>; def I3 : Ri<27>;
22 def I4 : Ri<28>; def I5 : Ri<29>; def I6 : Ri<30>; def I7 : Ri<31>;
23 // Floating-point registers?
28 // For fun, specify a register class.
30 // FIXME: the register order should be defined in terms of the prefered
31 // allocation order...
33 def IntRegs : RegisterClass<i64, 8, [G0, G1, G2, G3, G4, G5, G6, G7,
34 O0, O1, O2, O3, O4, O5, O6, O7,
35 L0, L1, L2, L3, L4, L5, L6, L7,
36 I0, I1, I2, I3, I4, I5, I6, I7]>;