1 //===- SparcV9_F4.td - Format 4 instructions: Sparc V9 Target -------------===//
3 //===----------------------------------------------------------------------===//
5 //----------------------- F4 classes -----------------------------------------
7 // F4 - Common superclass of all F4 instructions. All instructions have an op3
11 let Inst{24-19} = op3;
14 // F4_rs1 - Common class of instructions that use an rs1 field
17 let Inst{18-14} = rs1;
20 // F4_rs1rs2 - Common class of instructions that have rs1 and rs2 fields
21 class F4_rs1rs2 : F4_rs1 {
26 // F4_rs1rs2rd - Common class of instructions that have 3 register operands
27 class F4_rs1rs2rd : F4_rs1rs2 {
32 // F4_rs1rs2rd - Common class of instructions that have 2 reg and 1 imm operand
33 class F4_rs1simm11rd : F4_rs1 {
37 let Inst{10-0} = simm11;
41 // F4_cc - Common class of instructions that have a cond field
44 let Inst{17-14} = cond;
47 // F4_cc - Common class of instructions that have cc register as first operand
48 class F4_condcc : F4_cond {
55 // Actual F4 instruction classes
57 class F4_1<bits<2> opVal, bits<6> op3Val, string name> : F4_rs1rs2rd {
63 let Inst{13} = 0; // i bit
65 let Inst{10-5} = 0; // don't care
68 class F4_2<bits<2> opVal, bits<6> op3Val, string name> : F4_rs1simm11rd {
74 let Inst{13} = 1; // i bit
78 class F4_3<bits<2> opVal, bits<6> op3Val, bits<4> condVal,
79 string name> : F4_condcc {
88 let Inst{13} = 0; // i bit
89 let Inst{10-5} = 0; // don't care
93 class F4_4<bits<2> opVal, bits<6> op3Val, bits<4> condVal,
94 string name> : F4_condcc {
102 let Inst{29-25} = rd;
103 let Inst{13} = 1; // i bit
104 let Inst{10-0} = simm11;
109 class F4_6<bits<2> opVal, bits<6> op3Val, bits<3> rcondVal,
110 bits<5> opf_lowVal, string name> : F4_rs1rs2rd {
115 let Inst{12-10} = rcondVal;
116 let Inst{9-5} = opf_lowVal;
119 class F4_7<bits<2> opVal, bits<6> op3Val, bits<4> condVal,
120 bits<6> opf_lowVal, string name> : F4_cond {
129 let Inst{29-25} = rd;
131 let Inst{13-11} = cc;
132 let Inst{10-5} = opf_lowVal;
136 // FIXME: F4 classes 8-9