1 //===- Sparc.td - Target Description for Sparc V9 Target --------*- C++ -*-===//
3 //===----------------------------------------------------------------------===//
5 //===----------------------------------------------------------------------===//
9 // F3 - Common superclass of all F3 instructions. All instructions have an op3
13 let op{1} = 1; // Op = 2 or 3
14 let Inst{24-19} = op3;
17 // F3_rs1 - Common class of instructions that have an rs1 field
20 let Inst{18-14} = rs1;
23 // F3_rs1rs2 - Common class of instructions that only have rs1 and rs2 fields
24 class F3_rs1rs2 : F3_rs1 {
29 // F3_rs1rs2 - Common class of instructions that only have rs1 and rs2 fields
30 class F3_rs1rs2rd : F3_rs1rs2 {
35 // F3_rs1simm13 - Common class of instructions that only have rs1 and simm13
36 class F3_rs1simm13 : F3_rs1 {
38 let Inst{12-0} = simm13;
41 class F3_rs1simm13rd : F3_rs1simm13 {
46 // F3_rs1rd - Common class of instructions that have an rs1 and rd fields
47 class F3_rs1rd : F3_rs1 {
52 // F3_rs2 - Common class of instructions that don't use an rs1
58 // F3_rs2rd - Common class of instructions that use rs2 and rd, but not rs1
59 class F3_rs2rd : F3_rs2 {
64 // F3_rd - Common class of instructions that have an rd field
70 // F3_rdrs1 - Common class of instructions that have rd and rs1 fields
71 class F3_rdrs1 : F3_rd {
73 let Inst{18-14} = rs1;
76 // F3_rdrs1simm13 - Common class of instructions that have rd, rs1, and simm13
77 class F3_rdrs1simm13 : F3_rdrs1 {
79 let Inst{12-0} = simm13;
82 // F3_rdrs1rs2 - Common class of instructions that have rd, rs1, and rs2 fields
83 class F3_rdrs1rs2 : F3_rdrs1 {
89 // Specific F3 classes...
92 class F3_1<bits<2> opVal, bits<6> op3val, string name> : F3_rs1rs2rd {
96 let Inst{13} = 0; // i field = 0
97 let Inst{12-5} = 0; // don't care
100 // The store instructions seem to like to see rd first, then rs1 and rs2
101 class F3_1rd<bits<2> opVal, bits<6> op3val, string name> : F3_rdrs1rs2 {
105 let Inst{13} = 0; // i field = 0
106 let Inst{12-5} = 0; // don't care
109 class F3_2<bits<2> opVal, bits<6> op3val, string name> : F3_rs1simm13rd {
113 let Inst{13} = 1; // i field = 1
116 // The store instructions seem to like to see rd first, then rs1 and imm
117 class F3_2rd<bits<2> opVal, bits<6> op3val, string name> : F3_rdrs1simm13 {
121 let Inst{13} = 1; // i field = 1
124 class F3_3<bits<2> opVal, bits<6> op3val, string name> : F3_rs1rs2 {
128 let Inst{29-25} = 0; // don't care
129 let Inst{13} = 0; // i field = 0
130 let Inst{12-5} = 0; // don't care
133 class F3_4<bits<2> opVal, bits<6> op3Val, string name> : F3_rs1simm13 {
137 let Inst{29-25} = 0; // don't care
138 let Inst{13} = 1; // i field = 1
139 let Inst{12-0} = simm13;
142 class F3_5<bits<2> opVal, bits<6> op3Val, bits<3> rcondVal,
143 string name> : F3_rs1rs2rd {
147 let Inst{13} = 0; // i field = 0
148 let Inst{12-10} = rcondVal; // rcond field
149 let Inst{9-5} = 0; // don't care
152 class F3_6<bits<2> opVal, bits<6> op3Val, bits<3> rcondVal,
153 string name> : F3_rs1 {
160 let Inst{29-25} = rd;
161 let Inst{13} = 1; // i field = 1
162 let Inst{12-10} = rcondVal; // rcond field
163 let Inst{9-0} = simm10;
166 //FIXME: classes 7-10 not defined!!
168 class F3_11<bits<2> opVal, bits<6> op3Val, string name> : F3_rs1rs2rd {
173 let Inst{13} = 0; // i field = 0
175 let Inst{11-5} = 0; // don't care
178 class F3_12<bits<2> opVal, bits<6> op3Val, string name> : F3_rs1 {
185 let Inst{29-25} = rd;
186 let Inst{13} = 1; // i field = 1
187 let Inst{12} = 0; // x field = 0
188 let Inst{11-5} = 0; // don't care
189 let Inst{4-0} = shcnt;
192 class F3_13<bits<2> opVal, bits<6> op3Val, string name> : F3_rs1 {
199 let Inst{29-25} = rd;
200 let Inst{13} = 1; // i field = 1
201 let Inst{12} = 1; // x field = 1
202 let Inst{11-6} = 0; // don't care
203 let Inst{5-0} = shcnt;
206 class F3_14<bits<2> opVal, bits<6> op3Val,
207 bits<9> opfVal, string name> : F3_rs2rd {
211 let Inst{18-14} = 0; // don't care
212 let Inst{13-5} = opfVal;
215 class F3_15<bits<2> opVal, bits<6> op3Val,
216 bits<9> opfVal, string name> : F3 {
224 let Inst{29-27} = 0; // defined to be zero
225 let Inst{26-25} = cc;
226 let Inst{18-14} = rs1;
227 let Inst{13-5} = opfVal;
231 class F3_16<bits<2> opVal, bits<6> op3Val,
232 bits<9> opfval, string name> : F3_rs1rs2rd {
236 let Inst{13-5} = opfval;
239 class F3_17<bits<2> opVal, bits<6> op3Val, string name> : F3_rs1rd {
243 let Inst{13-0} = 0; // don't care
246 class F3_18<bits<5> fcn, string name> : F3 {
250 let Inst{29-25} = fcn;
251 let Inst{18-0 } = 0; // don't care;
254 class F3_19<bits<2> opVal, bits<6> op3Val, string name> : F3_rd {
258 let Inst{18-0} = 0; // don't care
261 // FIXME: class F3_20
262 // FIXME: class F3_21