1 #include "llvm/Target/Sparc.h"
2 #include "SparcInternals.h"
3 #include "llvm/Method.h"
4 #include "llvm/iTerminators.h"
5 #include "llvm/iOther.h"
6 #include "llvm/CodeGen/InstrScheduling.h"
7 #include "llvm/CodeGen/InstrSelection.h"
8 #include "llvm/Analysis/LiveVar/MethodLiveVarInfo.h"
9 #include "llvm/CodeGen/PhyRegAlloc.h"
10 #include "llvm/DerivedTypes.h"
12 //---------------------------------------------------------------------------
14 // This file contains implementation of Sparc specific helper methods
15 // used for register allocation.
16 //---------------------------------------------------------------------------
19 //---------------------------------------------------------------------------
20 // Finds the return value of a sparc specific call instruction
21 //---------------------------------------------------------------------------
23 UltraSparcRegInfo::getCallInstRetVal(const MachineInstr *CallMI) const {
25 unsigned OpCode = CallMI->getOpCode();
26 unsigned NumOfImpRefs = CallMI->getNumImplicitRefs();
28 if( OpCode == CALL ) {
30 // The one before the last implicit operand is the return value of
33 if( NumOfImpRefs > 1 )
34 if( CallMI->implicitRefIsDefined(NumOfImpRefs-2) )
35 return CallMI->getImplicitRef(NumOfImpRefs-2);
38 else if( OpCode == JMPLCALL) {
40 // The last implicit operand is the return value of a JMPL
42 if( NumOfImpRefs > 0 )
43 if( CallMI->implicitRefIsDefined(NumOfImpRefs-1) )
44 return CallMI->getImplicitRef(NumOfImpRefs-1);
47 assert(0 && "OpCode must be CALL/JMPL for a call instr");
54 //---------------------------------------------------------------------------
55 // Finds the return address of a call sparc specific call instruction
56 //---------------------------------------------------------------------------
58 UltraSparcRegInfo::getCallInstRetAddr(const MachineInstr *CallMI)const {
60 unsigned OpCode = CallMI->getOpCode();
64 unsigned NumOfImpRefs = CallMI->getNumImplicitRefs();
66 assert( NumOfImpRefs && "CALL instr must have at least on ImpRef");
68 // The last implicit operand is the return address of a CALL instr
70 return CallMI->getImplicitRef(NumOfImpRefs-1);
73 else if( OpCode == JMPLCALL ) {
75 MachineOperand & MO = ( MachineOperand &) CallMI->getOperand(2);
76 return MO.getVRegValue();
80 assert(0 && "OpCode must be CALL/JMPL for a call instr");
82 assert(0 && "There must be a return addr for a call instr");
89 //---------------------------------------------------------------------------
90 // Finds the # of actual arguments of the call instruction
91 //---------------------------------------------------------------------------
93 UltraSparcRegInfo::getCallInstNumArgs(const MachineInstr *CallMI) const {
95 unsigned OpCode = CallMI->getOpCode();
96 unsigned NumOfImpRefs = CallMI->getNumImplicitRefs();
99 if( OpCode == CALL ) {
101 switch( NumOfImpRefs ) {
103 case 0: assert(0 && "A CALL inst must have at least one ImpRef (RetAddr)");
108 default: // two or more implicit refs
109 if( CallMI->implicitRefIsDefined(NumOfImpRefs-2) )
110 NumArgs = NumOfImpRefs - 2; // i.e., NumOfImpRef-2 is the ret val
112 NumArgs = NumOfImpRefs - 1;
116 else if( OpCode == JMPLCALL ) {
118 // The last implicit operand is the return value of a JMPL instr
119 if( NumOfImpRefs > 0 ) {
120 if( CallMI->implicitRefIsDefined(NumOfImpRefs-1) )
121 NumArgs = NumOfImpRefs - 1; // i.e., NumOfImpRef-1 is the ret val
123 NumArgs = NumOfImpRefs;
126 NumArgs = NumOfImpRefs;
129 assert(0 && "OpCode must be CALL/JMPL for a call instr");
131 assert( (NumArgs != -1) && "Internal error in getCallInstNumArgs" );
132 return (unsigned) NumArgs;
137 //---------------------------------------------------------------------------
138 // Finds whether a call is an indirect call
139 //---------------------------------------------------------------------------
140 bool UltraSparcRegInfo::isVarArgCall(const MachineInstr *CallMI) const {
142 assert ( (UltraSparcInfo->getInstrInfo()).isCall(CallMI->getOpCode()) );
144 const MachineOperand & calleeOp = CallMI->getOperand(0);
145 Value *calleeVal = calleeOp.getVRegValue();
147 PointerType *PT = cast<PointerType> (calleeVal->getType());
148 MethodType *MT = cast<MethodType>(PT->getElementType());
150 return MT->isVarArg();
156 //---------------------------------------------------------------------------
157 // Suggests a register for the ret address in the RET machine instruction.
158 // We always suggest %i7 by convention.
159 //---------------------------------------------------------------------------
160 void UltraSparcRegInfo::suggestReg4RetAddr(const MachineInstr * RetMI,
161 LiveRangeInfo& LRI) const {
163 assert( (RetMI->getNumOperands() >= 2)
164 && "JMPL/RETURN must have 3 and 2 operands respectively");
166 MachineOperand & MO = ( MachineOperand &) RetMI->getOperand(0);
168 // return address is always mapped to i7
170 MO.setRegForValue( getUnifiedRegNum( IntRegClassID, SparcIntRegOrder::i7) );
172 // Possible Optimization:
173 // Instead of setting the color, we can suggest one. In that case,
174 // we have to test later whether it received the suggested color.
175 // In that case, a LR has to be created at the start of method.
176 // It has to be done as follows (remove the setRegVal above):
178 // const Value *RetAddrVal = MO.getVRegValue();
179 // assert( RetAddrVal && "LR for ret address must be created at start");
180 // LiveRange * RetAddrLR = LRI.getLiveRangeForValue( RetAddrVal);
181 // RetAddrLR->setSuggestedColor(getUnifiedRegNum( IntRegClassID,
182 // SparcIntRegOrdr::i7) );
186 //---------------------------------------------------------------------------
187 // Suggests a register for the ret address in the JMPL/CALL machine instr.
188 // Sparc ABI dictates that %o7 be used for this purpose.
189 //---------------------------------------------------------------------------
190 void UltraSparcRegInfo::suggestReg4CallAddr(const MachineInstr * CallMI,
192 vector<RegClass *> RCList) const {
195 const Value *RetAddrVal = getCallInstRetAddr( CallMI );
197 // RetAddrVal cannot be NULL (asserted in getCallInstRetAddr)
198 // create a new LR for the return address and color it
200 LiveRange * RetAddrLR = new LiveRange();
201 RetAddrLR->add( RetAddrVal );
202 unsigned RegClassID = getRegClassIDOfValue( RetAddrVal );
203 RetAddrLR->setRegClass( RCList[RegClassID] );
204 RetAddrLR->setColor(getUnifiedRegNum(IntRegClassID,SparcIntRegOrder::o7));
205 LRI.addLRToMap( RetAddrVal, RetAddrLR);
212 //---------------------------------------------------------------------------
213 // This method will suggest colors to incoming args to a method.
214 // According to the Sparc ABI, the first 6 incoming args are in
215 // %i0 - %i5 (if they are integer) OR in %f0 - %f31 (if they are float).
216 // If the arg is passed on stack due to the lack of regs, NOTHING will be
217 // done - it will be colored (or spilled) as a normal live range.
218 //---------------------------------------------------------------------------
219 void UltraSparcRegInfo::suggestRegs4MethodArgs(const Method *const Meth,
220 LiveRangeInfo& LRI) const
223 // get the argument list
224 const Method::ArgumentListType& ArgList = Meth->getArgumentList();
225 // get an iterator to arg list
226 Method::ArgumentListType::const_iterator ArgIt = ArgList.begin();
229 for( unsigned argNo=0; ArgIt != ArgList.end() ; ++ArgIt, ++argNo) {
232 LiveRange *const LR = LRI.getLiveRangeForValue((const Value *) *ArgIt);
233 assert( LR && "No live range found for method arg");
235 unsigned RegType = getRegType( LR );
238 // if the arg is in int class - allocate a reg for an int arg
240 if( RegType == IntRegType ) {
242 if( argNo < NumOfIntArgRegs) {
243 LR->setSuggestedColor( SparcIntRegOrder::i0 + argNo );
246 // Do NOTHING as this will be colored as a normal value.
247 if (DEBUG_RA) cerr << " Int Regr not suggested for method arg\n";
251 else if( RegType==FPSingleRegType && (argNo*2+1) < NumOfFloatArgRegs)
252 LR->setSuggestedColor( SparcFloatRegOrder::f0 + (argNo * 2 + 1) );
255 else if( RegType == FPDoubleRegType && (argNo*2) < NumOfFloatArgRegs)
256 LR->setSuggestedColor( SparcFloatRegOrder::f0 + (argNo * 2) );
263 //---------------------------------------------------------------------------
264 // This method is called after graph coloring to move incoming args to
265 // the correct hardware registers if they did not receive the correct
266 // (suggested) color through graph coloring.
267 //---------------------------------------------------------------------------
268 void UltraSparcRegInfo::colorMethodArgs(const Method *const Meth,
270 AddedInstrns *const FirstAI) const {
272 // get the argument list
273 const Method::ArgumentListType& ArgList = Meth->getArgumentList();
274 // get an iterator to arg list
275 Method::ArgumentListType::const_iterator ArgIt = ArgList.begin();
281 for( unsigned argNo=0; ArgIt != ArgList.end() ; ++ArgIt, ++argNo) {
284 LiveRange *const LR = LRI.getLiveRangeForValue((const Value *) *ArgIt);
285 assert( LR && "No live range found for method arg");
288 unsigned RegType = getRegType( LR );
289 unsigned RegClassID = (LR->getRegClass())->getID();
291 // Find whether this argument is coming in a register (if not, on stack)
292 // Also find the correct register that the argument must go (UniArgReg)
294 bool isArgInReg = false;
295 unsigned UniArgReg = InvalidRegNum; // reg that LR MUST be colored with
297 if( (RegType== IntRegType && argNo < NumOfIntArgRegs)) {
299 UniArgReg = getUnifiedRegNum( RegClassID, SparcIntRegOrder::i0 + argNo );
301 else if(RegType == FPSingleRegType && argNo < NumOfFloatArgRegs) {
303 UniArgReg = getUnifiedRegNum( RegClassID,
304 SparcFloatRegOrder::f0 + argNo*2 + 1 ) ;
306 else if(RegType == FPDoubleRegType && argNo < NumOfFloatArgRegs) {
308 UniArgReg = getUnifiedRegNum(RegClassID, SparcFloatRegOrder::f0+argNo*2);
312 if( LR->hasColor() ) { // if this arg received a register
314 unsigned UniLRReg = getUnifiedRegNum( RegClassID, LR->getColor() );
316 // if LR received the correct color, nothing to do
318 if( UniLRReg == UniArgReg )
321 // We are here because the LR did not receive the suggested
322 // but LR received another register.
323 // Now we have to copy the %i reg (or stack pos of arg)
324 // to the register the LR was colored with.
326 // if the arg is coming in UniArgReg register, it MUST go into
327 // the UniLRReg register
330 AdMI = cpReg2RegMI( UniArgReg, UniLRReg, RegType );
334 // Now the arg is coming on stack. Since the LR recieved a register,
335 // we just have to load the arg on stack into that register
337 const MachineFrameInfo& frameInfo = target.getFrameInfo();
338 assert(frameInfo.argsOnStackHaveFixedSize());
340 bool growUp; // find the offset of arg in stack frame
342 frameInfo.getFirstIncomingArgOffset(MachineCodeForMethod::get(Meth),
345 growUp? firstArg + argNo * frameInfo.getSizeOfEachArgOnStack()
346 : firstArg - argNo * frameInfo.getSizeOfEachArgOnStack();
348 AdMI = cpMem2RegMI(getFramePointer(), offsetFromFP,
352 FirstAI->InstrnsBefore.push_back( AdMI );
354 } // if LR received a color
358 // Now, the LR did not receive a color. But it has a stack offset for
360 // So, if the arg is coming in UniArgReg register, we can just move
361 // that on to the stack pos of LR
365 MachineInstr *AdIBef =
366 cpReg2MemMI(UniArgReg, getFramePointer(),
367 LR->getSpillOffFromFP(), RegType );
369 FirstAI->InstrnsBefore.push_back( AdMI );
374 // Now the arg is coming on stack. Since the LR did NOT
375 // recieved a register as well, it is allocated a stack position. We
376 // can simply change the stack poistion of the LR. We can do this,
377 // since this method is called before any other method that makes
378 // uses of the stack pos of the LR (e.g., updateMachineInstr)
380 const MachineFrameInfo& frameInfo = target.getFrameInfo();
381 assert(frameInfo.argsOnStackHaveFixedSize());
384 int firstArg = frameInfo.getFirstIncomingArgOffset(MachineCodeForMethod::get(Meth), growUp);
386 growUp? firstArg + argNo * frameInfo.getSizeOfEachArgOnStack()
387 : firstArg - argNo * frameInfo.getSizeOfEachArgOnStack();
389 LR->modifySpillOffFromFP( offsetFromFP );
394 } // for each incoming argument
401 //---------------------------------------------------------------------------
402 // This method is called before graph coloring to suggest colors to the
403 // outgoing call args and the return value of the call.
404 //---------------------------------------------------------------------------
405 void UltraSparcRegInfo::suggestRegs4CallArgs(const MachineInstr *const CallMI,
407 vector<RegClass *> RCList) const {
409 assert ( (UltraSparcInfo->getInstrInfo()).isCall(CallMI->getOpCode()) );
411 suggestReg4CallAddr(CallMI, LRI, RCList);
414 // First color the return value of the call instruction. The return value
415 // will be in %o0 if the value is an integer type, or in %f0 if the
416 // value is a float type.
418 // the return value cannot have a LR in machine instruction since it is
419 // only defined by the call instruction
421 // if type is not void, create a new live range and set its
422 // register class and add to LRI
425 const Value *RetVal = getCallInstRetVal( CallMI );
430 assert( (! LRI.getLiveRangeForValue( RetVal ) ) &&
431 "LR for ret Value of call already definded!");
434 // create a new LR for the return value
436 LiveRange * RetValLR = new LiveRange();
437 RetValLR->add( RetVal );
438 unsigned RegClassID = getRegClassIDOfValue( RetVal );
439 RetValLR->setRegClass( RCList[RegClassID] );
440 LRI.addLRToMap( RetVal, RetValLR);
442 // now suggest a register depending on the register class of ret arg
444 if( RegClassID == IntRegClassID )
445 RetValLR->setSuggestedColor(SparcIntRegOrder::o0);
446 else if (RegClassID == FloatRegClassID )
447 RetValLR->setSuggestedColor(SparcFloatRegOrder::f0 );
448 else assert( 0 && "Unknown reg class for return value of call\n");
453 // Now suggest colors for arguments (operands) of the call instruction.
454 // Colors are suggested only if the arg number is smaller than the
455 // the number of registers allocated for argument passing.
456 // Now, go thru call args - implicit operands of the call MI
458 unsigned NumOfCallArgs = getCallInstNumArgs( CallMI );
460 for(unsigned argNo=0, i=0; i < NumOfCallArgs; ++i, ++argNo ) {
462 const Value *CallArg = CallMI->getImplicitRef(i);
464 // get the LR of call operand (parameter)
465 LiveRange *const LR = LRI.getLiveRangeForValue(CallArg);
467 // not possible to have a null LR since all args (even consts)
468 // must be defined before
471 cerr << " ERROR: In call instr, no LR for arg: " ;
472 printValue(CallArg); cerr << endl;
474 assert(0 && "NO LR for call arg");
478 unsigned RegType = getRegType( LR );
480 // if the arg is in int class - allocate a reg for an int arg
481 if( RegType == IntRegType ) {
483 if( argNo < NumOfIntArgRegs)
484 LR->setSuggestedColor( SparcIntRegOrder::o0 + argNo );
487 // Do NOTHING as this will be colored as a normal value.
488 cerr << " Regr not suggested for int call arg" << endl;
491 else if( RegType == FPSingleRegType && (argNo*2 +1)< NumOfFloatArgRegs)
492 LR->setSuggestedColor( SparcFloatRegOrder::f0 + (argNo * 2 + 1) );
495 else if( RegType == FPDoubleRegType && (argNo*2) < NumOfFloatArgRegs)
496 LR->setSuggestedColor( SparcFloatRegOrder::f0 + (argNo * 2) );
499 } // for all call arguments
504 //---------------------------------------------------------------------------
505 // After graph coloring, we have call this method to see whehter the return
506 // value and the call args received the correct colors. If not, we have
507 // to instert copy instructions.
508 //---------------------------------------------------------------------------
510 void UltraSparcRegInfo::colorCallArgs(const MachineInstr *const CallMI,
512 AddedInstrns *const CallAI,
514 const BasicBlock *BB) const {
516 assert ( (UltraSparcInfo->getInstrInfo()).isCall(CallMI->getOpCode()) );
518 // Reset the optional args area in the stack frame
519 // since that is reused for each call
521 PRA.mcInfo.resetOptionalArgs(target);
523 // First color the return value of the call.
524 // If there is a LR for the return value, it means this
525 // method returns a value
529 const Value *RetVal = getCallInstRetVal( CallMI );
533 LiveRange * RetValLR = LRI.getLiveRangeForValue( RetVal );
536 cerr << "\nNo LR for:";
537 printValue( RetVal );
539 assert( RetValLR && "ERR:No LR for non-void return value");
543 unsigned RegClassID = (RetValLR->getRegClass())->getID();
544 bool recvCorrectColor = false;
546 unsigned CorrectCol; // correct color for ret value
547 if(RegClassID == IntRegClassID)
548 CorrectCol = SparcIntRegOrder::o0;
549 else if(RegClassID == FloatRegClassID)
550 CorrectCol = SparcFloatRegOrder::f0;
552 assert( 0 && "Unknown RegClass");
556 // if the LR received the correct color, NOTHING to do
558 if( RetValLR->hasColor() )
559 if( RetValLR->getColor() == CorrectCol )
560 recvCorrectColor = true;
563 // if we didn't receive the correct color for some reason,
564 // put copy instruction
566 if( !recvCorrectColor ) {
568 unsigned RegType = getRegType( RetValLR );
570 // the reg that LR must be colored with
571 unsigned UniRetReg = getUnifiedRegNum( RegClassID, CorrectCol);
573 if( RetValLR->hasColor() ) {
576 UniRetLRReg=getUnifiedRegNum(RegClassID,RetValLR->getColor());
578 // the return value is coming in UniRetReg but has to go into
581 AdMI = cpReg2RegMI( UniRetReg, UniRetLRReg, RegType );
586 // if the LR did NOT receive a color, we have to move the return
587 // value coming in UniRetReg to the stack pos of spilled LR
589 AdMI = cpReg2MemMI(UniRetReg, getFramePointer(),
590 RetValLR->getSpillOffFromFP(), RegType );
593 CallAI->InstrnsAfter.push_back( AdMI );
595 } // the LR didn't receive the suggested color
597 } // if there a return value
600 //-------------------------------------------
601 // Now color all args of the call instruction
602 //-------------------------------------------
604 vector <MachineInstr *> AddedInstrnsBefore;
606 unsigned NumOfCallArgs = getCallInstNumArgs( CallMI );
608 bool VarArgCall = isVarArgCall( CallMI );
610 if(VarArgCall) cerr << "\nVar arg call found!!\n";
612 for(unsigned argNo=0, i=0; i < NumOfCallArgs; ++i, ++argNo ) {
614 const Value *CallArg = CallMI->getImplicitRef(i);
616 // get the LR of call operand (parameter)
617 LiveRange *const LR = LRI.getLiveRangeForValue(CallArg);
619 unsigned RegType = getRegType( CallArg );
620 unsigned RegClassID = getRegClassIDOfValue( CallArg);
622 // find whether this argument is coming in a register (if not, on stack)
624 bool isArgInReg = false;
625 unsigned UniArgReg = InvalidRegNum; // reg that LR must be colored with
627 if( (RegType== IntRegType && argNo < NumOfIntArgRegs)) {
629 UniArgReg = getUnifiedRegNum(RegClassID, SparcIntRegOrder::o0 + argNo );
631 else if(RegType == FPSingleRegType && argNo < NumOfFloatArgRegs) {
635 UniArgReg = getUnifiedRegNum(RegClassID,
636 SparcFloatRegOrder::f0 + (argNo*2 + 1) );
638 // a variable argument call - must pass float arg in %o's
639 if( argNo < NumOfIntArgRegs)
640 UniArgReg=getUnifiedRegNum(IntRegClassID,SparcIntRegOrder::o0+argNo);
646 else if(RegType == FPDoubleRegType && argNo < NumOfFloatArgRegs) {
650 UniArgReg =getUnifiedRegNum(RegClassID,SparcFloatRegOrder::f0+argNo*2);
652 // a variable argument call - must pass float arg in %o's
653 if( argNo < NumOfIntArgRegs)
654 UniArgReg=getUnifiedRegNum(IntRegClassID,SparcIntRegOrder::o0+argNo);
660 // not possible to have a null LR since all args (even consts)
661 // must be defined before
664 cerr << " ERROR: In call instr, no LR for arg: " ;
665 printValue(CallArg); cerr << endl;
667 assert(0 && "NO LR for call arg");
672 if( LR->hasColor() ) {
675 unsigned UniLRReg = getUnifiedRegNum( RegClassID, LR->getColor() );
677 // if LR received the correct color, nothing to do
678 if( UniLRReg == UniArgReg )
681 // We are here because though the LR is allocated a register, it
682 // was not allocated the suggested register. So, we have to copy %ix reg
683 // (or stack pos of arg) to the register it was colored with
685 // the LR is colored with UniLRReg but has to go into UniArgReg
686 // to pass it as an argument
690 if( VarArgCall && RegClassID == FloatRegClassID ) {
693 // for a variable argument call, the float reg must go in a %o reg.
694 // We have to move a float reg to an int reg via memory.
695 // The store instruction will be directly added to
696 // CallAI->InstrnsBefore since it does not need reordering
698 int TmpOff = PRA.mcInfo.pushTempValue(target,
699 getSpilledRegSize(RegType));
701 AdMI = cpReg2MemMI(UniLRReg, getFramePointer(), TmpOff, RegType );
702 CallAI->InstrnsBefore.push_back( AdMI );
704 AdMI = cpMem2RegMI(getFramePointer(), TmpOff, UniArgReg, IntRegType);
705 AddedInstrnsBefore.push_back( AdMI );
709 AdMI = cpReg2RegMI(UniLRReg, UniArgReg, RegType );
710 AddedInstrnsBefore.push_back( AdMI );
716 // Now, we have to pass the arg on stack. Since LR received a register
717 // we just have to move that register to the stack position where
718 // the argument must be passed
720 int argOffset = PRA.mcInfo.allocateOptionalArg(target, LR->getType());
722 AdMI = cpReg2MemMI(UniLRReg, getStackPointer(), argOffset, RegType );
724 // Now add the instruction. We can directly add to
725 // CallAI->InstrnsBefore since we are just saving a reg on stack
727 CallAI->InstrnsBefore.push_back( AdMI );
729 //cerr << "\nCaution: Passing a reg on stack";
735 else { // LR is not colored (i.e., spilled)
739 // Now the LR did NOT recieve a register but has a stack poistion.
740 // Since, the outgoing arg goes in a register we just have to insert
741 // a load instruction to load the LR to outgoing register
743 if( VarArgCall && RegClassID == FloatRegClassID )
744 AdMI = cpMem2RegMI(getFramePointer(), LR->getSpillOffFromFP(),
745 UniArgReg, IntRegType );
747 AdMI = cpMem2RegMI(getFramePointer(), LR->getSpillOffFromFP(),
748 UniArgReg, RegType );
750 cerr << "\nCaution: Loading a spilled val to a reg as a call arg";
751 AddedInstrnsBefore.push_back( AdMI ); // Now add the instruction
755 // Now, we have to pass the arg on stack. Since LR also did NOT
756 // receive a register we have to move an argument in memory to
757 // outgoing parameter on stack.
759 // Optoimize: Optimize when reverse pointers in MahineInstr are
761 // call PRA.getUnusedRegAtMI(....) to get an unused reg. Only if this
762 // fails, then use the following code. Currently, we cannot call the
763 // above method since we cannot find LVSetBefore without the BB
765 int TReg = PRA.getUniRegNotUsedByThisInst( LR->getRegClass(), CallMI );
767 int TmpOff = PRA.mcInfo.pushTempValue(target,
768 getSpilledRegSize(getRegType(LR)) );
771 int argOffset = PRA.mcInfo.allocateOptionalArg(target, LR->getType());
773 MachineInstr *Ad1, *Ad2, *Ad3, *Ad4;
776 // (1) Save TReg on stack
777 // (2) Load LR value into TReg from stack pos of LR
778 // (3) Store Treg on outgoing Arg pos on stack
779 // (4) Load the old value of TReg from stack to TReg (restore it)
781 Ad1 = cpReg2MemMI(TReg, getFramePointer(), TmpOff, RegType );
782 Ad2 = cpMem2RegMI(getFramePointer(), LR->getSpillOffFromFP(),
784 Ad3 = cpReg2MemMI(TReg, getStackPointer(), argOffset, RegType );
785 Ad4 = cpMem2RegMI(getFramePointer(), TmpOff, TReg, RegType );
787 // We directly add to CallAI->InstrnsBefore instead of adding to
788 // AddedInstrnsBefore since these instructions must not be
791 CallAI->InstrnsBefore.push_back( Ad1 );
792 CallAI->InstrnsBefore.push_back( Ad2 );
793 CallAI->InstrnsBefore.push_back( Ad3 );
794 CallAI->InstrnsBefore.push_back( Ad4 );
796 cerr << "\nCaution: Call arg moved from stack2stack for: " << *CallMI ;
801 } // for each parameter in call instruction
804 // if we added any instruction before the call instruction, verify
805 // that they are in the proper order and if not, reorder them
807 if( ! AddedInstrnsBefore.empty() ) {
810 cerr << "\nCalling reorder with instrns: \n";
811 for(unsigned i=0; i < AddedInstrnsBefore.size(); i++)
812 cerr << *(AddedInstrnsBefore[i]);
815 vector <MachineInstr *> TmpVec;
816 OrderAddedInstrns(AddedInstrnsBefore, TmpVec, PRA);
819 cerr << "\nAfter reordering instrns: \n";
820 for(unsigned i=0; i < TmpVec.size(); i++)
821 cerr << *(TmpVec[i]);
824 // copy the results back from TmpVec to InstrnsBefore
825 for(unsigned i=0; i < TmpVec.size(); i++)
826 CallAI->InstrnsBefore.push_back( TmpVec[i] );
830 // now insert caller saving code for this call instruction
832 insertCallerSavingCode(CallMI, BB, PRA);
835 // Reset optional args area again to be safe
836 PRA.mcInfo.resetOptionalArgs(target);
841 //---------------------------------------------------------------------------
842 // This method is called for an LLVM return instruction to identify which
843 // values will be returned from this method and to suggest colors.
844 //---------------------------------------------------------------------------
845 void UltraSparcRegInfo::suggestReg4RetValue(const MachineInstr *const RetMI,
846 LiveRangeInfo& LRI) const {
848 assert( (UltraSparcInfo->getInstrInfo()).isReturn( RetMI->getOpCode() ) );
850 suggestReg4RetAddr(RetMI, LRI);
852 // if there is an implicit ref, that has to be the ret value
853 if( RetMI->getNumImplicitRefs() > 0 ) {
855 // The first implicit operand is the return value of a return instr
856 const Value *RetVal = RetMI->getImplicitRef(0);
859 LiveRange *const LR = LRI.getLiveRangeForValue( RetVal );
862 cerr << "\nNo LR for:";
863 printValue( RetVal );
865 assert( LR && "No LR for return value of non-void method");
869 unsigned RegClassID = (LR->getRegClass())->getID();
871 if( RegClassID == IntRegClassID )
872 LR->setSuggestedColor(SparcIntRegOrder::i0);
874 else if ( RegClassID == FloatRegClassID )
875 LR->setSuggestedColor(SparcFloatRegOrder::f0);
883 //---------------------------------------------------------------------------
884 // Colors the return value of a method to %i0 or %f0, if possible. If it is
885 // not possilbe to directly color the LR, insert a copy instruction to move
886 // the LR to %i0 or %f0. When the LR is spilled, instead of the copy, we
887 // have to put a load instruction.
888 //---------------------------------------------------------------------------
889 void UltraSparcRegInfo::colorRetValue(const MachineInstr *const RetMI,
891 AddedInstrns *const RetAI) const {
893 assert( (UltraSparcInfo->getInstrInfo()).isReturn( RetMI->getOpCode() ) );
895 // if there is an implicit ref, that has to be the ret value
896 if( RetMI->getNumImplicitRefs() > 0 ) {
898 // The first implicit operand is the return value of a return instr
899 const Value *RetVal = RetMI->getImplicitRef(0);
902 LiveRange *const LR = LRI.getLiveRangeForValue( RetVal );
905 cerr << "\nNo LR for:";
906 printValue( RetVal );
908 // assert( LR && "No LR for return value of non-void method");
912 unsigned RegClassID = getRegClassIDOfValue(RetVal);
913 unsigned RegType = getRegType( RetVal );
916 if(RegClassID == IntRegClassID)
917 CorrectCol = SparcIntRegOrder::i0;
918 else if(RegClassID == FloatRegClassID)
919 CorrectCol = SparcFloatRegOrder::f0;
921 assert( 0 && "Unknown RegClass");
925 // if the LR received the correct color, NOTHING to do
928 if( LR->getColor() == CorrectCol )
931 unsigned UniRetReg = getUnifiedRegNum( RegClassID, CorrectCol );
933 if( LR->hasColor() ) {
935 // We are here because the LR was allocted a regiter
936 // It may be the suggested register or not
938 // copy the LR of retun value to i0 or f0
940 unsigned UniLRReg =getUnifiedRegNum( RegClassID, LR->getColor());
942 // the LR received UniLRReg but must be colored with UniRetReg
943 // to pass as the return value
945 AdMI = cpReg2RegMI( UniLRReg, UniRetReg, RegType);
946 RetAI->InstrnsBefore.push_back( AdMI );
948 else { // if the LR is spilled
950 AdMI = cpMem2RegMI(getFramePointer(), LR->getSpillOffFromFP(),
952 RetAI->InstrnsBefore.push_back( AdMI );
953 cout << "\nCopied the return value from stack";
956 } // if there is a return value
961 //---------------------------------------------------------------------------
962 // Copy from a register to register. Register number must be the unified
964 //---------------------------------------------------------------------------
966 MachineInstr * UltraSparcRegInfo::cpReg2RegMI(const unsigned SrcReg,
967 const unsigned DestReg,
968 const int RegType) const {
970 assert( ((int)SrcReg != InvalidRegNum) && ((int)DestReg != InvalidRegNum) &&
973 MachineInstr * MI = NULL;
980 MI = new MachineInstr(ADD, 3);
981 MI->SetMachineOperand(0, SrcReg, false);
982 MI->SetMachineOperand(1, SparcIntRegOrder::g0, false);
983 MI->SetMachineOperand(2, DestReg, true);
986 case FPSingleRegType:
987 MI = new MachineInstr(FMOVS, 2);
988 MI->SetMachineOperand(0, SrcReg, false);
989 MI->SetMachineOperand(1, DestReg, true);
992 case FPDoubleRegType:
993 MI = new MachineInstr(FMOVD, 2);
994 MI->SetMachineOperand(0, SrcReg, false);
995 MI->SetMachineOperand(1, DestReg, true);
999 assert(0 && "Unknow RegType");
1006 //---------------------------------------------------------------------------
1007 // Copy from a register to memory (i.e., Store). Register number must
1008 // be the unified register number
1009 //---------------------------------------------------------------------------
1012 MachineInstr * UltraSparcRegInfo::cpReg2MemMI(const unsigned SrcReg,
1013 const unsigned DestPtrReg,
1015 const int RegType) const {
1018 MachineInstr * MI = NULL;
1023 case FloatCCRegType:
1024 MI = new MachineInstr(STX, 3);
1025 MI->SetMachineOperand(0, SrcReg, false);
1026 MI->SetMachineOperand(1, DestPtrReg, false);
1027 MI->SetMachineOperand(2, MachineOperand:: MO_SignExtendedImmed,
1028 (int64_t) Offset, false);
1031 case FPSingleRegType:
1032 MI = new MachineInstr(ST, 3);
1033 MI->SetMachineOperand(0, SrcReg, false);
1034 MI->SetMachineOperand(1, DestPtrReg, false);
1035 MI->SetMachineOperand(2, MachineOperand:: MO_SignExtendedImmed,
1036 (int64_t) Offset, false);
1039 case FPDoubleRegType:
1040 MI = new MachineInstr(STD, 3);
1041 MI->SetMachineOperand(0, SrcReg, false);
1042 MI->SetMachineOperand(1, DestPtrReg, false);
1043 MI->SetMachineOperand(2, MachineOperand:: MO_SignExtendedImmed,
1044 (int64_t) Offset, false);
1048 assert( 0 && "Cannot directly store %ccr to memory");
1051 assert(0 && "Unknow RegType in cpReg2MemMI");
1058 //---------------------------------------------------------------------------
1059 // Copy from memory to a reg (i.e., Load) Register number must be the unified
1061 //---------------------------------------------------------------------------
1064 MachineInstr * UltraSparcRegInfo::cpMem2RegMI(const unsigned SrcPtrReg,
1066 const unsigned DestReg,
1067 const int RegType) const {
1069 MachineInstr * MI = NULL;
1074 case FloatCCRegType:
1075 MI = new MachineInstr(LDX, 3);
1076 MI->SetMachineOperand(0, SrcPtrReg, false);
1077 MI->SetMachineOperand(1, MachineOperand:: MO_SignExtendedImmed,
1078 (int64_t) Offset, false);
1079 MI->SetMachineOperand(2, DestReg, true);
1082 case FPSingleRegType:
1083 MI = new MachineInstr(LD, 3);
1084 MI->SetMachineOperand(0, SrcPtrReg, false);
1085 MI->SetMachineOperand(1, MachineOperand:: MO_SignExtendedImmed,
1086 (int64_t) Offset, false);
1087 MI->SetMachineOperand(2, DestReg, true);
1091 case FPDoubleRegType:
1092 MI = new MachineInstr(LDD, 3);
1093 MI->SetMachineOperand(0, SrcPtrReg, false);
1094 MI->SetMachineOperand(1, MachineOperand:: MO_SignExtendedImmed,
1095 (int64_t) Offset, false);
1096 MI->SetMachineOperand(2, DestReg, true);
1100 assert( 0 && "Cannot directly load into %ccr from memory");
1103 assert(0 && "Unknown RegType in cpMem2RegMI");
1113 //---------------------------------------------------------------------------
1114 // Generate a copy instruction to copy a value to another. Temporarily
1115 // used by PhiElimination code.
1116 //---------------------------------------------------------------------------
1119 MachineInstr * UltraSparcRegInfo::cpValue2Value(Value *Src, Value *Dest) const{
1121 int RegType = getRegType( Src );
1123 assert( (RegType==getRegType(Src)) && "Src & Dest are diff types");
1125 MachineInstr * MI = NULL;
1131 MI = new MachineInstr(ADD, 3);
1132 MI->SetMachineOperand(0, MachineOperand:: MO_VirtualRegister, Src, false);
1133 MI->SetMachineOperand(1, SparcIntRegOrder::g0, false);
1134 MI->SetMachineOperand(2, MachineOperand:: MO_VirtualRegister, Dest, true);
1137 case FPSingleRegType:
1138 MI = new MachineInstr(FMOVS, 2);
1139 MI->SetMachineOperand(0, MachineOperand:: MO_VirtualRegister, Src, false);
1140 MI->SetMachineOperand(1, MachineOperand:: MO_VirtualRegister, Dest, true);
1144 case FPDoubleRegType:
1145 MI = new MachineInstr(FMOVD, 2);
1146 MI->SetMachineOperand(0, MachineOperand:: MO_VirtualRegister, Src, false);
1147 MI->SetMachineOperand(1, MachineOperand:: MO_VirtualRegister, Dest, true);
1151 assert(0 && "Unknow RegType in CpValu2Value");
1162 //----------------------------------------------------------------------------
1163 // This method inserts caller saving/restoring instructons before/after
1164 // a call machine instruction.
1165 //----------------------------------------------------------------------------
1168 void UltraSparcRegInfo::insertCallerSavingCode(const MachineInstr *MInst,
1169 const BasicBlock *BB,
1170 PhyRegAlloc &PRA) const {
1171 // assert( (getInstrInfo()).isCall( MInst->getOpCode() ) );
1173 // Clear the temp area of the stack
1174 //PRA.mcInfo.popAllTempValues(target);
1175 // TODO*** Don't do this since we can have a situation like
1178 stx %o1 %i6 1999 <--- inserted by this code
1182 stx %o1 %i6 2007 ???? <-- inserted by statck2stack call arg
1187 hash_set<unsigned> PushedRegSet;
1189 // Now find the LR of the return value of the call
1190 // The last *implicit operand* is the return value of a call
1191 // Insert it to to he PushedRegSet since we must not save that register
1192 // and restore it after the call.
1193 // We do this because, we look at the LV set *after* the instruction
1194 // to determine, which LRs must be saved across calls. The return value
1195 // of the call is live in this set - but we must not save/restore it.
1198 const Value *RetVal = getCallInstRetVal( MInst );
1202 LiveRange *RetValLR = PRA.LRI.getLiveRangeForValue( RetVal );
1203 assert( RetValLR && "No LR for RetValue of call");
1205 if( RetValLR->hasColor())
1206 PushedRegSet.insert(
1207 getUnifiedRegNum((RetValLR->getRegClass())->getID(),
1208 RetValLR->getColor() ) );
1212 const LiveVarSet *LVSetAft = PRA.LVI->getLiveVarSetAfterMInst(MInst, BB);
1214 LiveVarSet::const_iterator LIt = LVSetAft->begin();
1216 // for each live var in live variable set after machine inst
1217 for( ; LIt != LVSetAft->end(); ++LIt) {
1219 // get the live range corresponding to live var
1220 LiveRange *const LR = PRA.LRI.getLiveRangeForValue(*LIt );
1222 // LR can be null if it is a const since a const
1223 // doesn't have a dominating def - see Assumptions above
1226 if( LR->hasColor() ) {
1228 unsigned RCID = (LR->getRegClass())->getID();
1229 unsigned Color = LR->getColor();
1231 if ( isRegVolatile(RCID, Color) ) {
1233 // if the value is in both LV sets (i.e., live before and after
1234 // the call machine instruction)
1236 unsigned Reg = getUnifiedRegNum(RCID, Color);
1238 if( PushedRegSet.find(Reg) == PushedRegSet.end() ) {
1240 // if we haven't already pushed that register
1242 unsigned RegType = getRegType( LR );
1244 // Now get two instructions - to push on stack and pop from stack
1245 // and add them to InstrnsBefore and InstrnsAfter of the
1249 int StackOff = PRA.mcInfo.pushTempValue(target,
1250 getSpilledRegSize(RegType));
1253 MachineInstr *AdIBefCC, *AdIAftCC, *AdICpCC;
1254 MachineInstr *AdIBef, *AdIAft;
1257 //---- Insert code for pushing the reg on stack ----------
1259 if( RegType == IntCCRegType ) {
1261 // Handle IntCCRegType specially since we cannot directly
1262 // push %ccr on to the stack
1264 const LiveVarSet *LVSetBef =
1265 PRA.LVI->getLiveVarSetBeforeMInst(MInst, BB);
1267 // get a free INTEGER register
1269 PRA.getUsableUniRegAtMI(LR->getRegClass(), IntRegType, MInst,
1270 LVSetBef, AdIBefCC, AdIAftCC);
1272 // insert the instructions in reverse order since we are
1273 // adding them to the front of InstrnsBefore
1276 (PRA.AddedInstrMap[MInst]->InstrnsBefore).push_front(AdIAftCC);
1278 AdICpCC = cpCCR2IntMI(FreeIntReg);
1279 (PRA.AddedInstrMap[MInst]->InstrnsBefore).push_front(AdICpCC);
1282 (PRA.AddedInstrMap[MInst]->InstrnsBefore).push_front(AdIBefCC);
1285 cerr << "\n!! Inserted caller saving (push) inst for %ccr:";
1286 if(AdIBefCC) cerr << "\t" << *(AdIBefCC);
1287 cerr << "\t" << *AdICpCC;
1288 if(AdIAftCC) cerr << "\t" << *(AdIAftCC);
1292 // for any other register type, just add the push inst
1293 AdIBef = cpReg2MemMI(Reg, getFramePointer(), StackOff, RegType );
1294 ((PRA.AddedInstrMap[MInst])->InstrnsBefore).push_front(AdIBef);
1298 //---- Insert code for popping the reg from the stack ----------
1300 if( RegType == IntCCRegType ) {
1302 // Handle IntCCRegType specially since we cannot directly
1303 // pop %ccr on from the stack
1305 // get a free INT register
1307 PRA.getUsableUniRegAtMI(LR->getRegClass(), IntRegType, MInst,
1308 LVSetAft, AdIBefCC, AdIAftCC);
1311 (PRA.AddedInstrMap[MInst]->InstrnsAfter).push_back(AdIBefCC);
1313 AdICpCC = cpInt2CCRMI(FreeIntReg);
1314 (PRA.AddedInstrMap[MInst]->InstrnsAfter).push_back(AdICpCC);
1317 (PRA.AddedInstrMap[MInst]->InstrnsAfter).push_back(AdIAftCC);
1321 cerr << "\n!! Inserted caller saving (pop) inst for %ccr:";
1322 if(AdIBefCC) cerr << "\t" << *(AdIBefCC);
1323 cerr << "\t" << *AdICpCC;
1324 if(AdIAftCC) cerr << "\t" << *(AdIAftCC);
1328 // for any other register type, just add the pop inst
1329 AdIAft = cpMem2RegMI(getFramePointer(), StackOff, Reg, RegType );
1330 ((PRA.AddedInstrMap[MInst])->InstrnsAfter).push_back(AdIAft);
1333 PushedRegSet.insert( Reg );
1336 cerr << "\nFor call inst:" << *MInst;
1337 cerr << " -inserted caller saving instrs:\n\t ";
1338 if( RegType == IntCCRegType )
1339 cerr << *AdIBefCC << "\t" << *AdIAftCC ;
1341 cerr << *AdIBef << "\t" << *AdIAft ;
1343 } // if not already pushed
1345 } // if LR has a volatile color
1347 } // if LR has color
1349 } // if there is a LR for Var
1351 } // for each value in the LV set after instruction
1353 // Clear the temp area of the stack
1354 // PRA.mcInfo.popAllTempValues(target);
1355 // TODO *** see above call - optimize later
1360 //---------------------------------------------------------------------------
1361 // Copies %ccr into an integer register. IntReg is the UNIFIED register
1363 //---------------------------------------------------------------------------
1365 MachineInstr * UltraSparcRegInfo::cpCCR2IntMI(const unsigned IntReg) const {
1366 MachineInstr * MI = NULL;
1368 MI = new MachineInstr(RDCCR, 2);
1369 MI->SetMachineOperand(0, SparcIntCCRegOrder::ccr, false);
1370 MI->SetMachineOperand(1, IntReg, true);
1375 //---------------------------------------------------------------------------
1376 // Copies an integer register into %ccr. IntReg is the UNIFIED register
1378 //---------------------------------------------------------------------------
1380 MachineInstr * UltraSparcRegInfo::cpInt2CCRMI(const unsigned IntReg) const {
1381 MachineInstr * MI = NULL;
1383 MI = new MachineInstr(WRCCR, 3);
1384 MI->SetMachineOperand(0, IntReg, false);
1385 MI->SetMachineOperand(1, SparcIntRegOrder::g0, false);
1386 MI->SetMachineOperand(2, SparcIntCCRegOrder::ccr, true);
1394 //---------------------------------------------------------------------------
1395 // Print the register assigned to a LR
1396 //---------------------------------------------------------------------------
1398 void UltraSparcRegInfo::printReg(const LiveRange *const LR) {
1400 unsigned RegClassID = (LR->getRegClass())->getID();
1402 cerr << " *Node " << (LR->getUserIGNode())->getIndex();
1404 if( ! LR->hasColor() ) {
1405 cerr << " - could not find a color" << endl;
1409 // if a color is found
1411 cerr << " colored with color "<< LR->getColor();
1413 if( RegClassID == IntRegClassID ) {
1415 cerr<< " [" << SparcIntRegOrder::getRegName(LR->getColor()) ;
1416 cerr << "]" << endl;
1418 else if ( RegClassID == FloatRegClassID) {
1419 cerr << "[" << SparcFloatRegOrder::getRegName(LR->getColor());
1420 if( LR->getTypeID() == Type::DoubleTyID )
1421 cerr << "+" << SparcFloatRegOrder::getRegName(LR->getColor()+1);
1422 cerr << "]" << endl;
1426 //---------------------------------------------------------------------------
1427 // This method examines instructions inserted by RegAlloc code before a
1428 // machine instruction to detect invalid orders that destroy values before
1429 // they are used. If it detects such conditions, it reorders the instructions.
1431 // The unordered instructions come in the UnordVec. These instructions are
1432 // instructions inserted by RegAlloc. All such instruction MUST have
1433 // their USES BEFORE THE DEFS after reordering.
1435 // The UnordVec & OrdVec must be DISTINCT. The OrdVec must be empty when
1436 // this method is called.
1438 // This method uses two vectors for efficiency in accessing
1440 // Since instructions are inserted in RegAlloc, this assumes that the
1441 // first operand is the source reg and the last operand is the dest reg.
1443 // All the uses are before THE def to a register
1446 //---------------------------------------------------------------------------
1447 void UltraSparcRegInfo::OrderAddedInstrns( vector<MachineInstr *> &UnordVec,
1448 vector<MachineInstr *> &OrdVec,
1449 PhyRegAlloc &PRA) const{
1452 Problem: We can have instructions inserted by RegAlloc like
1454 2. add %oy %g0 %oz, where z!=x or z==x
1456 This is wrong since %oy used by 2 is overwritten by 1
1459 We re-order the instructions so that the uses are before the defs
1464 for each instruction 'DefInst' in the UnOrdVec
1465 for each instruction 'UseInst' that follows the DefInst
1466 if the reg defined by DefInst is used by UseInst
1467 mark DefInst as not movable in this iteration
1468 If DefInst is not marked as not-movable, move DefInst to OrdVec
1469 while all instructions in DefInst are moved to OrdVec
1471 For moving, we call the move2OrdVec(). It checks whether there is a def
1472 in it for the uses in the instruction to be added to OrdVec. If there
1473 are no preceding defs, it just appends the instruction. If there is a
1474 preceding def, it puts two instructions to save the reg on stack before
1475 the load and puts a restore at use.
1481 bool DebugPrint = false;
1485 CouldMoveAll = true;
1487 vector<MachineInstr *>::iterator DefIt = UnordVec.begin();
1489 for( ; DefIt != UnordVec.end(); ++DefIt ) {
1491 // for each instruction in the UnordVec do ...
1493 MachineInstr *DefInst = *DefIt;
1495 if( DefInst == NULL) continue;
1497 //cerr << "\nInst in UnordVec = " << *DefInst;
1499 // last operand is the def (unless for a store which has no def reg)
1500 MachineOperand& DefOp = DefInst->getOperand(DefInst->getNumOperands()-1);
1502 if( DefOp.opIsDef() &&
1503 DefOp.getOperandType() == MachineOperand::MO_MachineRegister) {
1505 // If the operand in DefInst is a def ...
1507 bool DefEqUse = false;
1509 vector<MachineInstr *>::iterator UseIt = DefIt;
1512 for( ; UseIt != UnordVec.end(); ++UseIt ) {
1514 MachineInstr *UseInst = *UseIt;
1515 if( UseInst == NULL) continue;
1517 // for each inst (UseInst) that is below the DefInst do ...
1520 MachineOperand& UseOp = UseInst->getOperand(0);
1522 if( ! UseOp.opIsDef() &&
1523 UseOp.getOperandType() == MachineOperand::MO_MachineRegister) {
1525 // if use is a register ...
1527 if( DefOp.getMachineRegNum() == UseOp.getMachineRegNum() ) {
1529 // if Def and this use are the same, it means that this use
1530 // is destroyed by a def before it is used
1532 // cerr << "\nCouldn't move " << *DefInst;
1535 CouldMoveAll = false;
1538 } // if two registers are equal
1540 } // if use is a register
1542 }// for all use instructions
1546 // after examining all the instructions that follow the DefInst
1547 // if there are no dependencies, we can move it to the OrdVec
1549 // cerr << "Moved to Ord: " << *DefInst;
1551 moveInst2OrdVec(OrdVec, DefInst, PRA);
1553 //OrdVec.push_back(DefInst);
1555 // mark the pos of DefInst with NULL to indicate that it is
1560 } // if Def is a machine register
1562 } // for all instructions in the UnordVec
1565 } while( !CouldMoveAll);
1569 cerr << "\nAdded instructions were reordered to:\n";
1570 for(unsigned int i=0; i < OrdVec.size(); i++)
1571 cerr << *(OrdVec[i]);
1583 void UltraSparcRegInfo::moveInst2OrdVec(vector<MachineInstr *> &OrdVec,
1584 MachineInstr *UnordInst,
1585 PhyRegAlloc &PRA ) const {
1587 MachineOperand& UseOp = UnordInst->getOperand(0);
1589 if( ! UseOp.opIsDef() &&
1590 UseOp.getOperandType() == MachineOperand::MO_MachineRegister) {
1592 // for the use of UnordInst, see whether there is a defining instr
1593 // before in the OrdVec
1594 bool DefEqUse = false;
1596 vector<MachineInstr *>::iterator OrdIt = OrdVec.begin();
1598 for( ; OrdIt != OrdVec.end(); ++OrdIt ) {
1600 MachineInstr *OrdInst = *OrdIt ;
1602 MachineOperand& DefOp =
1603 OrdInst->getOperand(OrdInst->getNumOperands()-1);
1605 if( DefOp.opIsDef() &&
1606 DefOp.getOperandType() == MachineOperand::MO_MachineRegister) {
1608 //cerr << "\nDefining Ord Inst: " << *OrdInst;
1610 if( DefOp.getMachineRegNum() == UseOp.getMachineRegNum() ) {
1612 // we are here because there is a preceding def in the OrdVec
1613 // for the use in this intr we are going to insert. This
1614 // happened because the original code was like:
1615 // 1. add %ox %g0 %oy
1616 // 2. add %oy %g0 %ox
1617 // In Round1, we added 2 to OrdVec but 1 remained in UnordVec
1618 // Now we are processing %ox of 1.
1621 const int UReg = DefOp.getMachineRegNum();
1622 const int RegType = getRegType(UReg);
1623 MachineInstr *AdIBef, *AdIAft;
1625 const int StackOff = PRA.mcInfo.pushTempValue(target,
1626 getSpilledRegSize(RegType));
1628 // Save the UReg (%ox) on stack before it's destroyed
1629 AdIBef=cpReg2MemMI(UReg, getFramePointer(), StackOff, RegType);
1630 OrdIt = OrdVec.insert( OrdIt, AdIBef);
1631 OrdIt++; // points to current instr we processed
1633 // Load directly into DReg (%oy)
1634 MachineOperand& DOp=
1635 (UnordInst->getOperand(UnordInst->getNumOperands()-1));
1636 assert(DOp.opIsDef() && "Last operand is not the def");
1637 const int DReg = DOp.getMachineRegNum();
1639 AdIAft=cpMem2RegMI(getFramePointer(), StackOff, DReg, RegType);
1640 OrdVec.push_back(AdIAft);
1642 cerr << "\nFixed CIRCULAR references by reordering";
1645 cerr << "\nBefore CIRCULAR Reordering:\n";
1649 cerr << "\nAfter CIRCULAR Reordering - All Inst so far:\n";
1650 for(unsigned i=0; i < OrdVec.size(); i++)
1651 cerr << *(OrdVec[i]);
1654 // Do not copy the UseInst to OrdVec
1658 }// if two registers are equal
1660 } // if Def is a register
1662 } // for each instr in OrdVec
1666 // We didn't find a def in the OrdVec, so just append this inst
1667 OrdVec.push_back( UnordInst );
1668 //cerr << "Reordered Inst (Moved Dn): " << *UnordInst;
1671 }// if the operand in UnordInst is a use