2 //***************************************************************************
7 // This file defines stuff that is to be private to the Sparc
8 // backend, but is shared among different portions of the backend.
9 //**************************************************************************/
12 #ifndef SPARC_INTERNALS_H
13 #define SPARC_INTERNALS_H
15 #include "llvm/Target/TargetMachine.h"
16 #include "llvm/Target/MachineInstrInfo.h"
17 #include "llvm/Target/MachineSchedInfo.h"
18 #include "llvm/Target/MachineFrameInfo.h"
19 #include "llvm/Target/MachineCacheInfo.h"
20 #include "llvm/Target/MachineRegInfo.h"
21 #include "llvm/Type.h"
22 #include <sys/types.h>
29 // OpCodeMask definitions for the Sparc V9
31 const OpCodeMask Immed = 0x00002000; // immed or reg operand?
32 const OpCodeMask Annul = 0x20000000; // annul delay instr?
33 const OpCodeMask PredictTaken = 0x00080000; // predict branch taken?
36 enum SparcInstrSchedClass {
37 SPARC_NONE, /* Instructions with no scheduling restrictions */
38 SPARC_IEUN, /* Integer class that can use IEU0 or IEU1 */
39 SPARC_IEU0, /* Integer class IEU0 */
40 SPARC_IEU1, /* Integer class IEU1 */
41 SPARC_FPM, /* FP Multiply or Divide instructions */
42 SPARC_FPA, /* All other FP instructions */
43 SPARC_CTI, /* Control-transfer instructions */
44 SPARC_LD, /* Load instructions */
45 SPARC_ST, /* Store instructions */
46 SPARC_SINGLE, /* Instructions that must issue by themselves */
48 SPARC_INV, /* This should stay at the end for the next value */
49 SPARC_NUM_SCHED_CLASSES = SPARC_INV
53 //---------------------------------------------------------------------------
54 // enum SparcMachineOpCode.
55 // const MachineInstrDescriptor SparcMachineInstrDesc[]
58 // Description of UltraSparc machine instructions.
60 //---------------------------------------------------------------------------
62 enum SparcMachineOpCode {
63 #define I(ENUM, OPCODESTRING, NUMOPERANDS, RESULTPOS, MAXIMM, IMMSE, \
64 NUMDELAYSLOTS, LATENCY, SCHEDCLASS, INSTFLAGS) \
66 #include "SparcInstr.def"
68 // End-of-array marker
70 NUM_REAL_OPCODES = PHI, // number of valid opcodes
71 NUM_TOTAL_OPCODES = INVALID_OPCODE
75 // Array of machine instruction descriptions...
76 extern const MachineInstrDescriptor SparcMachineInstrDesc[];
79 //---------------------------------------------------------------------------
80 // class UltraSparcInstrInfo
83 // Information about individual instructions.
84 // Most information is stored in the SparcMachineInstrDesc array above.
85 // Other information is computed on demand, and most such functions
86 // default to member functions in base class MachineInstrInfo.
87 //---------------------------------------------------------------------------
89 class UltraSparcInstrInfo : public MachineInstrInfo {
91 /*ctor*/ UltraSparcInstrInfo(const TargetMachine& tgt);
94 // All immediate constants are in position 0 except the
95 // store instructions.
97 virtual int getImmmedConstantPos(MachineOpCode opCode) const {
99 if (this->maxImmedConstant(opCode, ignore) != 0)
101 assert(! this->isStore((MachineOpCode) STB - 1)); // first store is STB
102 assert(! this->isStore((MachineOpCode) STD + 1)); // last store is STD
103 return (opCode >= STB || opCode <= STD)? 2 : 1;
109 virtual bool hasResultInterlock (MachineOpCode opCode) const
111 // All UltraSPARC instructions have interlocks (note that delay slots
112 // are not considered here).
113 // However, instructions that use the result of an FCMP produce a
114 // 9-cycle stall if they are issued less than 3 cycles after the FCMP.
115 // Force the compiler to insert a software interlock (i.e., gap of
116 // 2 other groups, including NOPs if necessary).
117 return (opCode == FCMPS || opCode == FCMPD || opCode == FCMPQ);
120 //-------------------------------------------------------------------------
121 // Code generation support for creating individual machine instructions
122 //-------------------------------------------------------------------------
124 // Create an instruction sequence to put the constant `val' into
125 // the virtual register `dest'. The generated instructions are
126 // returned in `minstrVec'. Any temporary registers (TmpInstruction)
127 // created are returned in `tempVec'.
129 virtual void CreateCodeToLoadConst(Value* val,
131 std::vector<MachineInstr*>& minstrVec,
132 std::vector<TmpInstruction*>& tmp) const;
135 // Create an instruction sequence to copy an integer value `val'
136 // to a floating point value `dest' by copying to memory and back.
137 // val must be an integral type. dest must be a Float or Double.
138 // The generated instructions are returned in `minstrVec'.
139 // Any temp. registers (TmpInstruction) created are returned in `tempVec'.
141 virtual void CreateCodeToCopyIntToFloat(Method* method,
144 std::vector<MachineInstr*>& minstr,
145 std::vector<TmpInstruction*>& temp,
146 TargetMachine& target) const;
148 // Similarly, create an instruction sequence to copy an FP value
149 // `val' to an integer value `dest' by copying to memory and back.
150 // See the previous function for information about return values.
152 virtual void CreateCodeToCopyFloatToInt(Method* method,
155 std::vector<MachineInstr*>& minstr,
156 std::vector<TmpInstruction*>& temp,
157 TargetMachine& target) const;
159 // create copy instruction(s)
161 CreateCopyInstructionsByType(const TargetMachine& target,
164 std::vector<MachineInstr*>& minstr) const;
168 //----------------------------------------------------------------------------
169 // class UltraSparcRegInfo
171 // This class implements the virtual class MachineRegInfo for Sparc.
173 //----------------------------------------------------------------------------
175 class UltraSparcRegInfo : public MachineRegInfo {
176 // The actual register classes in the Sparc
179 IntRegClassID, // Integer
180 FloatRegClassID, // Float (both single/double)
181 IntCCRegClassID, // Int Condition Code
182 FloatCCRegClassID // Float Condition code
186 // Type of registers available in Sparc. There can be several reg types
187 // in the same class. For instace, the float reg class has Single/Double
198 // **** WARNING: If the above enum order is changed, also modify
199 // getRegisterClassOfValue method below since it assumes this particular
200 // order for efficiency.
203 // reverse pointer to get info about the ultra sparc machine
205 const UltraSparc *const UltraSparcInfo;
207 // Number of registers used for passing int args (usually 6: %o0 - %o5)
209 unsigned const NumOfIntArgRegs;
211 // Number of registers used for passing float args (usually 32: %f0 - %f31)
213 unsigned const NumOfFloatArgRegs;
215 // An out of bound register number that can be used to initialize register
216 // numbers. Useful for error detection.
218 int const InvalidRegNum;
221 // ======================== Private Methods =============================
223 // The following methods are used to color special live ranges (e.g.
224 // method args and return values etc.) with specific hardware registers
225 // as required. See SparcRegInfo.cpp for the implementation.
227 void setCallOrRetArgCol(LiveRange *LR, unsigned RegNo,
228 const MachineInstr *MI,
229 std::hash_map<const MachineInstr *,
230 AddedInstrns *> &AIMap) const;
232 MachineInstr *getCopy2RegMI(const Value *SrcVal, unsigned Reg,
233 unsigned RegClassID) const;
235 void suggestReg4RetAddr(const MachineInstr *RetMI,
236 LiveRangeInfo &LRI) const;
238 void suggestReg4CallAddr(const MachineInstr *CallMI, LiveRangeInfo &LRI,
239 std::vector<RegClass *> RCList) const;
243 // The following methods are used to find the addresses etc. contained
244 // in specail machine instructions like CALL/RET
246 Value *getValue4ReturnAddr(const MachineInstr *MInst) const;
247 const Value *getCallInstRetAddr(const MachineInstr *CallMI) const;
248 unsigned getCallInstNumArgs(const MachineInstr *CallMI) const;
251 // The following 3 methods are used to find the RegType (see enum above)
252 // of a LiveRange, Value and using the unified RegClassID
253 int getRegType(const LiveRange *LR) const;
254 int getRegType(const Value *Val) const;
255 int getRegType(int reg) const;
258 // The following methods are used to generate copy instructions to move
259 // data between condition code registers
261 MachineInstr *cpCCR2IntMI(unsigned IntReg) const;
262 MachineInstr *cpInt2CCRMI(unsigned IntReg) const;
264 // Used to generate a copy instruction based on the register class of
267 MachineInstr *cpValue2RegMI(Value *Val, unsigned DestReg,
271 // The following 2 methods are used to order the instructions addeed by
272 // the register allocator in association with method calling. See
273 // SparcRegInfo.cpp for more details
275 void moveInst2OrdVec(std::vector<MachineInstr *> &OrdVec,
276 MachineInstr *UnordInst,
277 PhyRegAlloc &PRA) const;
279 void OrderAddedInstrns(std::vector<MachineInstr *> &UnordVec,
280 std::vector<MachineInstr *> &OrdVec,
281 PhyRegAlloc &PRA) const;
284 // To find whether a particular call is to a var arg method
286 bool isVarArgCall(const MachineInstr *CallMI) const;
290 UltraSparcRegInfo(const UltraSparc &tgt);
292 // To get complete machine information structure using the machine register
295 inline const UltraSparc &getUltraSparcInfo() const {
296 return *UltraSparcInfo;
299 // To find the register class of a Value
301 inline unsigned getRegClassIDOfValue(const Value *Val,
302 bool isCCReg = false) const {
304 Type::PrimitiveID ty = Val->getType()->getPrimitiveID();
307 if ((ty && ty <= Type::LongTyID) || (ty == Type::LabelTyID) ||
308 (ty == Type::MethodTyID) || (ty == Type::PointerTyID) )
309 res = IntRegClassID; // sparc int reg (ty=0: void)
310 else if (ty <= Type::DoubleTyID)
311 res = FloatRegClassID; // sparc float reg class
313 std::cerr << "TypeID: " << ty << "\n";
314 assert(0 && "Cannot resolve register class for type");
319 return res + 2; // corresponidng condition code regiser
325 // getZeroRegNum - returns the register that contains always zero this is the
326 // unified register number
328 virtual int getZeroRegNum() const;
330 // getCallAddressReg - returns the reg used for pushing the address when a
331 // method is called. This can be used for other purposes between calls
333 unsigned getCallAddressReg() const;
335 // Returns the register containing the return address.
336 // It should be made sure that this register contains the return
337 // value when a return instruction is reached.
339 unsigned getReturnAddressReg() const;
343 // The following methods are used to color special live ranges (e.g.
344 // method args and return values etc.) with specific hardware registers
345 // as required. See SparcRegInfo.cpp for the implementation for Sparc.
347 void suggestRegs4MethodArgs(const Method *Meth,
348 LiveRangeInfo& LRI) const;
350 void suggestRegs4CallArgs(const MachineInstr *CallMI,
352 std::vector<RegClass *> RCL) const;
354 void suggestReg4RetValue(const MachineInstr *RetMI,
355 LiveRangeInfo& LRI) const;
358 void colorMethodArgs(const Method *Meth, LiveRangeInfo &LRI,
359 AddedInstrns *FirstAI) const;
361 void colorCallArgs(const MachineInstr *CallMI, LiveRangeInfo &LRI,
362 AddedInstrns *CallAI, PhyRegAlloc &PRA,
363 const BasicBlock *BB) const;
365 void colorRetValue(const MachineInstr *RetI, LiveRangeInfo& LRI,
366 AddedInstrns *RetAI) const;
370 // method used for printing a register for debugging purposes
372 static void printReg(const LiveRange *LR);
374 // this method provides a unique number for each register
376 inline int getUnifiedRegNum(int RegClassID, int reg) const {
378 if( RegClassID == IntRegClassID && reg < 32 )
380 else if ( RegClassID == FloatRegClassID && reg < 64)
381 return reg + 32; // we have 32 int regs
382 else if( RegClassID == FloatCCRegClassID && reg < 4)
383 return reg + 32 + 64; // 32 int, 64 float
384 else if( RegClassID == IntCCRegClassID )
385 return 4+ 32 + 64; // only int cc reg
386 else if (reg==InvalidRegNum)
387 return InvalidRegNum;
389 assert(0 && "Invalid register class or reg number");
393 // given the unified register number, this gives the name
394 // for generating assembly code or debugging.
396 virtual const std::string getUnifiedRegName(int reg) const;
399 // returns the # of bytes of stack space allocated for each register
400 // type. For Sparc, currently we allocate 8 bytes on stack for all
401 // register types. We can optimize this later if necessary to save stack
402 // space (However, should make sure that stack alignment is correct)
404 inline int getSpilledRegSize(int RegType) const {
409 // To obtain the return value contained in a CALL machine instruction
411 const Value * getCallInstRetVal(const MachineInstr *CallMI) const;
414 // The following methods are used to generate "copy" machine instructions
415 // for an architecture.
417 MachineInstr * cpReg2RegMI(unsigned SrcReg, unsigned DestReg,
420 MachineInstr * cpReg2MemMI(unsigned SrcReg, unsigned DestPtrReg,
421 int Offset, int RegType) const;
423 MachineInstr * cpMem2RegMI(unsigned SrcPtrReg, int Offset,
424 unsigned DestReg, int RegType) const;
426 MachineInstr* cpValue2Value(Value *Src, Value *Dest) const;
429 // To see whether a register is a volatile (i.e., whehter it must be
430 // preserved acorss calls)
432 inline bool isRegVolatile(int RegClassID, int Reg) const {
433 return MachineRegClassArr[RegClassID]->isRegVolatile(Reg);
437 virtual unsigned getFramePointer() const;
438 virtual unsigned getStackPointer() const;
440 virtual int getInvalidRegNum() const {
441 return InvalidRegNum;
444 // This method inserts the caller saving code for call instructions
446 void insertCallerSavingCode(const MachineInstr *MInst,
447 const BasicBlock *BB, PhyRegAlloc &PRA ) const;
453 //---------------------------------------------------------------------------
454 // class UltraSparcSchedInfo
457 // Interface to instruction scheduling information for UltraSPARC.
458 // The parameter values above are based on UltraSPARC IIi.
459 //---------------------------------------------------------------------------
462 class UltraSparcSchedInfo: public MachineSchedInfo {
464 UltraSparcSchedInfo(const TargetMachine &tgt);
466 virtual void initializeResources();
470 //---------------------------------------------------------------------------
471 // class UltraSparcFrameInfo
474 // Interface to stack frame layout info for the UltraSPARC.
475 // Starting offsets for each area of the stack frame are aligned at
476 // a multiple of getStackFrameSizeAlignment().
477 //---------------------------------------------------------------------------
479 class UltraSparcFrameInfo: public MachineFrameInfo {
481 UltraSparcFrameInfo(const TargetMachine &tgt) : MachineFrameInfo(tgt) {}
484 int getStackFrameSizeAlignment () const { return StackFrameSizeAlignment;}
485 int getMinStackFrameSize () const { return MinStackFrameSize; }
486 int getNumFixedOutgoingArgs () const { return NumFixedOutgoingArgs; }
487 int getSizeOfEachArgOnStack () const { return SizeOfEachArgOnStack; }
488 bool argsOnStackHaveFixedSize () const { return true; }
491 // These methods compute offsets using the frame contents for a
492 // particular method. The frame contents are obtained from the
493 // MachineCodeInfoForMethod object for the given method.
495 int getFirstIncomingArgOffset (MachineCodeForMethod& mcInfo,
498 pos = true; // arguments area grows upwards
499 return FirstIncomingArgOffsetFromFP;
501 int getFirstOutgoingArgOffset (MachineCodeForMethod& mcInfo,
504 pos = true; // arguments area grows upwards
505 return FirstOutgoingArgOffsetFromSP;
507 int getFirstOptionalOutgoingArgOffset(MachineCodeForMethod& mcInfo,
510 pos = true; // arguments area grows upwards
511 return FirstOptionalOutgoingArgOffsetFromSP;
514 int getFirstAutomaticVarOffset (MachineCodeForMethod& mcInfo,
516 int getRegSpillAreaOffset (MachineCodeForMethod& mcInfo,
518 int getTmpAreaOffset (MachineCodeForMethod& mcInfo,
520 int getDynamicAreaOffset (MachineCodeForMethod& mcInfo,
524 // These methods specify the base register used for each stack area
525 // (generally FP or SP)
527 virtual int getIncomingArgBaseRegNum() const {
528 return (int) target.getRegInfo().getFramePointer();
530 virtual int getOutgoingArgBaseRegNum() const {
531 return (int) target.getRegInfo().getStackPointer();
533 virtual int getOptionalOutgoingArgBaseRegNum() const {
534 return (int) target.getRegInfo().getStackPointer();
536 virtual int getAutomaticVarBaseRegNum() const {
537 return (int) target.getRegInfo().getFramePointer();
539 virtual int getRegSpillAreaBaseRegNum() const {
540 return (int) target.getRegInfo().getFramePointer();
542 virtual int getDynamicAreaBaseRegNum() const {
543 return (int) target.getRegInfo().getStackPointer();
547 // All stack addresses must be offset by 0x7ff (2047) on Sparc V9.
548 static const int OFFSET = (int) 0x7ff;
549 static const int StackFrameSizeAlignment = 16;
550 static const int MinStackFrameSize = 176;
551 static const int NumFixedOutgoingArgs = 6;
552 static const int SizeOfEachArgOnStack = 8;
553 static const int StaticAreaOffsetFromFP = 0 + OFFSET;
554 static const int FirstIncomingArgOffsetFromFP = 128 + OFFSET;
555 static const int FirstOptionalIncomingArgOffsetFromFP = 176 + OFFSET;
556 static const int FirstOutgoingArgOffsetFromSP = 128 + OFFSET;
557 static const int FirstOptionalOutgoingArgOffsetFromSP = 176 + OFFSET;
561 //---------------------------------------------------------------------------
562 // class UltraSparcCacheInfo
565 // Interface to cache parameters for the UltraSPARC.
566 // Just use defaults for now.
567 //---------------------------------------------------------------------------
569 class UltraSparcCacheInfo: public MachineCacheInfo {
571 UltraSparcCacheInfo(const TargetMachine &T) : MachineCacheInfo(T) {}
575 //---------------------------------------------------------------------------
576 // class UltraSparcMachine
579 // Primary interface to machine description for the UltraSPARC.
580 // Primarily just initializes machine-dependent parameters in
581 // class TargetMachine, and creates machine-dependent subclasses
582 // for classes such as InstrInfo, SchedInfo and RegInfo.
583 //---------------------------------------------------------------------------
585 class UltraSparc : public TargetMachine {
587 UltraSparcInstrInfo instrInfo;
588 UltraSparcSchedInfo schedInfo;
589 UltraSparcRegInfo regInfo;
590 UltraSparcFrameInfo frameInfo;
591 UltraSparcCacheInfo cacheInfo;
595 virtual const MachineInstrInfo &getInstrInfo() const { return instrInfo; }
596 virtual const MachineSchedInfo &getSchedInfo() const { return schedInfo; }
597 virtual const MachineRegInfo &getRegInfo() const { return regInfo; }
598 virtual const MachineFrameInfo &getFrameInfo() const { return frameInfo; }
599 virtual const MachineCacheInfo &getCacheInfo() const { return cacheInfo; }
602 // addPassesToEmitAssembly - Add passes to the specified pass manager to get
603 // assembly langage code emited. For sparc, we have to do ...
605 virtual void addPassesToEmitAssembly(PassManager &PM, std::ostream &Out);
608 Pass *getMethodAsmPrinterPass(PassManager &PM, std::ostream &Out);
609 Pass *getModuleAsmPrinterPass(PassManager &PM, std::ostream &Out);