2 //***************************************************************************
4 // SparcInstrSelection.cpp
7 // BURS instruction selection for SPARC V9 architecture.
10 // 7/02/01 - Vikram Adve - Created
11 //**************************************************************************/
13 #include "SparcInternals.h"
14 #include "SparcInstrSelectionSupport.h"
15 #include "SparcRegClassInfo.h"
16 #include "llvm/CodeGen/InstrSelectionSupport.h"
17 #include "llvm/CodeGen/MachineInstr.h"
18 #include "llvm/CodeGen/InstrForest.h"
19 #include "llvm/CodeGen/InstrSelection.h"
20 #include "llvm/CodeGen/MachineCodeForMethod.h"
21 #include "llvm/CodeGen/MachineCodeForInstruction.h"
22 #include "llvm/DerivedTypes.h"
23 #include "llvm/iTerminators.h"
24 #include "llvm/iMemory.h"
25 #include "llvm/iOther.h"
26 #include "llvm/BasicBlock.h"
27 #include "llvm/Method.h"
28 #include "llvm/ConstantVals.h"
29 #include "Support/MathExtras.h"
33 //************************* Forward Declarations ***************************/
36 static void SetMemOperands_Internal (vector<MachineInstr*>& mvec,
37 vector<MachineInstr*>::iterator mvecI,
38 const InstructionNode* vmInstrNode,
40 std::vector<Value*>& idxVec,
41 const TargetMachine& target);
44 //************************ Internal Functions ******************************/
47 static inline MachineOpCode
48 ChooseBprInstruction(const InstructionNode* instrNode)
52 Instruction* setCCInstr =
53 ((InstructionNode*) instrNode->leftChild())->getInstruction();
55 switch(setCCInstr->getOpcode())
57 case Instruction::SetEQ: opCode = BRZ; break;
58 case Instruction::SetNE: opCode = BRNZ; break;
59 case Instruction::SetLE: opCode = BRLEZ; break;
60 case Instruction::SetGE: opCode = BRGEZ; break;
61 case Instruction::SetLT: opCode = BRLZ; break;
62 case Instruction::SetGT: opCode = BRGZ; break;
64 assert(0 && "Unrecognized VM instruction!");
65 opCode = INVALID_OPCODE;
73 static inline MachineOpCode
74 ChooseBpccInstruction(const InstructionNode* instrNode,
75 const BinaryOperator* setCCInstr)
77 MachineOpCode opCode = INVALID_OPCODE;
79 bool isSigned = setCCInstr->getOperand(0)->getType()->isSigned();
83 switch(setCCInstr->getOpcode())
85 case Instruction::SetEQ: opCode = BE; break;
86 case Instruction::SetNE: opCode = BNE; break;
87 case Instruction::SetLE: opCode = BLE; break;
88 case Instruction::SetGE: opCode = BGE; break;
89 case Instruction::SetLT: opCode = BL; break;
90 case Instruction::SetGT: opCode = BG; break;
92 assert(0 && "Unrecognized VM instruction!");
98 switch(setCCInstr->getOpcode())
100 case Instruction::SetEQ: opCode = BE; break;
101 case Instruction::SetNE: opCode = BNE; break;
102 case Instruction::SetLE: opCode = BLEU; break;
103 case Instruction::SetGE: opCode = BCC; break;
104 case Instruction::SetLT: opCode = BCS; break;
105 case Instruction::SetGT: opCode = BGU; break;
107 assert(0 && "Unrecognized VM instruction!");
115 static inline MachineOpCode
116 ChooseBFpccInstruction(const InstructionNode* instrNode,
117 const BinaryOperator* setCCInstr)
119 MachineOpCode opCode = INVALID_OPCODE;
121 switch(setCCInstr->getOpcode())
123 case Instruction::SetEQ: opCode = FBE; break;
124 case Instruction::SetNE: opCode = FBNE; break;
125 case Instruction::SetLE: opCode = FBLE; break;
126 case Instruction::SetGE: opCode = FBGE; break;
127 case Instruction::SetLT: opCode = FBL; break;
128 case Instruction::SetGT: opCode = FBG; break;
130 assert(0 && "Unrecognized VM instruction!");
138 // Create a unique TmpInstruction for a boolean value,
139 // representing the CC register used by a branch on that value.
140 // For now, hack this using a little static cache of TmpInstructions.
141 // Eventually the entire BURG instruction selection should be put
142 // into a separate class that can hold such information.
143 // The static cache is not too bad because the memory for these
144 // TmpInstructions will be freed along with the rest of the Method anyway.
146 static TmpInstruction*
147 GetTmpForCC(Value* boolVal, const Method* method, const Type* ccType)
149 typedef std::hash_map<const Value*, TmpInstruction*> BoolTmpCache;
150 static BoolTmpCache boolToTmpCache; // Map boolVal -> TmpInstruction*
151 static const Method* lastMethod = NULL; // Use to flush cache between methods
153 assert(boolVal->getType() == Type::BoolTy && "Weird but ok! Delete assert");
155 if (lastMethod != method)
158 boolToTmpCache.clear();
161 // Look for tmpI and create a new one otherwise. The new value is
162 // directly written to map using the ref returned by operator[].
163 TmpInstruction*& tmpI = boolToTmpCache[boolVal];
165 tmpI = new TmpInstruction(ccType, boolVal);
171 static inline MachineOpCode
172 ChooseBccInstruction(const InstructionNode* instrNode,
175 InstructionNode* setCCNode = (InstructionNode*) instrNode->leftChild();
176 BinaryOperator* setCCInstr = (BinaryOperator*) setCCNode->getInstruction();
177 const Type* setCCType = setCCInstr->getOperand(0)->getType();
179 isFPBranch = (setCCType == Type::FloatTy || setCCType == Type::DoubleTy);
182 return ChooseBFpccInstruction(instrNode, setCCInstr);
184 return ChooseBpccInstruction(instrNode, setCCInstr);
188 static inline MachineOpCode
189 ChooseMovFpccInstruction(const InstructionNode* instrNode)
191 MachineOpCode opCode = INVALID_OPCODE;
193 switch(instrNode->getInstruction()->getOpcode())
195 case Instruction::SetEQ: opCode = MOVFE; break;
196 case Instruction::SetNE: opCode = MOVFNE; break;
197 case Instruction::SetLE: opCode = MOVFLE; break;
198 case Instruction::SetGE: opCode = MOVFGE; break;
199 case Instruction::SetLT: opCode = MOVFL; break;
200 case Instruction::SetGT: opCode = MOVFG; break;
202 assert(0 && "Unrecognized VM instruction!");
210 // Assumes that SUBcc v1, v2 -> v3 has been executed.
211 // In most cases, we want to clear v3 and then follow it by instruction
213 // Set mustClearReg=false if v3 need not be cleared before conditional move.
214 // Set valueToMove=0 if we want to conditionally move 0 instead of 1
215 // (i.e., we want to test inverse of a condition)
216 // (The latter two cases do not seem to arise because SetNE needs nothing.)
219 ChooseMovpccAfterSub(const InstructionNode* instrNode,
223 MachineOpCode opCode = INVALID_OPCODE;
227 switch(instrNode->getInstruction()->getOpcode())
229 case Instruction::SetEQ: opCode = MOVE; break;
230 case Instruction::SetLE: opCode = MOVLE; break;
231 case Instruction::SetGE: opCode = MOVGE; break;
232 case Instruction::SetLT: opCode = MOVL; break;
233 case Instruction::SetGT: opCode = MOVG; break;
234 case Instruction::SetNE: assert(0 && "No move required!"); break;
235 default: assert(0 && "Unrecognized VM instr!"); break;
241 static inline MachineOpCode
242 ChooseConvertToFloatInstr(const InstructionNode* instrNode,
245 MachineOpCode opCode = INVALID_OPCODE;
247 switch(instrNode->getOpLabel())
250 if (opType == Type::SByteTy || opType == Type::ShortTy || opType == Type::IntTy)
252 else if (opType == Type::LongTy)
254 else if (opType == Type::DoubleTy)
256 else if (opType == Type::FloatTy)
259 assert(0 && "Cannot convert this type to FLOAT on SPARC");
263 // This is usually used in conjunction with CreateCodeToCopyIntToFloat().
264 // Both functions should treat the integer as a 32-bit value for types
265 // of 4 bytes or less, and as a 64-bit value otherwise.
266 if (opType == Type::SByteTy || opType == Type::UByteTy ||
267 opType == Type::ShortTy || opType == Type::UShortTy ||
268 opType == Type::IntTy || opType == Type::UIntTy)
270 else if (opType == Type::LongTy || opType == Type::ULongTy)
272 else if (opType == Type::FloatTy)
274 else if (opType == Type::DoubleTy)
277 assert(0 && "Cannot convert this type to DOUBLE on SPARC");
287 static inline MachineOpCode
288 ChooseConvertToIntInstr(const InstructionNode* instrNode,
291 MachineOpCode opCode = INVALID_OPCODE;;
293 int instrType = (int) instrNode->getOpLabel();
295 if (instrType == ToSByteTy || instrType == ToShortTy || instrType == ToIntTy)
297 switch (opType->getPrimitiveID())
299 case Type::FloatTyID: opCode = FSTOI; break;
300 case Type::DoubleTyID: opCode = FDTOI; break;
302 assert(0 && "Non-numeric non-bool type cannot be converted to Int");
306 else if (instrType == ToLongTy)
308 switch (opType->getPrimitiveID())
310 case Type::FloatTyID: opCode = FSTOX; break;
311 case Type::DoubleTyID: opCode = FDTOX; break;
313 assert(0 && "Non-numeric non-bool type cannot be converted to Long");
318 assert(0 && "Should not get here, Mo!");
324 static inline MachineOpCode
325 ChooseAddInstructionByType(const Type* resultType)
327 MachineOpCode opCode = INVALID_OPCODE;
329 if (resultType->isIntegral() ||
330 isa<PointerType>(resultType) ||
331 isa<FunctionType>(resultType) ||
332 resultType == Type::LabelTy ||
333 resultType == Type::BoolTy)
338 switch(resultType->getPrimitiveID())
340 case Type::FloatTyID: opCode = FADDS; break;
341 case Type::DoubleTyID: opCode = FADDD; break;
342 default: assert(0 && "Invalid type for ADD instruction"); break;
349 static inline MachineOpCode
350 ChooseAddInstruction(const InstructionNode* instrNode)
352 return ChooseAddInstructionByType(instrNode->getInstruction()->getType());
356 static inline MachineInstr*
357 CreateMovFloatInstruction(const InstructionNode* instrNode,
358 const Type* resultType)
360 MachineInstr* minstr = new MachineInstr((resultType == Type::FloatTy)
362 minstr->SetMachineOperandVal(0, MachineOperand::MO_VirtualRegister,
363 instrNode->leftChild()->getValue());
364 minstr->SetMachineOperandVal(1, MachineOperand::MO_VirtualRegister,
365 instrNode->getValue());
369 static inline MachineInstr*
370 CreateAddConstInstruction(const InstructionNode* instrNode)
372 MachineInstr* minstr = NULL;
374 Value* constOp = ((InstrTreeNode*) instrNode->rightChild())->getValue();
375 assert(isa<Constant>(constOp));
377 // Cases worth optimizing are:
378 // (1) Add with 0 for float or double: use an FMOV of appropriate type,
379 // instead of an FADD (1 vs 3 cycles). There is no integer MOV.
381 const Type* resultType = instrNode->getInstruction()->getType();
383 if (resultType == Type::FloatTy ||
384 resultType == Type::DoubleTy)
386 double dval = cast<ConstantFP>(constOp)->getValue();
388 minstr = CreateMovFloatInstruction(instrNode, resultType);
395 static inline MachineOpCode
396 ChooseSubInstructionByType(const Type* resultType)
398 MachineOpCode opCode = INVALID_OPCODE;
400 if (resultType->isIntegral() ||
401 resultType->isPointerType())
406 switch(resultType->getPrimitiveID())
408 case Type::FloatTyID: opCode = FSUBS; break;
409 case Type::DoubleTyID: opCode = FSUBD; break;
410 default: assert(0 && "Invalid type for SUB instruction"); break;
417 static inline MachineInstr*
418 CreateSubConstInstruction(const InstructionNode* instrNode)
420 MachineInstr* minstr = NULL;
422 Value* constOp = ((InstrTreeNode*) instrNode->rightChild())->getValue();
423 assert(isa<Constant>(constOp));
425 // Cases worth optimizing are:
426 // (1) Sub with 0 for float or double: use an FMOV of appropriate type,
427 // instead of an FSUB (1 vs 3 cycles). There is no integer MOV.
429 const Type* resultType = instrNode->getInstruction()->getType();
431 if (resultType == Type::FloatTy ||
432 resultType == Type::DoubleTy)
434 double dval = cast<ConstantFP>(constOp)->getValue();
436 minstr = CreateMovFloatInstruction(instrNode, resultType);
443 static inline MachineOpCode
444 ChooseFcmpInstruction(const InstructionNode* instrNode)
446 MachineOpCode opCode = INVALID_OPCODE;
448 Value* operand = ((InstrTreeNode*) instrNode->leftChild())->getValue();
449 switch(operand->getType()->getPrimitiveID()) {
450 case Type::FloatTyID: opCode = FCMPS; break;
451 case Type::DoubleTyID: opCode = FCMPD; break;
452 default: assert(0 && "Invalid type for FCMP instruction"); break;
459 // Assumes that leftArg and rightArg are both cast instructions.
462 BothFloatToDouble(const InstructionNode* instrNode)
464 InstrTreeNode* leftArg = instrNode->leftChild();
465 InstrTreeNode* rightArg = instrNode->rightChild();
466 InstrTreeNode* leftArgArg = leftArg->leftChild();
467 InstrTreeNode* rightArgArg = rightArg->leftChild();
468 assert(leftArg->getValue()->getType() == rightArg->getValue()->getType());
470 // Check if both arguments are floats cast to double
471 return (leftArg->getValue()->getType() == Type::DoubleTy &&
472 leftArgArg->getValue()->getType() == Type::FloatTy &&
473 rightArgArg->getValue()->getType() == Type::FloatTy);
477 static inline MachineOpCode
478 ChooseMulInstructionByType(const Type* resultType)
480 MachineOpCode opCode = INVALID_OPCODE;
482 if (resultType->isIntegral())
485 switch(resultType->getPrimitiveID())
487 case Type::FloatTyID: opCode = FMULS; break;
488 case Type::DoubleTyID: opCode = FMULD; break;
489 default: assert(0 && "Invalid type for MUL instruction"); break;
497 static inline MachineInstr*
498 CreateIntNegInstruction(const TargetMachine& target,
501 MachineInstr* minstr = new MachineInstr(SUB);
502 minstr->SetMachineOperandReg(0, target.getRegInfo().getZeroRegNum());
503 minstr->SetMachineOperandVal(1, MachineOperand::MO_VirtualRegister, vreg);
504 minstr->SetMachineOperandVal(2, MachineOperand::MO_VirtualRegister, vreg);
509 // Does not create any instructions if we cannot exploit constant to
510 // create a cheaper instruction.
511 // This returns the approximate cost of the instructions generated,
512 // which is used to pick the cheapest when both operands are constant.
513 static inline unsigned int
514 CreateMulConstInstruction(const TargetMachine &target,
515 Value* lval, Value* rval, Value* destVal,
516 vector<MachineInstr*>& mvec)
518 /* An integer multiply is generally more costly than FP multiply */
519 unsigned int cost = target.getInstrInfo().minLatency(MULX);
520 MachineInstr* minstr1 = NULL;
521 MachineInstr* minstr2 = NULL;
523 Value* constOp = rval;
524 if (! isa<Constant>(constOp))
527 // Cases worth optimizing are:
528 // (1) Multiply by 0 or 1 for any type: replace with copy (ADD or FMOV)
529 // (2) Multiply by 2^x for integer types: replace with Shift
531 const Type* resultType = destVal->getType();
533 if (resultType->isIntegral() || resultType->isPointerType())
537 int64_t C = GetConstantValueAsSignedInt(constOp, isValidConst);
540 bool needNeg = false;
547 if (C == 0 || C == 1)
549 cost = target.getInstrInfo().minLatency(ADD);
550 minstr1 = new MachineInstr(ADD);
552 minstr1->SetMachineOperandReg(0,
553 target.getRegInfo().getZeroRegNum());
555 minstr1->SetMachineOperandVal(0,
556 MachineOperand::MO_VirtualRegister, lval);
557 minstr1->SetMachineOperandReg(1,
558 target.getRegInfo().getZeroRegNum());
560 else if (IsPowerOf2(C, pow))
562 minstr1 = new MachineInstr((resultType == Type::LongTy)
564 minstr1->SetMachineOperandVal(0,
565 MachineOperand::MO_VirtualRegister, lval);
566 minstr1->SetMachineOperandConst(1,
567 MachineOperand::MO_UnextendedImmed, pow);
570 if (minstr1 && needNeg)
571 { // insert <reg = SUB 0, reg> after the instr to flip the sign
572 minstr2 = CreateIntNegInstruction(target, destVal);
573 cost += target.getInstrInfo().minLatency(minstr2->getOpCode());
579 if (resultType == Type::FloatTy ||
580 resultType == Type::DoubleTy)
582 double dval = cast<ConstantFP>(constOp)->getValue();
585 bool needNeg = (dval < 0);
587 MachineOpCode opCode = needNeg
588 ? (resultType == Type::FloatTy? FNEGS : FNEGD)
589 : (resultType == Type::FloatTy? FMOVS : FMOVD);
591 minstr1 = new MachineInstr(opCode);
592 minstr1->SetMachineOperandVal(0,
593 MachineOperand::MO_VirtualRegister,
600 minstr1->SetMachineOperandVal(2, MachineOperand::MO_VirtualRegister,
605 mvec.push_back(minstr1);
606 cost = target.getInstrInfo().minLatency(minstr1->getOpCode());
610 assert(minstr1 && "Otherwise cost needs to be initialized to 0");
611 cost += target.getInstrInfo().minLatency(minstr2->getOpCode());
612 mvec.push_back(minstr2);
619 // Does not create any instructions if we cannot exploit constant to
620 // create a cheaper instruction.
623 CreateCheapestMulConstInstruction(const TargetMachine &target,
624 Value* lval, Value* rval, Value* destVal,
625 vector<MachineInstr*>& mvec)
628 if (isa<Constant>(lval) && isa<Constant>(rval))
629 { // both operands are constant: try both orders!
630 vector<MachineInstr*> mvec1, mvec2;
631 unsigned int lcost = CreateMulConstInstruction(target, lval, rval,
633 unsigned int rcost = CreateMulConstInstruction(target, rval, lval,
635 vector<MachineInstr*>& mincostMvec = (lcost <= rcost)? mvec1 : mvec2;
636 vector<MachineInstr*>& maxcostMvec = (lcost <= rcost)? mvec2 : mvec1;
637 mvec.insert(mvec.end(), mincostMvec.begin(), mincostMvec.end());
639 for (unsigned int i=0; i < maxcostMvec.size(); ++i)
640 delete maxcostMvec[i];
642 else if (isa<Constant>(rval)) // rval is constant, but not lval
643 CreateMulConstInstruction(target, lval, rval, destVal, mvec);
644 else if (isa<Constant>(lval)) // lval is constant, but not rval
645 CreateMulConstInstruction(target, lval, rval, destVal, mvec);
647 // else neither is constant
651 // Return NULL if we cannot exploit constant to create a cheaper instruction
653 CreateMulInstruction(const TargetMachine &target,
654 Value* lval, Value* rval, Value* destVal,
655 vector<MachineInstr*>& mvec,
656 MachineOpCode forceMulOp = INVALID_MACHINE_OPCODE)
658 unsigned int L = mvec.size();
659 CreateCheapestMulConstInstruction(target, lval, rval, destVal, mvec);
660 if (mvec.size() == L)
661 { // no instructions were added so create MUL reg, reg, reg.
662 // Use FSMULD if both operands are actually floats cast to doubles.
663 // Otherwise, use the default opcode for the appropriate type.
664 MachineOpCode mulOp = ((forceMulOp != INVALID_MACHINE_OPCODE)
666 : ChooseMulInstructionByType(destVal->getType()));
667 MachineInstr* M = new MachineInstr(mulOp);
668 M->SetMachineOperandVal(0, MachineOperand::MO_VirtualRegister, lval);
669 M->SetMachineOperandVal(1, MachineOperand::MO_VirtualRegister, rval);
670 M->SetMachineOperandVal(2, MachineOperand::MO_VirtualRegister, destVal);
676 // Generate a divide instruction for Div or Rem.
677 // For Rem, this assumes that the operand type will be signed if the result
678 // type is signed. This is correct because they must have the same sign.
680 static inline MachineOpCode
681 ChooseDivInstruction(TargetMachine &target,
682 const InstructionNode* instrNode)
684 MachineOpCode opCode = INVALID_OPCODE;
686 const Type* resultType = instrNode->getInstruction()->getType();
688 if (resultType->isIntegral())
689 opCode = resultType->isSigned()? SDIVX : UDIVX;
691 switch(resultType->getPrimitiveID())
693 case Type::FloatTyID: opCode = FDIVS; break;
694 case Type::DoubleTyID: opCode = FDIVD; break;
695 default: assert(0 && "Invalid type for DIV instruction"); break;
702 // Return NULL if we cannot exploit constant to create a cheaper instruction
704 CreateDivConstInstruction(TargetMachine &target,
705 const InstructionNode* instrNode,
706 vector<MachineInstr*>& mvec)
708 MachineInstr* minstr1 = NULL;
709 MachineInstr* minstr2 = NULL;
711 Value* constOp = ((InstrTreeNode*) instrNode->rightChild())->getValue();
712 if (! isa<Constant>(constOp))
715 // Cases worth optimizing are:
716 // (1) Divide by 1 for any type: replace with copy (ADD or FMOV)
717 // (2) Divide by 2^x for integer types: replace with SR[L or A]{X}
719 const Type* resultType = instrNode->getInstruction()->getType();
721 if (resultType->isIntegral())
725 int64_t C = GetConstantValueAsSignedInt(constOp, isValidConst);
728 bool needNeg = false;
737 minstr1 = new MachineInstr(ADD);
738 minstr1->SetMachineOperandVal(0,
739 MachineOperand::MO_VirtualRegister,
740 instrNode->leftChild()->getValue());
741 minstr1->SetMachineOperandReg(1,
742 target.getRegInfo().getZeroRegNum());
744 else if (IsPowerOf2(C, pow))
746 MachineOpCode opCode= ((resultType->isSigned())
747 ? (resultType==Type::LongTy)? SRAX : SRA
748 : (resultType==Type::LongTy)? SRLX : SRL);
749 minstr1 = new MachineInstr(opCode);
750 minstr1->SetMachineOperandVal(0,
751 MachineOperand::MO_VirtualRegister,
752 instrNode->leftChild()->getValue());
753 minstr1->SetMachineOperandConst(1,
754 MachineOperand::MO_UnextendedImmed,
758 if (minstr1 && needNeg)
759 { // insert <reg = SUB 0, reg> after the instr to flip the sign
760 minstr2 = CreateIntNegInstruction(target,
761 instrNode->getValue());
767 if (resultType == Type::FloatTy ||
768 resultType == Type::DoubleTy)
770 double dval = cast<ConstantFP>(constOp)->getValue();
773 bool needNeg = (dval < 0);
775 MachineOpCode opCode = needNeg
776 ? (resultType == Type::FloatTy? FNEGS : FNEGD)
777 : (resultType == Type::FloatTy? FMOVS : FMOVD);
779 minstr1 = new MachineInstr(opCode);
780 minstr1->SetMachineOperandVal(0,
781 MachineOperand::MO_VirtualRegister,
782 instrNode->leftChild()->getValue());
788 minstr1->SetMachineOperandVal(2, MachineOperand::MO_VirtualRegister,
789 instrNode->getValue());
792 mvec.push_back(minstr1);
794 mvec.push_back(minstr2);
799 CreateCodeForVariableSizeAlloca(const TargetMachine& target,
802 Value* numElementsVal,
803 vector<MachineInstr*>& getMvec)
807 // Create a Value to hold the (constant) element size
808 Value* tsizeVal = ConstantSInt::get(Type::IntTy, tsize);
810 // Get the constant offset from SP for dynamically allocated storage
811 // and create a temporary Value to hold it.
812 assert(result && result->getParent() && "Result value is not part of a method?");
813 Method* method = result->getParent()->getParent();
814 MachineCodeForMethod& mcInfo = MachineCodeForMethod::get(method);
816 ConstantSInt* dynamicAreaOffset =
817 ConstantSInt::get(Type::IntTy,
818 target.getFrameInfo().getDynamicAreaOffset(mcInfo,growUp));
819 assert(! growUp && "Has SPARC v9 stack frame convention changed?");
821 // Create a temporary value to hold the result of MUL
822 TmpInstruction* tmpProd = new TmpInstruction(numElementsVal, tsizeVal);
823 MachineCodeForInstruction::get(result).addTemp(tmpProd);
825 // Instruction 1: mul numElements, typeSize -> tmpProd
826 M = new MachineInstr(MULX);
827 M->SetMachineOperandVal(0, MachineOperand::MO_VirtualRegister, numElementsVal);
828 M->SetMachineOperandVal(1, MachineOperand::MO_VirtualRegister, tsizeVal);
829 M->SetMachineOperandVal(2, MachineOperand::MO_VirtualRegister, tmpProd);
830 getMvec.push_back(M);
832 // Instruction 2: sub %sp, tmpProd -> %sp
833 M = new MachineInstr(SUB);
834 M->SetMachineOperandReg(0, target.getRegInfo().getStackPointer());
835 M->SetMachineOperandVal(1, MachineOperand::MO_VirtualRegister, tmpProd);
836 M->SetMachineOperandReg(2, target.getRegInfo().getStackPointer());
837 getMvec.push_back(M);
839 // Instruction 3: add %sp, frameSizeBelowDynamicArea -> result
840 M = new MachineInstr(ADD);
841 M->SetMachineOperandReg(0, target.getRegInfo().getStackPointer());
842 M->SetMachineOperandVal(1, MachineOperand::MO_VirtualRegister, dynamicAreaOffset);
843 M->SetMachineOperandVal(2, MachineOperand::MO_VirtualRegister, result);
844 getMvec.push_back(M);
849 CreateCodeForFixedSizeAlloca(const TargetMachine& target,
852 unsigned int numElements,
853 vector<MachineInstr*>& getMvec)
855 assert(result && result->getParent() &&
856 "Result value is not part of a method?");
857 Method* method = result->getParent()->getParent();
858 MachineCodeForMethod& mcInfo = MachineCodeForMethod::get(method);
860 // Check if the offset would small enough to use as an immediate in load/stores
861 // (check LDX because all load/stores have the same-size immediate field).
862 // If not, put the variable in the dynamically sized area of the frame.
863 unsigned int paddedSizeIgnored;
864 int offsetFromFP = mcInfo.computeOffsetforLocalVar(target, result,
866 tsize * numElements);
867 if (! target.getInstrInfo().constantFitsInImmedField(LDX, offsetFromFP))
869 CreateCodeForVariableSizeAlloca(target, result, tsize,
870 ConstantSInt::get(Type::IntTy,numElements),
875 // else offset fits in immediate field so go ahead and allocate it.
876 offsetFromFP = mcInfo.allocateLocalVar(target, result, tsize * numElements);
878 // Create a temporary Value to hold the constant offset.
879 // This is needed because it may not fit in the immediate field.
880 ConstantSInt* offsetVal = ConstantSInt::get(Type::IntTy, offsetFromFP);
882 // Instruction 1: add %fp, offsetFromFP -> result
883 MachineInstr* M = new MachineInstr(ADD);
884 M->SetMachineOperandReg(0, target.getRegInfo().getFramePointer());
885 M->SetMachineOperandVal(1, MachineOperand::MO_VirtualRegister, offsetVal);
886 M->SetMachineOperandVal(2, MachineOperand::MO_VirtualRegister, result);
888 getMvec.push_back(M);
893 //------------------------------------------------------------------------
894 // Function SetOperandsForMemInstr
896 // Choose addressing mode for the given load or store instruction.
897 // Use [reg+reg] if it is an indexed reference, and the index offset is
898 // not a constant or if it cannot fit in the offset field.
899 // Use [reg+offset] in all other cases.
901 // This assumes that all array refs are "lowered" to one of these forms:
902 // %x = load (subarray*) ptr, constant ; single constant offset
903 // %x = load (subarray*) ptr, offsetVal ; single non-constant offset
904 // Generally, this should happen via strength reduction + LICM.
905 // Also, strength reduction should take care of using the same register for
906 // the loop index variable and an array index, when that is profitable.
907 //------------------------------------------------------------------------
910 SetOperandsForMemInstr(vector<MachineInstr*>& mvec,
911 vector<MachineInstr*>::iterator mvecI,
912 const InstructionNode* vmInstrNode,
913 const TargetMachine& target)
915 MemAccessInst* memInst = (MemAccessInst*) vmInstrNode->getInstruction();
917 // Variables to hold the index vector, ptr value, and offset value.
918 // The major work here is to extract these for all 3 instruction types
919 // and then call the common function SetMemOperands_Internal().
921 Value* ptrVal = memInst->getPointerOperand();
923 // Start with the index vector of this instruction, if any.
924 vector<Value*> idxVec;
925 idxVec.insert(idxVec.end(), memInst->idx_begin(), memInst->idx_end());
927 // If there is a GetElemPtr instruction to fold in to this instr,
928 // it must be in the left child for Load and GetElemPtr, and in the
929 // right child for Store instructions.
930 InstrTreeNode* ptrChild = (vmInstrNode->getOpLabel() == Instruction::Store
931 ? vmInstrNode->rightChild()
932 : vmInstrNode->leftChild());
934 // Fold chains of GetElemPtr instructions for structure references.
935 if (isa<StructType>(cast<PointerType>(ptrVal->getType())->getElementType())
936 && (ptrChild->getOpLabel() == Instruction::GetElementPtr ||
937 ptrChild->getOpLabel() == GetElemPtrIdx))
939 Value* newPtr = FoldGetElemChain((InstructionNode*) ptrChild, idxVec);
944 SetMemOperands_Internal(mvec, mvecI, vmInstrNode, ptrVal, idxVec, target);
948 // Generate the correct operands (and additional instructions if needed)
949 // for the given pointer and given index vector.
952 SetMemOperands_Internal(vector<MachineInstr*>& mvec,
953 vector<MachineInstr*>::iterator mvecI,
954 const InstructionNode* vmInstrNode,
956 vector<Value*>& idxVec,
957 const TargetMachine& target)
959 MemAccessInst* memInst = (MemAccessInst*) vmInstrNode->getInstruction();
961 // Initialize so we default to storing the offset in a register.
962 int64_t smallConstOffset = 0;
963 Value* valueForRegOffset = NULL;
964 MachineOperand::MachineOperandType offsetOpType =MachineOperand::MO_VirtualRegister;
966 // Check if there is an index vector and if so, compute the
967 // right offset for structures and for arrays
969 if (idxVec.size() > 0)
973 const PointerType* ptrType = cast<PointerType>(ptrVal->getType());
975 // Handle special common case of leading [0] index.
976 bool firstIndexIsZero =
977 bool(isa<ConstantUInt>(idxVec.front()) &&
978 cast<ConstantUInt>(idxVec.front())->getValue() == 0);
980 // This is a real structure reference if the ptr target is a
981 // structure type, and the first offset is [0] (eliminate that offset).
982 if (firstIndexIsZero && ptrType->getElementType()->isStructType())
984 // Compute the offset value using the index vector. Create a
985 // virtual reg. for it since it may not fit in the immed field.
986 assert(idxVec.size() >= 2);
987 idxVec.erase(idxVec.begin());
988 unsigned offset = target.DataLayout.getIndexedOffset(ptrType,idxVec);
989 valueForRegOffset = ConstantSInt::get(Type::IntTy, offset);
993 // It is an array ref, and must have been lowered to a single offset.
994 assert((memInst->getNumOperands()
995 == (unsigned) 1 + memInst->getFirstIndexOperandNumber())
996 && "Array refs must be lowered before Instruction Selection");
998 Value* arrayOffsetVal = * memInst->idx_begin();
1000 // If index is 0, the offset value is just 0. Otherwise,
1001 // generate a MUL instruction to compute address from index.
1002 // The call to getTypeSize() will fail if size is not constant.
1003 // CreateMulInstruction() folds constants intelligently enough.
1005 if (firstIndexIsZero)
1007 offsetOpType = MachineOperand::MO_SignExtendedImmed;
1008 smallConstOffset = 0;
1012 vector<MachineInstr*> mulVec;
1013 Instruction* addr = new TmpInstruction(Type::UIntTy, memInst);
1014 MachineCodeForInstruction::get(memInst).addTemp(addr);
1016 unsigned int eltSize =
1017 target.DataLayout.getTypeSize(ptrType->getElementType());
1018 assert(eltSize > 0 && "Invalid or non-const array element size");
1019 ConstantUInt* eltVal = ConstantUInt::get(Type::UIntTy, eltSize);
1021 CreateMulInstruction(target,
1022 arrayOffsetVal, /* lval, not likely const */
1023 eltVal, /* rval, likely constant */
1025 mulVec, INVALID_MACHINE_OPCODE);
1026 assert(mulVec.size() > 0 && "No multiply instruction created?");
1027 for (vector<MachineInstr*>::const_iterator I = mulVec.begin();
1028 I != mulVec.end(); ++I)
1030 mvecI = mvec.insert(mvecI, *I); // ptr to inserted value
1031 ++mvecI; // ptr to mem. instr.
1034 valueForRegOffset = addr;
1040 offsetOpType = MachineOperand::MO_SignExtendedImmed;
1041 smallConstOffset = 0;
1045 // Operand 0 is value, operand 1 is ptr, operand 2 is offset
1046 // For LOAD or GET_ELEMENT_PTR,
1047 // Operand 0 is ptr, operand 1 is offset, operand 2 is result.
1049 unsigned offsetOpNum, ptrOpNum;
1050 if (memInst->getOpcode() == Instruction::Store)
1052 (*mvecI)->SetMachineOperandVal(0, MachineOperand::MO_VirtualRegister,
1053 vmInstrNode->leftChild()->getValue());
1061 (*mvecI)->SetMachineOperandVal(2, MachineOperand::MO_VirtualRegister,
1065 (*mvecI)->SetMachineOperandVal(ptrOpNum, MachineOperand::MO_VirtualRegister,
1068 if (offsetOpType == MachineOperand::MO_VirtualRegister)
1070 assert(valueForRegOffset != NULL);
1071 (*mvecI)->SetMachineOperandVal(offsetOpNum, offsetOpType,
1075 (*mvecI)->SetMachineOperandConst(offsetOpNum, offsetOpType,
1081 // Substitute operand `operandNum' of the instruction in node `treeNode'
1082 // in place of the use(s) of that instruction in node `parent'.
1083 // Check both explicit and implicit operands!
1084 // Also make sure to skip over a parent who:
1085 // (1) is a list node in the Burg tree, or
1086 // (2) itself had its results forwarded to its parent
1089 ForwardOperand(InstructionNode* treeNode,
1090 InstrTreeNode* parent,
1093 assert(treeNode && parent && "Invalid invocation of ForwardOperand");
1095 Instruction* unusedOp = treeNode->getInstruction();
1096 Value* fwdOp = unusedOp->getOperand(operandNum);
1098 // The parent itself may be a list node, so find the real parent instruction
1099 while (parent->getNodeType() != InstrTreeNode::NTInstructionNode)
1101 parent = parent->parent();
1102 assert(parent && "ERROR: Non-instruction node has no parent in tree.");
1104 InstructionNode* parentInstrNode = (InstructionNode*) parent;
1106 Instruction* userInstr = parentInstrNode->getInstruction();
1107 MachineCodeForInstruction &mvec = MachineCodeForInstruction::get(userInstr);
1109 // The parent's mvec would be empty if it was itself forwarded.
1110 // Recursively call ForwardOperand in that case...
1112 if (mvec.size() == 0)
1114 assert(parent->parent() != NULL &&
1115 "Parent could not have been forwarded, yet has no instructions?");
1116 ForwardOperand(treeNode, parent->parent(), operandNum);
1120 bool fwdSuccessful = false;
1121 for (unsigned i=0, N=mvec.size(); i < N; i++)
1123 MachineInstr* minstr = mvec[i];
1124 for (unsigned i=0, numOps=minstr->getNumOperands(); i < numOps; ++i)
1126 const MachineOperand& mop = minstr->getOperand(i);
1127 if (mop.getOperandType() == MachineOperand::MO_VirtualRegister &&
1128 mop.getVRegValue() == unusedOp)
1130 minstr->SetMachineOperandVal(i,
1131 MachineOperand::MO_VirtualRegister, fwdOp);
1132 fwdSuccessful = true;
1136 for (unsigned i=0,numOps=minstr->getNumImplicitRefs(); i<numOps; ++i)
1137 if (minstr->getImplicitRef(i) == unusedOp)
1139 minstr->setImplicitRef(i, fwdOp,
1140 minstr->implicitRefIsDefined(i));
1141 fwdSuccessful = true;
1144 assert(fwdSuccessful && "Value to be forwarded is never used!");
1149 void UltraSparcInstrInfo::
1150 CreateCopyInstructionsByType(const TargetMachine& target,
1154 vector<MachineInstr*>& minstrVec) const
1156 bool loadConstantToReg = false;
1158 const Type* resultType = dest->getType();
1160 MachineOpCode opCode = ChooseAddInstructionByType(resultType);
1161 if (opCode == INVALID_OPCODE)
1163 assert(0 && "Unsupported result type in CreateCopyInstructionsByType()");
1167 // if `src' is a constant that doesn't fit in the immed field or if it is
1168 // a global variable (i.e., a constant address), generate a load
1169 // instruction instead of an add
1171 if (isa<Constant>(src))
1173 unsigned int machineRegNum;
1175 MachineOperand::MachineOperandType opType =
1176 ChooseRegOrImmed(src, opCode, target, /*canUseImmed*/ true,
1177 machineRegNum, immedValue);
1179 if (opType == MachineOperand::MO_VirtualRegister)
1180 loadConstantToReg = true;
1182 else if (isa<GlobalValue>(src))
1183 loadConstantToReg = true;
1185 if (loadConstantToReg)
1186 { // `src' is constant and cannot fit in immed field for the ADD
1187 // Insert instructions to "load" the constant into a register
1188 vector<TmpInstruction*> tempVec;
1189 target.getInstrInfo().CreateCodeToLoadConst(method, src, dest,
1191 for (unsigned i=0; i < tempVec.size(); i++)
1192 MachineCodeForInstruction::get(dest).addTemp(tempVec[i]);
1195 { // Create an add-with-0 instruction of the appropriate type.
1196 // Make `src' the second operand, in case it is a constant
1197 // Use (unsigned long) 0 for a NULL pointer value.
1199 const Type* zeroValueType =
1200 (resultType->getPrimitiveID() == Type::PointerTyID)? Type::ULongTy
1202 MachineInstr* minstr = new MachineInstr(opCode);
1203 minstr->SetMachineOperandVal(0, MachineOperand::MO_VirtualRegister,
1204 Constant::getNullConstant(zeroValueType));
1205 minstr->SetMachineOperandVal(1, MachineOperand::MO_VirtualRegister, src);
1206 minstr->SetMachineOperandVal(2, MachineOperand::MO_VirtualRegister,dest);
1207 minstrVec.push_back(minstr);
1213 //******************* Externally Visible Functions *************************/
1216 //------------------------------------------------------------------------
1217 // External Function: GetInstructionsForProlog
1218 // External Function: GetInstructionsForEpilog
1221 // Create prolog and epilog code for procedure entry and exit
1222 //------------------------------------------------------------------------
1225 GetInstructionsForProlog(BasicBlock* entryBB,
1226 TargetMachine &target,
1227 MachineInstr** mvec)
1230 const MachineFrameInfo& frameInfo = target.getFrameInfo();
1233 // The second operand is the stack size. If it does not fit in the
1234 // immediate field, we have to use a free register to hold the size.
1235 // We will assume that local register `l0' is unused since the SAVE
1236 // instruction must be the first instruction in each procedure.
1238 Method* method = entryBB->getParent();
1239 MachineCodeForMethod& mcInfo = MachineCodeForMethod::get(method);
1240 unsigned int staticStackSize = mcInfo.getStaticStackSize();
1242 if (staticStackSize < (unsigned) frameInfo.getMinStackFrameSize())
1243 staticStackSize = (unsigned) frameInfo.getMinStackFrameSize();
1245 if (unsigned padsz = (staticStackSize %
1246 (unsigned) frameInfo.getStackFrameSizeAlignment()))
1247 staticStackSize += frameInfo.getStackFrameSizeAlignment() - padsz;
1249 if (target.getInstrInfo().constantFitsInImmedField(SAVE, staticStackSize))
1251 M = new MachineInstr(SAVE);
1252 M->SetMachineOperandReg(0, target.getRegInfo().getStackPointer());
1253 M->SetMachineOperandConst(1, MachineOperand::MO_SignExtendedImmed,
1254 - (int) staticStackSize);
1255 M->SetMachineOperandReg(2, target.getRegInfo().getStackPointer());
1260 M = new MachineInstr(SETSW);
1261 M->SetMachineOperandConst(0, MachineOperand::MO_SignExtendedImmed,
1262 - (int) staticStackSize);
1263 M->SetMachineOperandReg(1, MachineOperand::MO_MachineRegister,
1264 target.getRegInfo().getUnifiedRegNum(
1265 target.getRegInfo().getRegClassIDOfType(Type::IntTy),
1266 SparcIntRegOrder::l0));
1269 M = new MachineInstr(SAVE);
1270 M->SetMachineOperandReg(0, target.getRegInfo().getStackPointer());
1271 M->SetMachineOperandReg(1, MachineOperand::MO_MachineRegister,
1272 target.getRegInfo().getUnifiedRegNum(
1273 target.getRegInfo().getRegClassIDOfType(Type::IntTy),
1274 SparcIntRegOrder::l0));
1275 M->SetMachineOperandReg(2, target.getRegInfo().getStackPointer());
1284 GetInstructionsForEpilog(BasicBlock* anExitBB,
1285 TargetMachine &target,
1286 MachineInstr** mvec)
1288 mvec[0] = new MachineInstr(RESTORE);
1289 mvec[0]->SetMachineOperandReg(0, target.getRegInfo().getZeroRegNum());
1290 mvec[0]->SetMachineOperandConst(1, MachineOperand::MO_SignExtendedImmed,
1292 mvec[0]->SetMachineOperandReg(2, target.getRegInfo().getZeroRegNum());
1298 //------------------------------------------------------------------------
1299 // External Function: ThisIsAChainRule
1302 // Check if a given BURG rule is a chain rule.
1303 //------------------------------------------------------------------------
1306 ThisIsAChainRule(int eruleno)
1310 case 111: // stmt: reg
1311 case 113: // stmt: bool
1334 return false; break;
1339 //------------------------------------------------------------------------
1340 // External Function: GetInstructionsByRule
1343 // Choose machine instructions for the SPARC according to the
1344 // patterns chosen by the BURG-generated parser.
1345 //------------------------------------------------------------------------
1348 GetInstructionsByRule(InstructionNode* subtreeRoot,
1351 TargetMachine &target,
1352 vector<MachineInstr*>& mvec)
1354 bool checkCast = false; // initialize here to use fall-through
1356 int forwardOperandNum = -1;
1357 unsigned int allocaSize = 0;
1358 MachineInstr* M, *M2;
1363 // If the code for this instruction was folded into the parent (user),
1365 if (subtreeRoot->isFoldedIntoParent())
1369 // Let's check for chain rules outside the switch so that we don't have
1370 // to duplicate the list of chain rule production numbers here again
1372 if (ThisIsAChainRule(ruleForNode))
1374 // Chain rules have a single nonterminal on the RHS.
1375 // Get the rule that matches the RHS non-terminal and use that instead.
1377 assert(nts[0] && ! nts[1]
1378 && "A chain rule should have only one RHS non-terminal!");
1379 nextRule = burm_rule(subtreeRoot->state, nts[0]);
1380 nts = burm_nts[nextRule];
1381 GetInstructionsByRule(subtreeRoot, nextRule, nts, target, mvec);
1385 switch(ruleForNode) {
1386 case 1: // stmt: Ret
1387 case 2: // stmt: RetValue(reg)
1388 { // NOTE: Prepass of register allocation is responsible
1389 // for moving return value to appropriate register.
1390 // Mark the return-address register as a hidden virtual reg.
1391 // Mark the return value register as an implicit ref of
1392 // the machine instruction.
1393 // Finally put a NOP in the delay slot.
1394 ReturnInst *returnInstr =
1395 cast<ReturnInst>(subtreeRoot->getInstruction());
1396 assert(returnInstr->getOpcode() == Instruction::Ret);
1398 Instruction* returnReg = new TmpInstruction(returnInstr);
1399 MachineCodeForInstruction::get(returnInstr).addTemp(returnReg);
1401 M = new MachineInstr(JMPLRET);
1402 M->SetMachineOperandReg(0, MachineOperand::MO_VirtualRegister,
1404 M->SetMachineOperandConst(1,MachineOperand::MO_SignExtendedImmed,
1406 M->SetMachineOperandReg(2, target.getRegInfo().getZeroRegNum());
1408 if (returnInstr->getReturnValue() != NULL)
1409 M->addImplicitRef(returnInstr->getReturnValue());
1412 mvec.push_back(new MachineInstr(NOP));
1417 case 3: // stmt: Store(reg,reg)
1418 case 4: // stmt: Store(reg,ptrreg)
1419 mvec.push_back(new MachineInstr(
1420 ChooseStoreInstruction(
1421 subtreeRoot->leftChild()->getValue()->getType())));
1422 SetOperandsForMemInstr(mvec, mvec.end()-1, subtreeRoot, target);
1425 case 5: // stmt: BrUncond
1426 M = new MachineInstr(BA);
1427 M->SetMachineOperandVal(0, MachineOperand::MO_CCRegister,
1429 M->SetMachineOperandVal(1, MachineOperand::MO_PCRelativeDisp,
1430 cast<BranchInst>(subtreeRoot->getInstruction())->getSuccessor(0));
1434 mvec.push_back(new MachineInstr(NOP));
1437 case 206: // stmt: BrCond(setCCconst)
1438 { // setCCconst => boolean was computed with `%b = setCC type reg1 const'
1439 // If the constant is ZERO, we can use the branch-on-integer-register
1440 // instructions and avoid the SUBcc instruction entirely.
1441 // Otherwise this is just the same as case 5, so just fall through.
1443 InstrTreeNode* constNode = subtreeRoot->leftChild()->rightChild();
1445 constNode->getNodeType() ==InstrTreeNode::NTConstNode);
1446 Constant *constVal = cast<Constant>(constNode->getValue());
1449 if ((constVal->getType()->isIntegral()
1450 || constVal->getType()->isPointerType())
1451 && GetConstantValueAsSignedInt(constVal, isValidConst) == 0
1454 // That constant is a zero after all...
1455 // Use the left child of setCC as the first argument!
1456 // Mark the setCC node so that no code is generated for it.
1457 InstructionNode* setCCNode = (InstructionNode*)
1458 subtreeRoot->leftChild();
1459 assert(setCCNode->getOpLabel() == SetCCOp);
1460 setCCNode->markFoldedIntoParent();
1462 BranchInst* brInst=cast<BranchInst>(subtreeRoot->getInstruction());
1464 M = new MachineInstr(ChooseBprInstruction(subtreeRoot));
1465 M->SetMachineOperandVal(0, MachineOperand::MO_VirtualRegister,
1466 setCCNode->leftChild()->getValue());
1467 M->SetMachineOperandVal(1, MachineOperand::MO_PCRelativeDisp,
1468 brInst->getSuccessor(0));
1472 mvec.push_back(new MachineInstr(NOP));
1475 M = new MachineInstr(BA);
1476 M->SetMachineOperandVal(0, MachineOperand::MO_CCRegister,
1478 M->SetMachineOperandVal(1, MachineOperand::MO_PCRelativeDisp,
1479 brInst->getSuccessor(1));
1483 mvec.push_back(new MachineInstr(NOP));
1487 // ELSE FALL THROUGH
1490 case 6: // stmt: BrCond(bool)
1491 { // bool => boolean was computed with some boolean operator
1492 // (SetCC, Not, ...). We need to check whether the type was a FP,
1493 // signed int or unsigned int, and check the branching condition in
1494 // order to choose the branch to use.
1495 // If it is an integer CC, we also need to find the unique
1496 // TmpInstruction representing that CC.
1498 BranchInst* brInst = cast<BranchInst>(subtreeRoot->getInstruction());
1500 M = new MachineInstr(ChooseBccInstruction(subtreeRoot, isFPBranch));
1502 Value* ccValue = GetTmpForCC(subtreeRoot->leftChild()->getValue(),
1503 brInst->getParent()->getParent(),
1504 isFPBranch? Type::FloatTy : Type::IntTy);
1506 M->SetMachineOperandVal(0, MachineOperand::MO_CCRegister, ccValue);
1507 M->SetMachineOperandVal(1, MachineOperand::MO_PCRelativeDisp,
1508 brInst->getSuccessor(0));
1512 mvec.push_back(new MachineInstr(NOP));
1515 M = new MachineInstr(BA);
1516 M->SetMachineOperandVal(0, MachineOperand::MO_CCRegister,
1518 M->SetMachineOperandVal(1, MachineOperand::MO_PCRelativeDisp,
1519 brInst->getSuccessor(1));
1523 mvec.push_back(new MachineInstr(NOP));
1527 case 208: // stmt: BrCond(boolconst)
1529 // boolconst => boolean is a constant; use BA to first or second label
1530 Constant* constVal =
1531 cast<Constant>(subtreeRoot->leftChild()->getValue());
1532 unsigned dest = cast<ConstantBool>(constVal)->getValue()? 0 : 1;
1534 M = new MachineInstr(BA);
1535 M->SetMachineOperandVal(0, MachineOperand::MO_CCRegister,
1537 M->SetMachineOperandVal(1, MachineOperand::MO_PCRelativeDisp,
1538 ((BranchInst*) subtreeRoot->getInstruction())->getSuccessor(dest));
1542 mvec.push_back(new MachineInstr(NOP));
1546 case 8: // stmt: BrCond(boolreg)
1547 { // boolreg => boolean is stored in an existing register.
1548 // Just use the branch-on-integer-register instruction!
1550 M = new MachineInstr(BRNZ);
1551 M->SetMachineOperandVal(0, MachineOperand::MO_VirtualRegister,
1552 subtreeRoot->leftChild()->getValue());
1553 M->SetMachineOperandVal(1, MachineOperand::MO_PCRelativeDisp,
1554 ((BranchInst*) subtreeRoot->getInstruction())->getSuccessor(0));
1558 mvec.push_back(new MachineInstr(NOP));
1561 M = new MachineInstr(BA);
1562 M->SetMachineOperandVal(0, MachineOperand::MO_CCRegister,
1564 M->SetMachineOperandVal(1, MachineOperand::MO_PCRelativeDisp,
1565 ((BranchInst*) subtreeRoot->getInstruction())->getSuccessor(1));
1569 mvec.push_back(new MachineInstr(NOP));
1573 case 9: // stmt: Switch(reg)
1574 assert(0 && "*** SWITCH instruction is not implemented yet.");
1577 case 10: // reg: VRegList(reg, reg)
1578 assert(0 && "VRegList should never be the topmost non-chain rule");
1581 case 21: // bool: Not(bool): Both these are implemented as:
1582 case 421: // reg: BNot(reg) : reg = reg XOR-NOT 0
1583 M = new MachineInstr(XNOR);
1584 M->SetMachineOperandVal(0, MachineOperand::MO_VirtualRegister,
1585 subtreeRoot->leftChild()->getValue());
1586 M->SetMachineOperandReg(1, target.getRegInfo().getZeroRegNum());
1587 M->SetMachineOperandVal(2, MachineOperand::MO_VirtualRegister,
1588 subtreeRoot->getValue());
1592 case 322: // reg: ToBoolTy(bool):
1593 case 22: // reg: ToBoolTy(reg):
1595 const Type* opType = subtreeRoot->leftChild()->getValue()->getType();
1596 assert(opType->isIntegral() || opType->isPointerType()
1597 || opType == Type::BoolTy);
1598 forwardOperandNum = 0; // forward first operand to user
1602 case 23: // reg: ToUByteTy(reg)
1603 case 25: // reg: ToUShortTy(reg)
1604 case 27: // reg: ToUIntTy(reg)
1605 case 29: // reg: ToULongTy(reg)
1607 const Type* opType = subtreeRoot->leftChild()->getValue()->getType();
1608 assert(opType->isIntegral() ||
1609 opType->isPointerType() ||
1610 opType == Type::BoolTy && "Cast is illegal for other types");
1611 forwardOperandNum = 0; // forward first operand to user
1615 case 24: // reg: ToSByteTy(reg)
1616 case 26: // reg: ToShortTy(reg)
1617 case 28: // reg: ToIntTy(reg)
1618 case 30: // reg: ToLongTy(reg)
1620 const Type* opType = subtreeRoot->leftChild()->getValue()->getType();
1621 if (opType->isIntegral()
1622 || opType->isPointerType()
1623 || opType == Type::BoolTy)
1625 forwardOperandNum = 0; // forward first operand to user
1629 // If the source operand is an FP type, the int result must be
1630 // copied from float to int register via memory!
1631 Instruction *dest = subtreeRoot->getInstruction();
1632 Value* leftVal = subtreeRoot->leftChild()->getValue();
1634 vector<MachineInstr*> minstrVec;
1636 if (opType == Type::FloatTy || opType == Type::DoubleTy)
1638 // Create a temporary to represent the INT register
1639 // into which the FP value will be copied via memory.
1640 // The type of this temporary will determine the FP
1641 // register used: single-prec for a 32-bit int or smaller,
1642 // double-prec for a 64-bit int.
1644 const Type* destTypeToUse =
1645 (dest->getType() == Type::LongTy)? Type::DoubleTy
1647 destForCast = new TmpInstruction(destTypeToUse, leftVal);
1648 MachineCodeForInstruction &MCFI =
1649 MachineCodeForInstruction::get(dest);
1650 MCFI.addTemp(destForCast);
1652 vector<TmpInstruction*> tempVec;
1653 target.getInstrInfo().CreateCodeToCopyFloatToInt(
1654 dest->getParent()->getParent(),
1655 (TmpInstruction*) destForCast, dest,
1656 minstrVec, tempVec, target);
1658 for (unsigned i=0; i < tempVec.size(); ++i)
1659 MCFI.addTemp(tempVec[i]);
1662 destForCast = leftVal;
1664 MachineOpCode opCode=ChooseConvertToIntInstr(subtreeRoot, opType);
1665 assert(opCode != INVALID_OPCODE && "Expected to need conversion!");
1667 M = new MachineInstr(opCode);
1668 M->SetMachineOperandVal(0, MachineOperand::MO_VirtualRegister,
1670 M->SetMachineOperandVal(1, MachineOperand::MO_VirtualRegister,
1674 // Append the copy code, if any, after the conversion instr.
1675 mvec.insert(mvec.end(), minstrVec.begin(), minstrVec.end());
1680 case 31: // reg: ToFloatTy(reg):
1681 case 32: // reg: ToDoubleTy(reg):
1682 case 232: // reg: ToDoubleTy(Constant):
1684 // If this instruction has a parent (a user) in the tree
1685 // and the user is translated as an FsMULd instruction,
1686 // then the cast is unnecessary. So check that first.
1687 // In the future, we'll want to do the same for the FdMULq instruction,
1688 // so do the check here instead of only for ToFloatTy(reg).
1690 if (subtreeRoot->parent() != NULL &&
1691 MachineCodeForInstruction::get(((InstructionNode*)subtreeRoot->parent())->getInstruction())[0]->getOpCode() == FSMULD)
1693 forwardOperandNum = 0; // forward first operand to user
1697 Value* leftVal = subtreeRoot->leftChild()->getValue();
1698 const Type* opType = leftVal->getType();
1699 MachineOpCode opCode=ChooseConvertToFloatInstr(subtreeRoot,opType);
1700 if (opCode == INVALID_OPCODE) // no conversion needed
1702 forwardOperandNum = 0; // forward first operand to user
1706 // If the source operand is a non-FP type it must be
1707 // first copied from int to float register via memory!
1708 Instruction *dest = subtreeRoot->getInstruction();
1711 if (opType != Type::FloatTy && opType != Type::DoubleTy)
1713 // Create a temporary to represent the FP register
1714 // into which the integer will be copied via memory.
1715 // The type of this temporary will determine the FP
1716 // register used: single-prec for a 32-bit int or smaller,
1717 // double-prec for a 64-bit int.
1719 const Type* srcTypeToUse =
1720 (leftVal->getType() == Type::LongTy)? Type::DoubleTy
1723 srcForCast = new TmpInstruction(srcTypeToUse, dest);
1724 MachineCodeForInstruction &DestMCFI =
1725 MachineCodeForInstruction::get(dest);
1726 DestMCFI.addTemp(srcForCast);
1728 vector<MachineInstr*> minstrVec;
1729 vector<TmpInstruction*> tempVec;
1730 target.getInstrInfo().CreateCodeToCopyIntToFloat(
1731 dest->getParent()->getParent(),
1732 leftVal, (TmpInstruction*) srcForCast,
1733 minstrVec, tempVec, target);
1735 mvec.insert(mvec.end(), minstrVec.begin(),minstrVec.end());
1737 for (unsigned i=0; i < tempVec.size(); ++i)
1738 DestMCFI.addTemp(tempVec[i]);
1741 srcForCast = leftVal;
1743 M = new MachineInstr(opCode);
1744 M->SetMachineOperandVal(0, MachineOperand::MO_VirtualRegister,
1746 M->SetMachineOperandVal(1, MachineOperand::MO_VirtualRegister,
1753 case 19: // reg: ToArrayTy(reg):
1754 case 20: // reg: ToPointerTy(reg):
1755 forwardOperandNum = 0; // forward first operand to user
1758 case 233: // reg: Add(reg, Constant)
1759 M = CreateAddConstInstruction(subtreeRoot);
1765 // ELSE FALL THROUGH
1767 case 33: // reg: Add(reg, reg)
1768 mvec.push_back(new MachineInstr(ChooseAddInstruction(subtreeRoot)));
1769 Set3OperandsFromInstr(mvec.back(), subtreeRoot, target);
1772 case 234: // reg: Sub(reg, Constant)
1773 M = CreateSubConstInstruction(subtreeRoot);
1779 // ELSE FALL THROUGH
1781 case 34: // reg: Sub(reg, reg)
1782 mvec.push_back(new MachineInstr(ChooseSubInstructionByType(
1783 subtreeRoot->getInstruction()->getType())));
1784 Set3OperandsFromInstr(mvec.back(), subtreeRoot, target);
1787 case 135: // reg: Mul(todouble, todouble)
1791 case 35: // reg: Mul(reg, reg)
1793 MachineOpCode forceOp = ((checkCast && BothFloatToDouble(subtreeRoot))
1795 : INVALID_MACHINE_OPCODE);
1796 CreateMulInstruction(target,
1797 subtreeRoot->leftChild()->getValue(),
1798 subtreeRoot->rightChild()->getValue(),
1799 subtreeRoot->getInstruction(),
1803 case 335: // reg: Mul(todouble, todoubleConst)
1807 case 235: // reg: Mul(reg, Constant)
1809 MachineOpCode forceOp = ((checkCast && BothFloatToDouble(subtreeRoot))
1811 : INVALID_MACHINE_OPCODE);
1812 CreateMulInstruction(target,
1813 subtreeRoot->leftChild()->getValue(),
1814 subtreeRoot->rightChild()->getValue(),
1815 subtreeRoot->getInstruction(),
1819 case 236: // reg: Div(reg, Constant)
1821 CreateDivConstInstruction(target, subtreeRoot, mvec);
1822 if (mvec.size() > L)
1824 // ELSE FALL THROUGH
1826 case 36: // reg: Div(reg, reg)
1827 mvec.push_back(new MachineInstr(ChooseDivInstruction(target, subtreeRoot)));
1828 Set3OperandsFromInstr(mvec.back(), subtreeRoot, target);
1831 case 37: // reg: Rem(reg, reg)
1832 case 237: // reg: Rem(reg, Constant)
1834 Instruction* remInstr = subtreeRoot->getInstruction();
1836 TmpInstruction* quot = new TmpInstruction(
1837 subtreeRoot->leftChild()->getValue(),
1838 subtreeRoot->rightChild()->getValue());
1839 TmpInstruction* prod = new TmpInstruction(
1841 subtreeRoot->rightChild()->getValue());
1842 MachineCodeForInstruction::get(remInstr).addTemp(quot).addTemp(prod);
1844 M = new MachineInstr(ChooseDivInstruction(target, subtreeRoot));
1845 Set3OperandsFromInstr(M, subtreeRoot, target);
1846 M->SetMachineOperandVal(2, MachineOperand::MO_VirtualRegister,quot);
1849 M = new MachineInstr(ChooseMulInstructionByType(
1850 subtreeRoot->getInstruction()->getType()));
1851 M->SetMachineOperandVal(0, MachineOperand::MO_VirtualRegister,quot);
1852 M->SetMachineOperandVal(1, MachineOperand::MO_VirtualRegister,
1853 subtreeRoot->rightChild()->getValue());
1854 M->SetMachineOperandVal(2, MachineOperand::MO_VirtualRegister,prod);
1857 M = new MachineInstr(ChooseSubInstructionByType(
1858 subtreeRoot->getInstruction()->getType()));
1859 Set3OperandsFromInstr(M, subtreeRoot, target);
1860 M->SetMachineOperandVal(1, MachineOperand::MO_VirtualRegister,prod);
1866 case 38: // bool: And(bool, bool)
1867 case 238: // bool: And(bool, boolconst)
1868 case 338: // reg : BAnd(reg, reg)
1869 case 538: // reg : BAnd(reg, Constant)
1870 mvec.push_back(new MachineInstr(AND));
1871 Set3OperandsFromInstr(mvec.back(), subtreeRoot, target);
1874 case 138: // bool: And(bool, not)
1875 case 438: // bool: BAnd(bool, not)
1876 mvec.push_back(new MachineInstr(ANDN));
1877 Set3OperandsFromInstr(mvec.back(), subtreeRoot, target);
1880 case 39: // bool: Or(bool, bool)
1881 case 239: // bool: Or(bool, boolconst)
1882 case 339: // reg : BOr(reg, reg)
1883 case 539: // reg : BOr(reg, Constant)
1884 mvec.push_back(new MachineInstr(ORN));
1885 Set3OperandsFromInstr(mvec.back(), subtreeRoot, target);
1888 case 139: // bool: Or(bool, not)
1889 case 439: // bool: BOr(bool, not)
1890 mvec.push_back(new MachineInstr(ORN));
1891 Set3OperandsFromInstr(mvec.back(), subtreeRoot, target);
1894 case 40: // bool: Xor(bool, bool)
1895 case 240: // bool: Xor(bool, boolconst)
1896 case 340: // reg : BXor(reg, reg)
1897 case 540: // reg : BXor(reg, Constant)
1898 mvec.push_back(new MachineInstr(XOR));
1899 Set3OperandsFromInstr(mvec.back(), subtreeRoot, target);
1902 case 140: // bool: Xor(bool, not)
1903 case 440: // bool: BXor(bool, not)
1904 mvec.push_back(new MachineInstr(XNOR));
1905 Set3OperandsFromInstr(mvec.back(), subtreeRoot, target);
1908 case 41: // boolconst: SetCC(reg, Constant)
1910 // If the SetCC was folded into the user (parent), it will be
1911 // caught above. All other cases are the same as case 42,
1912 // so just fall through.
1914 case 42: // bool: SetCC(reg, reg):
1916 // This generates a SUBCC instruction, putting the difference in
1917 // a result register, and setting a condition code.
1919 // If the boolean result of the SetCC is used by anything other
1920 // than a single branch instruction, the boolean must be
1921 // computed and stored in the result register. Otherwise, discard
1922 // the difference (by using %g0) and keep only the condition code.
1924 // To compute the boolean result in a register we use a conditional
1925 // move, unless the result of the SUBCC instruction can be used as
1926 // the bool! This assumes that zero is FALSE and any non-zero
1929 InstructionNode* parentNode = (InstructionNode*) subtreeRoot->parent();
1930 Instruction* setCCInstr = subtreeRoot->getInstruction();
1931 bool keepBoolVal = (parentNode == NULL ||
1932 parentNode->getInstruction()->getOpcode()
1933 != Instruction::Br);
1934 bool subValIsBoolVal = setCCInstr->getOpcode() == Instruction::SetNE;
1935 bool keepSubVal = keepBoolVal && subValIsBoolVal;
1936 bool computeBoolVal = keepBoolVal && ! subValIsBoolVal;
1940 MachineOpCode movOpCode = 0;
1942 // Mark the 4th operand as being a CC register, and as a def
1943 // A TmpInstruction is created to represent the CC "result".
1944 // Unlike other instances of TmpInstruction, this one is used
1945 // by machine code of multiple LLVM instructions, viz.,
1946 // the SetCC and the branch. Make sure to get the same one!
1947 // Note that we do this even for FP CC registers even though they
1948 // are explicit operands, because the type of the operand
1949 // needs to be a floating point condition code, not an integer
1950 // condition code. Think of this as casting the bool result to
1951 // a FP condition code register.
1953 Value* leftVal = subtreeRoot->leftChild()->getValue();
1954 bool isFPCompare = (leftVal->getType() == Type::FloatTy ||
1955 leftVal->getType() == Type::DoubleTy);
1957 TmpInstruction* tmpForCC = GetTmpForCC(setCCInstr,
1958 setCCInstr->getParent()->getParent(),
1959 isFPCompare? Type::FloatTy : Type::IntTy);
1960 MachineCodeForInstruction::get(setCCInstr).addTemp(tmpForCC);
1964 // Integer condition: dest. should be %g0 or an integer register.
1965 // If result must be saved but condition is not SetEQ then we need
1966 // a separate instruction to compute the bool result, so discard
1967 // result of SUBcc instruction anyway.
1969 M = new MachineInstr(SUBcc);
1970 Set3OperandsFromInstr(M, subtreeRoot, target, ! keepSubVal);
1971 M->SetMachineOperandVal(3, MachineOperand::MO_CCRegister,
1972 tmpForCC, /*def*/true);
1976 { // recompute bool using the integer condition codes
1978 ChooseMovpccAfterSub(subtreeRoot,mustClearReg,valueToMove);
1983 // FP condition: dest of FCMP should be some FCCn register
1984 M = new MachineInstr(ChooseFcmpInstruction(subtreeRoot));
1985 M->SetMachineOperandVal(0, MachineOperand::MO_CCRegister,
1987 M->SetMachineOperandVal(1,MachineOperand::MO_VirtualRegister,
1988 subtreeRoot->leftChild()->getValue());
1989 M->SetMachineOperandVal(2,MachineOperand::MO_VirtualRegister,
1990 subtreeRoot->rightChild()->getValue());
1994 {// recompute bool using the FP condition codes
1995 mustClearReg = true;
1997 movOpCode = ChooseMovFpccInstruction(subtreeRoot);
2004 {// Unconditionally set register to 0
2005 M = new MachineInstr(SETHI);
2006 M->SetMachineOperandConst(0,MachineOperand::MO_UnextendedImmed,
2008 M->SetMachineOperandVal(1, MachineOperand::MO_VirtualRegister,
2013 // Now conditionally move `valueToMove' (0 or 1) into the register
2014 M = new MachineInstr(movOpCode);
2015 M->SetMachineOperandVal(0, MachineOperand::MO_CCRegister,
2017 M->SetMachineOperandConst(1, MachineOperand::MO_UnextendedImmed,
2019 M->SetMachineOperandVal(2, MachineOperand::MO_VirtualRegister,
2026 case 43: // boolreg: VReg
2027 case 44: // boolreg: Constant
2030 case 51: // reg: Load(reg)
2031 case 52: // reg: Load(ptrreg)
2032 case 53: // reg: LoadIdx(reg,reg)
2033 case 54: // reg: LoadIdx(ptrreg,reg)
2034 mvec.push_back(new MachineInstr(ChooseLoadInstruction(
2035 subtreeRoot->getValue()->getType())));
2036 SetOperandsForMemInstr(mvec, mvec.end()-1, subtreeRoot, target);
2039 case 55: // reg: GetElemPtr(reg)
2040 case 56: // reg: GetElemPtrIdx(reg,reg)
2041 // If the GetElemPtr was folded into the user (parent), it will be
2042 // caught above. For other cases, we have to compute the address.
2043 mvec.push_back(new MachineInstr(ADD));
2044 SetOperandsForMemInstr(mvec, mvec.end()-1, subtreeRoot, target);
2047 case 57: // reg: Alloca: Implement as 1 instruction:
2048 { // add %fp, offsetFromFP -> result
2049 AllocationInst* instr =
2050 cast<AllocationInst>(subtreeRoot->getInstruction());
2051 unsigned int tsize =
2052 target.findOptimalStorageSize(instr->getAllocatedType());
2054 CreateCodeForFixedSizeAlloca(target, instr, tsize, 1, mvec);
2058 case 58: // reg: Alloca(reg): Implement as 3 instructions:
2059 // mul num, typeSz -> tmp
2060 // sub %sp, tmp -> %sp
2061 { // add %sp, frameSizeBelowDynamicArea -> result
2062 AllocationInst* instr =
2063 cast<AllocationInst>(subtreeRoot->getInstruction());
2064 const Type* eltType = instr->getAllocatedType();
2066 // If #elements is constant, use simpler code for fixed-size allocas
2067 int tsize = (int) target.findOptimalStorageSize(eltType);
2068 Value* numElementsVal = NULL;
2069 bool isArray = instr->isArrayAllocation();
2072 isa<Constant>(numElementsVal = instr->getArraySize()))
2073 { // total size is constant: generate code for fixed-size alloca
2074 unsigned int numElements = isArray?
2075 cast<ConstantUInt>(numElementsVal)->getValue() : 1;
2076 CreateCodeForFixedSizeAlloca(target, instr, tsize,
2079 else // total size is not constant.
2080 CreateCodeForVariableSizeAlloca(target, instr, tsize,
2081 numElementsVal, mvec);
2085 case 61: // reg: Call
2086 { // Generate a call-indirect (i.e., jmpl) for now to expose
2087 // the potential need for registers. If an absolute address
2088 // is available, replace this with a CALL instruction.
2089 // Mark both the indirection register and the return-address
2090 // register as hidden virtual registers.
2091 // Also, mark the operands of the Call and return value (if
2092 // any) as implicit operands of the CALL machine instruction.
2094 CallInst *callInstr = cast<CallInst>(subtreeRoot->getInstruction());
2095 Value *callee = callInstr->getCalledValue();
2097 // Create hidden virtual register for return address, with type void*.
2098 Instruction* retAddrReg =
2099 new TmpInstruction(PointerType::get(Type::VoidTy), callInstr);
2100 MachineCodeForInstruction::get(callInstr).addTemp(retAddrReg);
2102 // Generate the machine instruction and its operands.
2103 // Use CALL for direct function calls; this optimistically assumes
2104 // the PC-relative address fits in the CALL address field (22 bits).
2105 // Use JMPL for indirect calls.
2107 if (isa<Function>(callee))
2108 { // direct function call
2109 M = new MachineInstr(CALL);
2110 M->SetMachineOperandVal(0, MachineOperand::MO_PCRelativeDisp,
2114 { // indirect function call
2115 M = new MachineInstr(JMPLCALL);
2116 M->SetMachineOperandVal(0, MachineOperand::MO_VirtualRegister,
2118 M->SetMachineOperandConst(1, MachineOperand::MO_SignExtendedImmed,
2120 M->SetMachineOperandVal(2, MachineOperand::MO_VirtualRegister,
2126 // WARNING: Operands 0..N-1 must go in slots 0..N-1 of implicitUses.
2127 // The result value must go in slot N. This is assumed
2128 // in register allocation.
2130 // Add the call operands and return value as implicit refs
2131 for (unsigned i=0, N=callInstr->getNumOperands(); i < N; ++i)
2132 if (callInstr->getOperand(i) != callee)
2133 mvec.back()->addImplicitRef(callInstr->getOperand(i));
2135 if (callInstr->getType() != Type::VoidTy)
2136 mvec.back()->addImplicitRef(callInstr, /*isDef*/ true);
2138 // For the CALL instruction, the ret. addr. reg. is also implicit
2139 if (isa<Function>(callee))
2140 mvec.back()->addImplicitRef(retAddrReg, /*isDef*/ true);
2143 mvec.push_back(new MachineInstr(NOP));
2147 case 62: // reg: Shl(reg, reg)
2148 { const Type* opType = subtreeRoot->leftChild()->getValue()->getType();
2149 assert(opType->isIntegral()
2150 || opType == Type::BoolTy
2151 || opType->isPointerType()&& "Shl unsupported for other types");
2152 mvec.push_back(new MachineInstr((opType == Type::LongTy)? SLLX : SLL));
2153 Set3OperandsFromInstr(mvec.back(), subtreeRoot, target);
2157 case 63: // reg: Shr(reg, reg)
2158 { const Type* opType = subtreeRoot->leftChild()->getValue()->getType();
2159 assert(opType->isIntegral()
2160 || opType == Type::BoolTy
2161 || opType->isPointerType() &&"Shr unsupported for other types");
2162 mvec.push_back(new MachineInstr((opType->isSigned()
2163 ? ((opType == Type::LongTy)? SRAX : SRA)
2164 : ((opType == Type::LongTy)? SRLX : SRL))));
2165 Set3OperandsFromInstr(mvec.back(), subtreeRoot, target);
2169 case 64: // reg: Phi(reg,reg)
2170 break; // don't forward the value
2172 #undef NEED_PHI_MACHINE_INSTRS
2173 #ifdef NEED_PHI_MACHINE_INSTRS
2174 { // This instruction has variable #operands, so resultPos is 0.
2175 Instruction* phi = subtreeRoot->getInstruction();
2176 M = new MachineInstr(PHI, 1 + phi->getNumOperands());
2177 M->SetMachineOperandVal(0, MachineOperand::MO_VirtualRegister,
2178 subtreeRoot->getValue());
2179 for (unsigned i=0, N=phi->getNumOperands(); i < N; i++)
2180 M->SetMachineOperandVal(i+1, MachineOperand::MO_VirtualRegister,
2181 phi->getOperand(i));
2185 #endif // NEED_PHI_MACHINE_INSTRS
2188 case 71: // reg: VReg
2189 case 72: // reg: Constant
2190 break; // don't forward the value
2193 assert(0 && "Unrecognized BURG rule");
2198 if (forwardOperandNum >= 0)
2199 { // We did not generate a machine instruction but need to use operand.
2200 // If user is in the same tree, replace Value in its machine operand.
2201 // If not, insert a copy instruction which should get coalesced away
2202 // by register allocation.
2203 if (subtreeRoot->parent() != NULL)
2204 ForwardOperand(subtreeRoot, subtreeRoot->parent(), forwardOperandNum);
2207 vector<MachineInstr*> minstrVec;
2208 target.getInstrInfo().CreateCopyInstructionsByType(target,
2209 subtreeRoot->getInstruction()->getParent()->getParent(),
2210 subtreeRoot->getInstruction()->getOperand(forwardOperandNum),
2211 subtreeRoot->getInstruction(), minstrVec);
2212 assert(minstrVec.size() > 0);
2213 mvec.insert(mvec.end(), minstrVec.begin(), minstrVec.end());