1 //===-- SparcV9InstrInfo.h - Define TargetInstrInfo for SparcV9 -----*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by the LLVM research group and is distributed under
6 // the University of Illinois Open Source License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This class contains information about individual instructions.
11 // Most information is stored in the SparcV9MachineInstrDesc array above.
12 // Other information is computed on demand, and most such functions
13 // default to member functions in base class TargetInstrInfo.
15 //===----------------------------------------------------------------------===//
17 #ifndef SPARC_INSTRINFO_H
18 #define SPARC_INSTRINFO_H
20 #include "llvm/Target/TargetInstrInfo.h"
21 #include "llvm/CodeGen/MachineInstr.h"
22 #include "SparcV9Internals.h"
26 struct SparcV9InstrInfo : public TargetInstrInfo {
29 // All immediate constants are in position 1 except the
30 // store instructions and SETxx.
32 virtual int getImmedConstantPos(MachineOpCode opCode) const {
34 if (this->maxImmedConstant(opCode, ignore) != 0) {
36 assert(! this->isStore((MachineOpCode) V9::STBr - 1));
38 assert(! this->isStore((MachineOpCode) V9::STXFSRi + 1));
40 if (opCode == V9::SETSW || opCode == V9::SETUW ||
41 opCode == V9::SETX || opCode == V9::SETHI)
43 if (opCode >= V9::STBr && opCode <= V9::STXFSRi)
51 virtual bool hasResultInterlock(MachineOpCode opCode) const
53 // All UltraSPARC instructions have interlocks (note that delay slots
54 // are not considered here).
55 // However, instructions that use the result of an FCMP produce a
56 // 9-cycle stall if they are issued less than 3 cycles after the FCMP.
57 // Force the compiler to insert a software interlock (i.e., gap of
58 // 2 other groups, including NOPs if necessary).
59 return (opCode == V9::FCMPS || opCode == V9::FCMPD || opCode == V9::FCMPQ);
62 //-------------------------------------------------------------------------
63 // Queries about representation of LLVM quantities (e.g., constants)
64 //-------------------------------------------------------------------------
66 virtual bool ConstantMayNotFitInImmedField(const Constant* CV,
67 const Instruction* I) const;
69 //-------------------------------------------------------------------------
70 // Code generation support for creating individual machine instructions
71 //-------------------------------------------------------------------------
73 // Get certain common op codes for the current target. This and all the
74 // Create* methods below should be moved to a machine code generation class
76 virtual MachineOpCode getNOPOpCode() const { return V9::NOP; }
78 // Get the value of an integral constant in the form that must
79 // be put into the machine register. The specified constant is interpreted
80 // as (i.e., converted if necessary to) the specified destination type. The
81 // result is always returned as an uint64_t, since the representation of
82 // int64_t and uint64_t are identical. The argument can be any known const.
84 // isValidConstant is set to true if a valid constant was found.
86 virtual uint64_t ConvertConstantToIntType(const TargetMachine &target,
89 bool &isValidConstant) const;
91 // Create an instruction sequence to put the constant `val' into
92 // the virtual register `dest'. `val' may be a Constant or a
93 // GlobalValue, viz., the constant address of a global variable or function.
94 // The generated instructions are returned in `mvec'.
95 // Any temp. registers (TmpInstruction) created are recorded in mcfi.
96 // Any stack space required is allocated via mcff.
98 virtual void CreateCodeToLoadConst(const TargetMachine& target,
102 std::vector<MachineInstr*>& mvec,
103 MachineCodeForInstruction& mcfi) const;
105 // Create an instruction sequence to copy an integer value `val'
106 // to a floating point value `dest' by copying to memory and back.
107 // val must be an integral type. dest must be a Float or Double.
108 // The generated instructions are returned in `mvec'.
109 // Any temp. registers (TmpInstruction) created are recorded in mcfi.
110 // Any stack space required is allocated via mcff.
112 virtual void CreateCodeToCopyIntToFloat(const TargetMachine& target,
116 std::vector<MachineInstr*>& mvec,
117 MachineCodeForInstruction& mcfi) const;
119 // Similarly, create an instruction sequence to copy an FP value
120 // `val' to an integer value `dest' by copying to memory and back.
121 // The generated instructions are returned in `mvec'.
122 // Any temp. registers (TmpInstruction) created are recorded in mcfi.
123 // Any stack space required is allocated via mcff.
125 virtual void CreateCodeToCopyFloatToInt(const TargetMachine& target,
129 std::vector<MachineInstr*>& mvec,
130 MachineCodeForInstruction& mcfi) const;
132 // Create instruction(s) to copy src to dest, for arbitrary types
133 // The generated instructions are returned in `mvec'.
134 // Any temp. registers (TmpInstruction) created are recorded in mcfi.
135 // Any stack space required is allocated via mcff.
137 virtual void CreateCopyInstructionsByType(const TargetMachine& target,
141 std::vector<MachineInstr*>& mvec,
142 MachineCodeForInstruction& mcfi) const;
144 // Create instruction sequence to produce a sign-extended register value
145 // from an arbitrary sized value (sized in bits, not bytes).
146 // The generated instructions are appended to `mvec'.
147 // Any temp. registers (TmpInstruction) created are recorded in mcfi.
148 // Any stack space required is allocated via mcff.
150 virtual void CreateSignExtensionInstructions(const TargetMachine& target,
154 unsigned int numLowBits,
155 std::vector<MachineInstr*>& mvec,
156 MachineCodeForInstruction& mcfi) const;
158 // Create instruction sequence to produce a zero-extended register value
159 // from an arbitrary sized value (sized in bits, not bytes).
160 // The generated instructions are appended to `mvec'.
161 // Any temp. registers (TmpInstruction) created are recorded in mcfi.
162 // Any stack space required is allocated via mcff.
164 virtual void CreateZeroExtensionInstructions(const TargetMachine& target,
168 unsigned int numLowBits,
169 std::vector<MachineInstr*>& mvec,
170 MachineCodeForInstruction& mcfi) const;
173 } // End llvm namespace