1 //===-- SparcInstrInfo.cpp ------------------------------------------------===//
3 //===----------------------------------------------------------------------===//
5 #include "SparcInternals.h"
6 #include "SparcInstrSelectionSupport.h"
7 #include "llvm/CodeGen/InstrSelection.h"
8 #include "llvm/CodeGen/InstrSelectionSupport.h"
9 #include "llvm/CodeGen/MachineFunction.h"
10 #include "llvm/CodeGen/MachineFunctionInfo.h"
11 #include "llvm/CodeGen/MachineCodeForInstruction.h"
12 #include "llvm/Function.h"
13 #include "llvm/Constants.h"
14 #include "llvm/DerivedTypes.h"
18 static const uint32_t MAXLO = (1 << 10) - 1; // set bits set by %lo(*)
19 static const uint32_t MAXSIMM = (1 << 12) - 1; // set bits in simm13 field of OR
22 //----------------------------------------------------------------------------
23 // Function: CreateSETUWConst
25 // Set a 32-bit unsigned constant in the register `dest', using
26 // SETHI, OR in the worst case. This function correctly emulates
27 // the SETUW pseudo-op for SPARC v9 (if argument isSigned == false).
29 // The isSigned=true case is used to implement SETSW without duplicating code.
31 // Optimize some common cases:
32 // (1) Small value that fits in simm13 field of OR: don't need SETHI.
33 // (2) isSigned = true and C is a small negative signed value, i.e.,
34 // high bits are 1, and the remaining bits fit in simm13(OR).
35 //----------------------------------------------------------------------------
38 CreateSETUWConst(const TargetMachine& target, uint32_t C,
39 Instruction* dest, vector<MachineInstr*>& mvec,
40 bool isSigned = false)
42 MachineInstr *miSETHI = NULL, *miOR = NULL;
44 // In order to get efficient code, we should not generate the SETHI if
45 // all high bits are 1 (i.e., this is a small signed value that fits in
46 // the simm13 field of OR). So we check for and handle that case specially.
47 // NOTE: The value C = 0x80000000 is bad: sC < 0 *and* -sC < 0.
48 // In fact, sC == -sC, so we have to check for this explicitly.
49 int32_t sC = (int32_t) C;
50 bool smallNegValue =isSigned && sC < 0 && sC != -sC && -sC < (int32_t)MAXSIMM;
52 // Set the high 22 bits in dest if non-zero and simm13 field of OR not enough
53 if (!smallNegValue && (C & ~MAXLO) && C > MAXSIMM)
55 miSETHI = Create2OperandInstr_UImmed(SETHI, C, dest);
56 miSETHI->setOperandHi32(0);
57 mvec.push_back(miSETHI);
60 // Set the low 10 or 12 bits in dest. This is necessary if no SETHI
61 // was generated, or if the low 10 bits are non-zero.
62 if (miSETHI==NULL || C & MAXLO)
65 { // unsigned value with high-order bits set using SETHI
66 miOR = Create3OperandInstr_UImmed(OR, dest, C, dest);
67 miOR->setOperandLo32(1);
70 { // unsigned or small signed value that fits in simm13 field of OR
71 assert(smallNegValue || (C & ~MAXSIMM) == 0);
72 miOR = new MachineInstr(OR);
73 miOR->SetMachineOperandReg(0, target.getRegInfo().getZeroRegNum());
74 miOR->SetMachineOperandConst(1, MachineOperand::MO_SignExtendedImmed,
76 miOR->SetMachineOperandVal(2,MachineOperand::MO_VirtualRegister,dest);
81 assert((miSETHI || miOR) && "Oops, no code was generated!");
85 //----------------------------------------------------------------------------
86 // Function: CreateSETSWConst
88 // Set a 32-bit signed constant in the register `dest', with sign-extension
89 // to 64 bits. This uses SETHI, OR, SRA in the worst case.
90 // This function correctly emulates the SETSW pseudo-op for SPARC v9.
92 // Optimize the same cases as SETUWConst, plus:
93 // (1) SRA is not needed for positive or small negative values.
94 //----------------------------------------------------------------------------
97 CreateSETSWConst(const TargetMachine& target, int32_t C,
98 Instruction* dest, vector<MachineInstr*>& mvec)
102 // Set the low 32 bits of dest
103 CreateSETUWConst(target, (uint32_t) C, dest, mvec, /*isSigned*/true);
105 // Sign-extend to the high 32 bits if needed
106 if (C < 0 && (-C) > (int32_t) MAXSIMM)
108 MI = Create3OperandInstr_UImmed(SRA, dest, 0, dest);
114 //----------------------------------------------------------------------------
115 // Function: CreateSETXConst
117 // Set a 64-bit signed or unsigned constant in the register `dest'.
118 // Use SETUWConst for each 32 bit word, plus a left-shift-by-32 in between.
119 // This function correctly emulates the SETX pseudo-op for SPARC v9.
121 // Optimize the same cases as SETUWConst for each 32 bit word.
122 //----------------------------------------------------------------------------
125 CreateSETXConst(const TargetMachine& target, uint64_t C,
126 Instruction* tmpReg, Instruction* dest,
127 vector<MachineInstr*>& mvec)
129 assert(C > (unsigned int) ~0 && "Use SETUW/SETSW for 32-bit values!");
133 // Code to set the upper 32 bits of the value in register `tmpReg'
134 CreateSETUWConst(target, (C >> 32), tmpReg, mvec);
136 // Shift tmpReg left by 32 bits
137 MI = Create3OperandInstr_UImmed(SLLX, tmpReg, 32, tmpReg);
140 // Code to set the low 32 bits of the value in register `dest'
141 CreateSETUWConst(target, C, dest, mvec);
143 // dest = OR(tmpReg, dest)
144 MI = Create3OperandInstr(OR, dest, tmpReg, dest);
149 //----------------------------------------------------------------------------
150 // Function: CreateSETUWLabel
152 // Set a 32-bit constant (given by a symbolic label) in the register `dest'.
153 //----------------------------------------------------------------------------
156 CreateSETUWLabel(const TargetMachine& target, Value* val,
157 Instruction* dest, vector<MachineInstr*>& mvec)
161 // Set the high 22 bits in dest
162 MI = Create2OperandInstr(SETHI, val, dest);
163 MI->setOperandHi32(0);
166 // Set the low 10 bits in dest
167 MI = Create3OperandInstr(OR, dest, val, dest);
168 MI->setOperandLo32(1);
173 //----------------------------------------------------------------------------
174 // Function: CreateSETXLabel
176 // Set a 64-bit constant (given by a symbolic label) in the register `dest'.
177 //----------------------------------------------------------------------------
180 CreateSETXLabel(const TargetMachine& target,
181 Value* val, Instruction* tmpReg, Instruction* dest,
182 vector<MachineInstr*>& mvec)
184 assert(isa<Constant>(val) || isa<GlobalValue>(val) &&
185 "I only know about constant values and global addresses");
189 MI = Create2OperandInstr_Addr(SETHI, val, tmpReg);
190 MI->setOperandHi64(0);
193 MI = Create3OperandInstr_Addr(OR, tmpReg, val, tmpReg);
194 MI->setOperandLo64(1);
197 MI = Create3OperandInstr_UImmed(SLLX, tmpReg, 32, tmpReg);
200 MI = Create2OperandInstr_Addr(SETHI, val, dest);
201 MI->setOperandHi32(0);
204 MI = Create3OperandInstr(OR, dest, tmpReg, dest);
207 MI = Create3OperandInstr_Addr(OR, dest, val, dest);
208 MI->setOperandLo32(1);
213 //----------------------------------------------------------------------------
214 // Function: CreateUIntSetInstruction
216 // Create code to Set an unsigned constant in the register `dest'.
217 // Uses CreateSETUWConst, CreateSETSWConst or CreateSETXConst as needed.
218 // CreateSETSWConst is an optimization for the case that the unsigned value
219 // has all ones in the 33 high bits (so that sign-extension sets them all).
220 //----------------------------------------------------------------------------
223 CreateUIntSetInstruction(const TargetMachine& target,
224 uint64_t C, Instruction* dest,
225 std::vector<MachineInstr*>& mvec,
226 MachineCodeForInstruction& mcfi)
228 static const uint64_t lo32 = (uint32_t) ~0;
229 if (C <= lo32) // High 32 bits are 0. Set low 32 bits.
230 CreateSETUWConst(target, (uint32_t) C, dest, mvec);
231 else if ((C & ~lo32) == ~lo32 && (C & (1 << 31)))
232 { // All high 33 (not 32) bits are 1s: sign-extension will take care
233 // of high 32 bits, so use the sequence for signed int
234 CreateSETSWConst(target, (int32_t) C, dest, mvec);
237 { // C does not fit in 32 bits
238 TmpInstruction* tmpReg = new TmpInstruction(Type::IntTy);
239 mcfi.addTemp(tmpReg);
240 CreateSETXConst(target, C, tmpReg, dest, mvec);
245 //----------------------------------------------------------------------------
246 // Function: CreateIntSetInstruction
248 // Create code to Set a signed constant in the register `dest'.
249 // Really the same as CreateUIntSetInstruction.
250 //----------------------------------------------------------------------------
253 CreateIntSetInstruction(const TargetMachine& target,
254 int64_t C, Instruction* dest,
255 std::vector<MachineInstr*>& mvec,
256 MachineCodeForInstruction& mcfi)
258 CreateUIntSetInstruction(target, (uint64_t) C, dest, mvec, mcfi);
262 //---------------------------------------------------------------------------
263 // Create a table of LLVM opcode -> max. immediate constant likely to
264 // be usable for that operation.
265 //---------------------------------------------------------------------------
267 // Entry == 0 ==> no immediate constant field exists at all.
268 // Entry > 0 ==> abs(immediate constant) <= Entry
270 vector<int> MaxConstantsTable(Instruction::OtherOpsEnd);
273 MaxConstantForInstr(unsigned llvmOpCode)
275 int modelOpCode = -1;
277 if (llvmOpCode >= Instruction::BinaryOpsBegin &&
278 llvmOpCode < Instruction::BinaryOpsEnd)
282 case Instruction::Ret: modelOpCode = JMPLCALL; break;
284 case Instruction::Malloc:
285 case Instruction::Alloca:
286 case Instruction::GetElementPtr:
287 case Instruction::PHINode:
288 case Instruction::Cast:
289 case Instruction::Call: modelOpCode = ADD; break;
291 case Instruction::Shl:
292 case Instruction::Shr: modelOpCode = SLLX; break;
297 return (modelOpCode < 0)? 0: SparcMachineInstrDesc[modelOpCode].maxImmedConst;
301 InitializeMaxConstantsTable()
304 assert(MaxConstantsTable.size() == Instruction::OtherOpsEnd &&
305 "assignments below will be illegal!");
306 for (op = Instruction::TermOpsBegin; op < Instruction::TermOpsEnd; ++op)
307 MaxConstantsTable[op] = MaxConstantForInstr(op);
308 for (op = Instruction::BinaryOpsBegin; op < Instruction::BinaryOpsEnd; ++op)
309 MaxConstantsTable[op] = MaxConstantForInstr(op);
310 for (op = Instruction::MemoryOpsBegin; op < Instruction::MemoryOpsEnd; ++op)
311 MaxConstantsTable[op] = MaxConstantForInstr(op);
312 for (op = Instruction::OtherOpsBegin; op < Instruction::OtherOpsEnd; ++op)
313 MaxConstantsTable[op] = MaxConstantForInstr(op);
317 //---------------------------------------------------------------------------
318 // class UltraSparcInstrInfo
321 // Information about individual instructions.
322 // Most information is stored in the SparcMachineInstrDesc array above.
323 // Other information is computed on demand, and most such functions
324 // default to member functions in base class TargetInstrInfo.
325 //---------------------------------------------------------------------------
328 UltraSparcInstrInfo::UltraSparcInstrInfo()
329 : TargetInstrInfo(SparcMachineInstrDesc,
330 /*descSize = */ NUM_TOTAL_OPCODES,
331 /*numRealOpCodes = */ NUM_REAL_OPCODES)
333 InitializeMaxConstantsTable();
337 UltraSparcInstrInfo::ConstantMayNotFitInImmedField(const Constant* CV,
338 const Instruction* I) const
340 if (I->getOpcode() >= MaxConstantsTable.size()) // user-defined op (or bug!)
343 if (isa<ConstantPointerNull>(CV)) // can always use %g0
346 if (const ConstantUInt* U = dyn_cast<ConstantUInt>(CV))
347 /* Large unsigned longs may really just be small negative signed longs */
348 return (labs((int64_t) U->getValue()) > MaxConstantsTable[I->getOpcode()]);
350 if (const ConstantSInt* S = dyn_cast<ConstantSInt>(CV))
351 return (labs(S->getValue()) > MaxConstantsTable[I->getOpcode()]);
353 if (isa<ConstantBool>(CV))
354 return (1 > MaxConstantsTable[I->getOpcode()]);
360 // Create an instruction sequence to put the constant `val' into
361 // the virtual register `dest'. `val' may be a Constant or a
362 // GlobalValue, viz., the constant address of a global variable or function.
363 // The generated instructions are returned in `mvec'.
364 // Any temp. registers (TmpInstruction) created are recorded in mcfi.
365 // Any stack space required is allocated via MachineFunction.
368 UltraSparcInstrInfo::CreateCodeToLoadConst(const TargetMachine& target,
372 vector<MachineInstr*>& mvec,
373 MachineCodeForInstruction& mcfi) const
375 assert(isa<Constant>(val) || isa<GlobalValue>(val) &&
376 "I only know about constant values and global addresses");
378 // Use a "set" instruction for known constants or symbolic constants (labels)
379 // that can go in an integer reg.
380 // We have to use a "load" instruction for all other constants,
381 // in particular, floating point constants.
383 const Type* valType = val->getType();
385 // Unfortunate special case: a ConstantPointerRef is just a
386 // reference to GlobalValue.
387 if (isa<ConstantPointerRef>(val))
388 val = cast<ConstantPointerRef>(val)->getValue();
390 if (isa<GlobalValue>(val))
392 TmpInstruction* tmpReg =
393 new TmpInstruction(PointerType::get(val->getType()), val);
394 mcfi.addTemp(tmpReg);
395 CreateSETXLabel(target, val, tmpReg, dest, mvec);
397 else if (valType->isIntegral())
399 bool isValidConstant;
400 unsigned opSize = target.getTargetData().getTypeSize(val->getType());
401 unsigned destSize = target.getTargetData().getTypeSize(dest->getType());
403 if (! dest->getType()->isSigned())
405 uint64_t C = GetConstantValueAsUnsignedInt(val, isValidConstant);
406 assert(isValidConstant && "Unrecognized constant");
408 if (opSize > destSize ||
409 (val->getType()->isSigned()
410 && destSize < target.getTargetData().getIntegerRegize()))
411 { // operand is larger than dest,
412 // OR both are equal but smaller than the full register size
413 // AND operand is signed, so it may have extra sign bits:
415 C = C & ((1U << 8*destSize) - 1);
417 CreateUIntSetInstruction(target, C, dest, mvec, mcfi);
421 int64_t C = GetConstantValueAsSignedInt(val, isValidConstant);
422 assert(isValidConstant && "Unrecognized constant");
424 if (opSize > destSize)
425 // operand is larger than dest: mask high bits
426 C = C & ((1U << 8*destSize) - 1);
428 if (opSize > destSize ||
429 (opSize == destSize && !val->getType()->isSigned()))
430 // sign-extend from destSize to 64 bits
431 C = ((C & (1U << (8*destSize - 1)))
432 ? C | ~((1U << 8*destSize) - 1)
435 CreateIntSetInstruction(target, C, dest, mvec, mcfi);
440 // Make an instruction sequence to load the constant, viz:
441 // SETX <addr-of-constant>, tmpReg, addrReg
442 // LOAD /*addr*/ addrReg, /*offset*/ 0, dest
444 // First, create a tmp register to be used by the SETX sequence.
445 TmpInstruction* tmpReg =
446 new TmpInstruction(PointerType::get(val->getType()), val);
447 mcfi.addTemp(tmpReg);
449 // Create another TmpInstruction for the address register
450 TmpInstruction* addrReg =
451 new TmpInstruction(PointerType::get(val->getType()), val);
452 mcfi.addTemp(addrReg);
454 // Put the address (a symbolic name) into a register
455 CreateSETXLabel(target, val, tmpReg, addrReg, mvec);
457 // Generate the load instruction
458 int64_t zeroOffset = 0; // to avoid ambiguity with (Value*) 0
460 Create3OperandInstr_SImmed(ChooseLoadInstruction(val->getType()),
461 addrReg, zeroOffset, dest);
464 // Make sure constant is emitted to constant pool in assembly code.
465 MachineFunction::get(F).getInfo()->addToConstantPool(cast<Constant>(val));
470 // Create an instruction sequence to copy an integer register `val'
471 // to a floating point register `dest' by copying to memory and back.
472 // val must be an integral type. dest must be a Float or Double.
473 // The generated instructions are returned in `mvec'.
474 // Any temp. registers (TmpInstruction) created are recorded in mcfi.
475 // Any stack space required is allocated via MachineFunction.
478 UltraSparcInstrInfo::CreateCodeToCopyIntToFloat(const TargetMachine& target,
482 vector<MachineInstr*>& mvec,
483 MachineCodeForInstruction& mcfi) const
485 assert((val->getType()->isIntegral() || isa<PointerType>(val->getType()))
486 && "Source type must be integral (integer or bool) or pointer");
487 assert(dest->getType()->isFloatingPoint()
488 && "Dest type must be float/double");
490 // Get a stack slot to use for the copy
491 int offset = MachineFunction::get(F).getInfo()->allocateLocalVar(val);
493 // Get the size of the source value being copied.
494 size_t srcSize = target.getTargetData().getTypeSize(val->getType());
496 // Store instruction stores `val' to [%fp+offset].
497 // The store and load opCodes are based on the size of the source value.
498 // If the value is smaller than 32 bits, we must sign- or zero-extend it
499 // to 32 bits since the load-float will load 32 bits.
500 // Note that the store instruction is the same for signed and unsigned ints.
501 const Type* storeType = (srcSize <= 4)? Type::IntTy : Type::LongTy;
502 Value* storeVal = val;
503 if (srcSize < target.getTargetData().getTypeSize(Type::FloatTy))
504 { // sign- or zero-extend respectively
505 storeVal = new TmpInstruction(storeType, val);
506 if (val->getType()->isSigned())
507 CreateSignExtensionInstructions(target, F, val, storeVal, 8*srcSize,
510 CreateZeroExtensionInstructions(target, F, val, storeVal, 8*srcSize,
513 MachineInstr* store=new MachineInstr(ChooseStoreInstruction(storeType));
514 store->SetMachineOperandVal(0, MachineOperand::MO_VirtualRegister, storeVal);
515 store->SetMachineOperandReg(1, target.getRegInfo().getFramePointer());
516 store->SetMachineOperandConst(2,MachineOperand::MO_SignExtendedImmed,offset);
517 mvec.push_back(store);
519 // Load instruction loads [%fp+offset] to `dest'.
520 // The type of the load opCode is the floating point type that matches the
521 // stored type in size:
522 // On SparcV9: float for int or smaller, double for long.
524 const Type* loadType = (srcSize <= 4)? Type::FloatTy : Type::DoubleTy;
525 MachineInstr* load = new MachineInstr(ChooseLoadInstruction(loadType));
526 load->SetMachineOperandReg(0, target.getRegInfo().getFramePointer());
527 load->SetMachineOperandConst(1, MachineOperand::MO_SignExtendedImmed,offset);
528 load->SetMachineOperandVal(2, MachineOperand::MO_VirtualRegister, dest);
529 mvec.push_back(load);
532 // Similarly, create an instruction sequence to copy an FP register
533 // `val' to an integer register `dest' by copying to memory and back.
534 // The generated instructions are returned in `mvec'.
535 // Any temp. registers (TmpInstruction) created are recorded in mcfi.
536 // Any stack space required is allocated via MachineFunction.
539 UltraSparcInstrInfo::CreateCodeToCopyFloatToInt(const TargetMachine& target,
543 vector<MachineInstr*>& mvec,
544 MachineCodeForInstruction& mcfi) const
546 const Type* opTy = val->getType();
547 const Type* destTy = dest->getType();
549 assert(opTy->isFloatingPoint() && "Source type must be float/double");
550 assert((destTy->isIntegral() || isa<PointerType>(destTy))
551 && "Dest type must be integer, bool or pointer");
553 int offset = MachineFunction::get(F).getInfo()->allocateLocalVar(val);
555 // Store instruction stores `val' to [%fp+offset].
556 // The store opCode is based only the source value being copied.
558 MachineInstr* store=new MachineInstr(ChooseStoreInstruction(opTy));
559 store->SetMachineOperandVal(0, MachineOperand::MO_VirtualRegister, val);
560 store->SetMachineOperandReg(1, target.getRegInfo().getFramePointer());
561 store->SetMachineOperandConst(2,MachineOperand::MO_SignExtendedImmed,offset);
562 mvec.push_back(store);
564 // Load instruction loads [%fp+offset] to `dest'.
565 // The type of the load opCode is the integer type that matches the
566 // source type in size:
567 // On SparcV9: int for float, long for double.
568 // Note that we *must* use signed loads even for unsigned dest types, to
569 // ensure correct sign-extension for UByte, UShort or UInt:
571 const Type* loadTy = (opTy == Type::FloatTy)? Type::IntTy : Type::LongTy;
572 MachineInstr* load = new MachineInstr(ChooseLoadInstruction(loadTy));
573 load->SetMachineOperandReg(0, target.getRegInfo().getFramePointer());
574 load->SetMachineOperandConst(1, MachineOperand::MO_SignExtendedImmed,offset);
575 load->SetMachineOperandVal(2, MachineOperand::MO_VirtualRegister, dest);
576 mvec.push_back(load);
580 // Create instruction(s) to copy src to dest, for arbitrary types
581 // The generated instructions are returned in `mvec'.
582 // Any temp. registers (TmpInstruction) created are recorded in mcfi.
583 // Any stack space required is allocated via MachineFunction.
586 UltraSparcInstrInfo::CreateCopyInstructionsByType(const TargetMachine& target,
590 vector<MachineInstr*>& mvec,
591 MachineCodeForInstruction& mcfi) const
593 bool loadConstantToReg = false;
595 const Type* resultType = dest->getType();
597 MachineOpCode opCode = ChooseAddInstructionByType(resultType);
598 if (opCode == INVALID_OPCODE)
600 assert(0 && "Unsupported result type in CreateCopyInstructionsByType()");
604 // if `src' is a constant that doesn't fit in the immed field or if it is
605 // a global variable (i.e., a constant address), generate a load
606 // instruction instead of an add
608 if (isa<Constant>(src))
610 unsigned int machineRegNum;
612 MachineOperand::MachineOperandType opType =
613 ChooseRegOrImmed(src, opCode, target, /*canUseImmed*/ true,
614 machineRegNum, immedValue);
616 if (opType == MachineOperand::MO_VirtualRegister)
617 loadConstantToReg = true;
619 else if (isa<GlobalValue>(src))
620 loadConstantToReg = true;
622 if (loadConstantToReg)
623 { // `src' is constant and cannot fit in immed field for the ADD
624 // Insert instructions to "load" the constant into a register
625 target.getInstrInfo().CreateCodeToLoadConst(target, F, src, dest,
629 { // Create an add-with-0 instruction of the appropriate type.
630 // Make `src' the second operand, in case it is a constant
631 // Use (unsigned long) 0 for a NULL pointer value.
633 const Type* zeroValueType =
634 isa<PointerType>(resultType) ? Type::ULongTy : resultType;
635 MachineInstr* minstr =
636 Create3OperandInstr(opCode, Constant::getNullValue(zeroValueType),
638 mvec.push_back(minstr);
643 // Helper function for sign-extension and zero-extension.
644 // For SPARC v9, we sign-extend the given operand using SLL; SRA/SRL.
646 CreateBitExtensionInstructions(bool signExtend,
647 const TargetMachine& target,
651 unsigned int numLowBits,
652 vector<MachineInstr*>& mvec,
653 MachineCodeForInstruction& mcfi)
657 assert(numLowBits <= 32 && "Otherwise, nothing should be done here!");
660 { // SLL is needed since operand size is < 32 bits.
661 TmpInstruction *tmpI = new TmpInstruction(destVal->getType(),
662 srcVal, destVal, "make32");
664 M = Create3OperandInstr_UImmed(SLLX, srcVal, 32-numLowBits, tmpI);
669 M = Create3OperandInstr_UImmed(signExtend? SRA : SRL,
670 srcVal, 32-numLowBits, destVal);
675 // Create instruction sequence to produce a sign-extended register value
676 // from an arbitrary-sized integer value (sized in bits, not bytes).
677 // The generated instructions are returned in `mvec'.
678 // Any temp. registers (TmpInstruction) created are recorded in mcfi.
679 // Any stack space required is allocated via MachineFunction.
682 UltraSparcInstrInfo::CreateSignExtensionInstructions(
683 const TargetMachine& target,
687 unsigned int numLowBits,
688 vector<MachineInstr*>& mvec,
689 MachineCodeForInstruction& mcfi) const
691 CreateBitExtensionInstructions(/*signExtend*/ true, target, F, srcVal,
692 destVal, numLowBits, mvec, mcfi);
696 // Create instruction sequence to produce a zero-extended register value
697 // from an arbitrary-sized integer value (sized in bits, not bytes).
698 // For SPARC v9, we sign-extend the given operand using SLL; SRL.
699 // The generated instructions are returned in `mvec'.
700 // Any temp. registers (TmpInstruction) created are recorded in mcfi.
701 // Any stack space required is allocated via MachineFunction.
704 UltraSparcInstrInfo::CreateZeroExtensionInstructions(
705 const TargetMachine& target,
709 unsigned int numLowBits,
710 vector<MachineInstr*>& mvec,
711 MachineCodeForInstruction& mcfi) const
713 CreateBitExtensionInstructions(/*signExtend*/ false, target, F, srcVal,
714 destVal, numLowBits, mvec, mcfi);