1 //===-- SparcInstrInfo.cpp ------------------------------------------------===//
3 //===----------------------------------------------------------------------===//
5 #include "SparcInternals.h"
6 #include "SparcInstrSelectionSupport.h"
7 #include "llvm/CodeGen/InstrSelection.h"
8 #include "llvm/CodeGen/InstrSelectionSupport.h"
9 #include "llvm/CodeGen/MachineFunction.h"
10 #include "llvm/CodeGen/MachineFunctionInfo.h"
11 #include "llvm/CodeGen/MachineCodeForInstruction.h"
12 #include "llvm/CodeGen/MachineInstrBuilder.h"
13 #include "llvm/Function.h"
14 #include "llvm/Constants.h"
15 #include "llvm/DerivedTypes.h"
16 #include "Config/stdlib.h"
18 static const uint32_t MAXLO = (1 << 10) - 1; // set bits set by %lo(*)
19 static const uint32_t MAXSIMM = (1 << 12) - 1; // set bits in simm13 field of OR
22 //---------------------------------------------------------------------------
23 // Function GetConstantValueAsUnsignedInt
24 // Function GetConstantValueAsSignedInt
26 // Convenience functions to get the value of an integral constant, for an
27 // appropriate integer or non-integer type that can be held in a signed
28 // or unsigned integer respectively. The type of the argument must be
30 // Signed or unsigned integer
34 // isValidConstant is set to true if a valid constant was found.
35 //---------------------------------------------------------------------------
38 GetConstantValueAsUnsignedInt(const Value *V,
39 bool &isValidConstant)
41 isValidConstant = true;
44 if (const ConstantBool *CB = dyn_cast<ConstantBool>(V))
45 return (int64_t)CB->getValue();
46 else if (const ConstantInt *CI = dyn_cast<ConstantInt>(V))
47 return CI->getRawValue();
49 isValidConstant = false;
54 GetConstantValueAsSignedInt(const Value *V, bool &isValidConstant)
56 uint64_t C = GetConstantValueAsUnsignedInt(V, isValidConstant);
57 if (isValidConstant) {
58 if (V->getType()->isSigned() || C < INT64_MAX) // safe to cast to signed
61 isValidConstant = false;
67 //----------------------------------------------------------------------------
68 // Function: CreateSETUWConst
70 // Set a 32-bit unsigned constant in the register `dest', using
71 // SETHI, OR in the worst case. This function correctly emulates
72 // the SETUW pseudo-op for SPARC v9 (if argument isSigned == false).
74 // The isSigned=true case is used to implement SETSW without duplicating code.
76 // Optimize some common cases:
77 // (1) Small value that fits in simm13 field of OR: don't need SETHI.
78 // (2) isSigned = true and C is a small negative signed value, i.e.,
79 // high bits are 1, and the remaining bits fit in simm13(OR).
80 //----------------------------------------------------------------------------
83 CreateSETUWConst(const TargetMachine& target, uint32_t C,
84 Instruction* dest, std::vector<MachineInstr*>& mvec,
85 bool isSigned = false)
87 MachineInstr *miSETHI = NULL, *miOR = NULL;
89 // In order to get efficient code, we should not generate the SETHI if
90 // all high bits are 1 (i.e., this is a small signed value that fits in
91 // the simm13 field of OR). So we check for and handle that case specially.
92 // NOTE: The value C = 0x80000000 is bad: sC < 0 *and* -sC < 0.
93 // In fact, sC == -sC, so we have to check for this explicitly.
94 int32_t sC = (int32_t) C;
95 bool smallNegValue =isSigned && sC < 0 && sC != -sC && -sC < (int32_t)MAXSIMM;
97 // Set the high 22 bits in dest if non-zero and simm13 field of OR not enough
98 if (!smallNegValue && (C & ~MAXLO) && C > MAXSIMM) {
99 miSETHI = BuildMI(V9::SETHI, 2).addZImm(C).addRegDef(dest);
100 miSETHI->setOperandHi32(0);
101 mvec.push_back(miSETHI);
104 // Set the low 10 or 12 bits in dest. This is necessary if no SETHI
105 // was generated, or if the low 10 bits are non-zero.
106 if (miSETHI==NULL || C & MAXLO) {
108 // unsigned value with high-order bits set using SETHI
109 miOR = BuildMI(V9::ORi,3).addReg(dest).addZImm(C).addRegDef(dest);
110 miOR->setOperandLo32(1);
112 // unsigned or small signed value that fits in simm13 field of OR
113 assert(smallNegValue || (C & ~MAXSIMM) == 0);
114 miOR = BuildMI(V9::ORi, 3).addMReg(target.getRegInfo()
116 .addSImm(sC).addRegDef(dest);
118 mvec.push_back(miOR);
121 assert((miSETHI || miOR) && "Oops, no code was generated!");
125 //----------------------------------------------------------------------------
126 // Function: CreateSETSWConst
128 // Set a 32-bit signed constant in the register `dest', with sign-extension
129 // to 64 bits. This uses SETHI, OR, SRA in the worst case.
130 // This function correctly emulates the SETSW pseudo-op for SPARC v9.
132 // Optimize the same cases as SETUWConst, plus:
133 // (1) SRA is not needed for positive or small negative values.
134 //----------------------------------------------------------------------------
137 CreateSETSWConst(const TargetMachine& target, int32_t C,
138 Instruction* dest, std::vector<MachineInstr*>& mvec)
140 // Set the low 32 bits of dest
141 CreateSETUWConst(target, (uint32_t) C, dest, mvec, /*isSigned*/true);
143 // Sign-extend to the high 32 bits if needed.
144 // NOTE: The value C = 0x80000000 is bad: -C == C and so -C is < MAXSIMM
145 if (C < 0 && (C == -C || -C > (int32_t) MAXSIMM))
146 mvec.push_back(BuildMI(V9::SRAi5,3).addReg(dest).addZImm(0).addRegDef(dest));
150 //----------------------------------------------------------------------------
151 // Function: CreateSETXConst
153 // Set a 64-bit signed or unsigned constant in the register `dest'.
154 // Use SETUWConst for each 32 bit word, plus a left-shift-by-32 in between.
155 // This function correctly emulates the SETX pseudo-op for SPARC v9.
157 // Optimize the same cases as SETUWConst for each 32 bit word.
158 //----------------------------------------------------------------------------
161 CreateSETXConst(const TargetMachine& target, uint64_t C,
162 Instruction* tmpReg, Instruction* dest,
163 std::vector<MachineInstr*>& mvec)
165 assert(C > (unsigned int) ~0 && "Use SETUW/SETSW for 32-bit values!");
169 // Code to set the upper 32 bits of the value in register `tmpReg'
170 CreateSETUWConst(target, (C >> 32), tmpReg, mvec);
172 // Shift tmpReg left by 32 bits
173 mvec.push_back(BuildMI(V9::SLLXi6, 3).addReg(tmpReg).addZImm(32)
176 // Code to set the low 32 bits of the value in register `dest'
177 CreateSETUWConst(target, C, dest, mvec);
179 // dest = OR(tmpReg, dest)
180 mvec.push_back(BuildMI(V9::ORr,3).addReg(dest).addReg(tmpReg).addRegDef(dest));
184 //----------------------------------------------------------------------------
185 // Function: CreateSETUWLabel
187 // Set a 32-bit constant (given by a symbolic label) in the register `dest'.
188 //----------------------------------------------------------------------------
191 CreateSETUWLabel(const TargetMachine& target, Value* val,
192 Instruction* dest, std::vector<MachineInstr*>& mvec)
196 // Set the high 22 bits in dest
197 MI = BuildMI(V9::SETHI, 2).addReg(val).addRegDef(dest);
198 MI->setOperandHi32(0);
201 // Set the low 10 bits in dest
202 MI = BuildMI(V9::ORr, 3).addReg(dest).addReg(val).addRegDef(dest);
203 MI->setOperandLo32(1);
208 //----------------------------------------------------------------------------
209 // Function: CreateSETXLabel
211 // Set a 64-bit constant (given by a symbolic label) in the register `dest'.
212 //----------------------------------------------------------------------------
215 CreateSETXLabel(const TargetMachine& target,
216 Value* val, Instruction* tmpReg, Instruction* dest,
217 std::vector<MachineInstr*>& mvec)
219 assert(isa<Constant>(val) || isa<GlobalValue>(val) &&
220 "I only know about constant values and global addresses");
224 MI = BuildMI(V9::SETHI, 2).addPCDisp(val).addRegDef(tmpReg);
225 MI->setOperandHi64(0);
228 MI = BuildMI(V9::ORi, 3).addReg(tmpReg).addPCDisp(val).addRegDef(tmpReg);
229 MI->setOperandLo64(1);
232 mvec.push_back(BuildMI(V9::SLLXi6, 3).addReg(tmpReg).addZImm(32)
234 MI = BuildMI(V9::SETHI, 2).addPCDisp(val).addRegDef(dest);
235 MI->setOperandHi32(0);
238 MI = BuildMI(V9::ORr, 3).addReg(dest).addReg(tmpReg).addRegDef(dest);
241 MI = BuildMI(V9::ORi, 3).addReg(dest).addPCDisp(val).addRegDef(dest);
242 MI->setOperandLo32(1);
247 //----------------------------------------------------------------------------
248 // Function: CreateUIntSetInstruction
250 // Create code to Set an unsigned constant in the register `dest'.
251 // Uses CreateSETUWConst, CreateSETSWConst or CreateSETXConst as needed.
252 // CreateSETSWConst is an optimization for the case that the unsigned value
253 // has all ones in the 33 high bits (so that sign-extension sets them all).
254 //----------------------------------------------------------------------------
257 CreateUIntSetInstruction(const TargetMachine& target,
258 uint64_t C, Instruction* dest,
259 std::vector<MachineInstr*>& mvec,
260 MachineCodeForInstruction& mcfi)
262 static const uint64_t lo32 = (uint32_t) ~0;
263 if (C <= lo32) // High 32 bits are 0. Set low 32 bits.
264 CreateSETUWConst(target, (uint32_t) C, dest, mvec);
265 else if ((C & ~lo32) == ~lo32 && (C & (1U << 31))) {
266 // All high 33 (not 32) bits are 1s: sign-extension will take care
267 // of high 32 bits, so use the sequence for signed int
268 CreateSETSWConst(target, (int32_t) C, dest, mvec);
269 } else if (C > lo32) {
270 // C does not fit in 32 bits
271 TmpInstruction* tmpReg = new TmpInstruction(mcfi, Type::IntTy);
272 CreateSETXConst(target, C, tmpReg, dest, mvec);
277 //----------------------------------------------------------------------------
278 // Function: CreateIntSetInstruction
280 // Create code to Set a signed constant in the register `dest'.
281 // Really the same as CreateUIntSetInstruction.
282 //----------------------------------------------------------------------------
285 CreateIntSetInstruction(const TargetMachine& target,
286 int64_t C, Instruction* dest,
287 std::vector<MachineInstr*>& mvec,
288 MachineCodeForInstruction& mcfi)
290 CreateUIntSetInstruction(target, (uint64_t) C, dest, mvec, mcfi);
294 //---------------------------------------------------------------------------
295 // Create a table of LLVM opcode -> max. immediate constant likely to
296 // be usable for that operation.
297 //---------------------------------------------------------------------------
299 // Entry == 0 ==> no immediate constant field exists at all.
300 // Entry > 0 ==> abs(immediate constant) <= Entry
302 std::vector<int> MaxConstantsTable(Instruction::OtherOpsEnd);
305 MaxConstantForInstr(unsigned llvmOpCode)
307 int modelOpCode = -1;
309 if (llvmOpCode >= Instruction::BinaryOpsBegin &&
310 llvmOpCode < Instruction::BinaryOpsEnd)
311 modelOpCode = V9::ADDi;
314 case Instruction::Ret: modelOpCode = V9::JMPLCALLi; break;
316 case Instruction::Malloc:
317 case Instruction::Alloca:
318 case Instruction::GetElementPtr:
319 case Instruction::PHINode:
320 case Instruction::Cast:
321 case Instruction::Call: modelOpCode = V9::ADDi; break;
323 case Instruction::Shl:
324 case Instruction::Shr: modelOpCode = V9::SLLXi6; break;
329 return (modelOpCode < 0)? 0: SparcMachineInstrDesc[modelOpCode].maxImmedConst;
333 InitializeMaxConstantsTable()
336 assert(MaxConstantsTable.size() == Instruction::OtherOpsEnd &&
337 "assignments below will be illegal!");
338 for (op = Instruction::TermOpsBegin; op < Instruction::TermOpsEnd; ++op)
339 MaxConstantsTable[op] = MaxConstantForInstr(op);
340 for (op = Instruction::BinaryOpsBegin; op < Instruction::BinaryOpsEnd; ++op)
341 MaxConstantsTable[op] = MaxConstantForInstr(op);
342 for (op = Instruction::MemoryOpsBegin; op < Instruction::MemoryOpsEnd; ++op)
343 MaxConstantsTable[op] = MaxConstantForInstr(op);
344 for (op = Instruction::OtherOpsBegin; op < Instruction::OtherOpsEnd; ++op)
345 MaxConstantsTable[op] = MaxConstantForInstr(op);
349 //---------------------------------------------------------------------------
350 // class UltraSparcInstrInfo
353 // Information about individual instructions.
354 // Most information is stored in the SparcMachineInstrDesc array above.
355 // Other information is computed on demand, and most such functions
356 // default to member functions in base class TargetInstrInfo.
357 //---------------------------------------------------------------------------
360 UltraSparcInstrInfo::UltraSparcInstrInfo()
361 : TargetInstrInfo(SparcMachineInstrDesc,
362 /*descSize = */ V9::NUM_TOTAL_OPCODES,
363 /*numRealOpCodes = */ V9::NUM_REAL_OPCODES)
365 InitializeMaxConstantsTable();
369 UltraSparcInstrInfo::ConstantMayNotFitInImmedField(const Constant* CV,
370 const Instruction* I) const
372 if (I->getOpcode() >= MaxConstantsTable.size()) // user-defined op (or bug!)
375 if (isa<ConstantPointerNull>(CV)) // can always use %g0
378 if (const ConstantInt* CI = dyn_cast<ConstantInt>(CV))
379 return labs((int64_t)CI->getRawValue()) > MaxConstantsTable[I->getOpcode()];
381 if (isa<ConstantBool>(CV))
382 return 1 > MaxConstantsTable[I->getOpcode()];
388 // Create an instruction sequence to put the constant `val' into
389 // the virtual register `dest'. `val' may be a Constant or a
390 // GlobalValue, viz., the constant address of a global variable or function.
391 // The generated instructions are returned in `mvec'.
392 // Any temp. registers (TmpInstruction) created are recorded in mcfi.
393 // Any stack space required is allocated via MachineFunction.
396 UltraSparcInstrInfo::CreateCodeToLoadConst(const TargetMachine& target,
400 std::vector<MachineInstr*>& mvec,
401 MachineCodeForInstruction& mcfi) const
403 assert(isa<Constant>(val) || isa<GlobalValue>(val) &&
404 "I only know about constant values and global addresses");
406 // Use a "set" instruction for known constants or symbolic constants (labels)
407 // that can go in an integer reg.
408 // We have to use a "load" instruction for all other constants,
409 // in particular, floating point constants.
411 const Type* valType = val->getType();
413 // Unfortunate special case: a ConstantPointerRef is just a
414 // reference to GlobalValue.
415 if (isa<ConstantPointerRef>(val))
416 val = cast<ConstantPointerRef>(val)->getValue();
418 if (isa<GlobalValue>(val)) {
419 TmpInstruction* tmpReg =
420 new TmpInstruction(mcfi, PointerType::get(val->getType()), val);
421 CreateSETXLabel(target, val, tmpReg, dest, mvec);
422 } else if (valType->isIntegral()) {
423 bool isValidConstant;
424 unsigned opSize = target.getTargetData().getTypeSize(val->getType());
425 unsigned destSize = target.getTargetData().getTypeSize(dest->getType());
427 if (! dest->getType()->isSigned()) {
428 uint64_t C = GetConstantValueAsUnsignedInt(val, isValidConstant);
429 assert(isValidConstant && "Unrecognized constant");
431 if (opSize > destSize || (val->getType()->isSigned() && destSize < 8)) {
432 // operand is larger than dest,
433 // OR both are equal but smaller than the full register size
434 // AND operand is signed, so it may have extra sign bits:
436 C = C & ((1U << 8*destSize) - 1);
438 CreateUIntSetInstruction(target, C, dest, mvec, mcfi);
440 int64_t C = GetConstantValueAsSignedInt(val, isValidConstant);
441 assert(isValidConstant && "Unrecognized constant");
443 if (opSize > destSize)
444 // operand is larger than dest: mask high bits
445 C = C & ((1U << 8*destSize) - 1);
447 if (opSize > destSize ||
448 (opSize == destSize && !val->getType()->isSigned()))
449 // sign-extend from destSize to 64 bits
450 C = ((C & (1U << (8*destSize - 1)))
451 ? C | ~((1U << 8*destSize) - 1)
454 CreateIntSetInstruction(target, C, dest, mvec, mcfi);
457 // Make an instruction sequence to load the constant, viz:
458 // SETX <addr-of-constant>, tmpReg, addrReg
459 // LOAD /*addr*/ addrReg, /*offset*/ 0, dest
461 // First, create a tmp register to be used by the SETX sequence.
462 TmpInstruction* tmpReg =
463 new TmpInstruction(mcfi, PointerType::get(val->getType()), val);
465 // Create another TmpInstruction for the address register
466 TmpInstruction* addrReg =
467 new TmpInstruction(mcfi, PointerType::get(val->getType()), val);
469 // Put the address (a symbolic name) into a register
470 CreateSETXLabel(target, val, tmpReg, addrReg, mvec);
472 // Generate the load instruction
473 int64_t zeroOffset = 0; // to avoid ambiguity with (Value*) 0
474 unsigned Opcode = ChooseLoadInstruction(val->getType());
475 Opcode = convertOpcodeFromRegToImm(Opcode);
476 mvec.push_back(BuildMI(Opcode, 3).addReg(addrReg).
477 addSImm(zeroOffset).addRegDef(dest));
479 // Make sure constant is emitted to constant pool in assembly code.
480 MachineFunction::get(F).getInfo()->addToConstantPool(cast<Constant>(val));
485 // Create an instruction sequence to copy an integer register `val'
486 // to a floating point register `dest' by copying to memory and back.
487 // val must be an integral type. dest must be a Float or Double.
488 // The generated instructions are returned in `mvec'.
489 // Any temp. registers (TmpInstruction) created are recorded in mcfi.
490 // Any stack space required is allocated via MachineFunction.
493 UltraSparcInstrInfo::CreateCodeToCopyIntToFloat(const TargetMachine& target,
497 std::vector<MachineInstr*>& mvec,
498 MachineCodeForInstruction& mcfi) const
500 assert((val->getType()->isIntegral() || isa<PointerType>(val->getType()))
501 && "Source type must be integral (integer or bool) or pointer");
502 assert(dest->getType()->isFloatingPoint()
503 && "Dest type must be float/double");
505 // Get a stack slot to use for the copy
506 int offset = MachineFunction::get(F).getInfo()->allocateLocalVar(val);
508 // Get the size of the source value being copied.
509 size_t srcSize = target.getTargetData().getTypeSize(val->getType());
511 // Store instruction stores `val' to [%fp+offset].
512 // The store and load opCodes are based on the size of the source value.
513 // If the value is smaller than 32 bits, we must sign- or zero-extend it
514 // to 32 bits since the load-float will load 32 bits.
515 // Note that the store instruction is the same for signed and unsigned ints.
516 const Type* storeType = (srcSize <= 4)? Type::IntTy : Type::LongTy;
517 Value* storeVal = val;
518 if (srcSize < target.getTargetData().getTypeSize(Type::FloatTy)) {
519 // sign- or zero-extend respectively
520 storeVal = new TmpInstruction(mcfi, storeType, val);
521 if (val->getType()->isSigned())
522 CreateSignExtensionInstructions(target, F, val, storeVal, 8*srcSize,
525 CreateZeroExtensionInstructions(target, F, val, storeVal, 8*srcSize,
529 unsigned FPReg = target.getRegInfo().getFramePointer();
530 unsigned StoreOpcode = ChooseStoreInstruction(storeType);
531 StoreOpcode = convertOpcodeFromRegToImm(StoreOpcode);
532 mvec.push_back(BuildMI(StoreOpcode, 3)
533 .addReg(storeVal).addMReg(FPReg).addSImm(offset));
535 // Load instruction loads [%fp+offset] to `dest'.
536 // The type of the load opCode is the floating point type that matches the
537 // stored type in size:
538 // On SparcV9: float for int or smaller, double for long.
540 const Type* loadType = (srcSize <= 4)? Type::FloatTy : Type::DoubleTy;
541 unsigned LoadOpcode = ChooseLoadInstruction(loadType);
542 LoadOpcode = convertOpcodeFromRegToImm(LoadOpcode);
543 mvec.push_back(BuildMI(LoadOpcode, 3)
544 .addMReg(FPReg).addSImm(offset).addRegDef(dest));
547 // Similarly, create an instruction sequence to copy an FP register
548 // `val' to an integer register `dest' by copying to memory and back.
549 // The generated instructions are returned in `mvec'.
550 // Any temp. virtual registers (TmpInstruction) created are recorded in mcfi.
551 // Temporary stack space required is allocated via MachineFunction.
554 UltraSparcInstrInfo::CreateCodeToCopyFloatToInt(const TargetMachine& target,
558 std::vector<MachineInstr*>& mvec,
559 MachineCodeForInstruction& mcfi) const
561 const Type* opTy = val->getType();
562 const Type* destTy = dest->getType();
564 assert(opTy->isFloatingPoint() && "Source type must be float/double");
565 assert((destTy->isIntegral() || isa<PointerType>(destTy))
566 && "Dest type must be integer, bool or pointer");
568 // FIXME: For now, we allocate permanent space because the stack frame
569 // manager does not allow locals to be allocated (e.g., for alloca) after
570 // a temp is allocated!
572 int offset = MachineFunction::get(F).getInfo()->allocateLocalVar(val);
574 unsigned FPReg = target.getRegInfo().getFramePointer();
576 // Store instruction stores `val' to [%fp+offset].
577 // The store opCode is based only the source value being copied.
579 unsigned StoreOpcode = ChooseStoreInstruction(opTy);
580 StoreOpcode = convertOpcodeFromRegToImm(StoreOpcode);
581 mvec.push_back(BuildMI(StoreOpcode, 3)
582 .addReg(val).addMReg(FPReg).addSImm(offset));
584 // Load instruction loads [%fp+offset] to `dest'.
585 // The type of the load opCode is the integer type that matches the
586 // source type in size:
587 // On SparcV9: int for float, long for double.
588 // Note that we *must* use signed loads even for unsigned dest types, to
589 // ensure correct sign-extension for UByte, UShort or UInt:
591 const Type* loadTy = (opTy == Type::FloatTy)? Type::IntTy : Type::LongTy;
592 unsigned LoadOpcode = ChooseLoadInstruction(loadTy);
593 LoadOpcode = convertOpcodeFromRegToImm(LoadOpcode);
594 mvec.push_back(BuildMI(LoadOpcode, 3).addMReg(FPReg)
595 .addSImm(offset).addRegDef(dest));
599 // Create instruction(s) to copy src to dest, for arbitrary types
600 // The generated instructions are returned in `mvec'.
601 // Any temp. registers (TmpInstruction) created are recorded in mcfi.
602 // Any stack space required is allocated via MachineFunction.
605 UltraSparcInstrInfo::CreateCopyInstructionsByType(const TargetMachine& target,
609 std::vector<MachineInstr*>& mvec,
610 MachineCodeForInstruction& mcfi) const
612 bool loadConstantToReg = false;
614 const Type* resultType = dest->getType();
616 MachineOpCode opCode = ChooseAddInstructionByType(resultType);
617 if (opCode == V9::INVALID_OPCODE) {
618 assert(0 && "Unsupported result type in CreateCopyInstructionsByType()");
622 // if `src' is a constant that doesn't fit in the immed field or if it is
623 // a global variable (i.e., a constant address), generate a load
624 // instruction instead of an add
626 if (isa<Constant>(src)) {
627 unsigned int machineRegNum;
629 MachineOperand::MachineOperandType opType =
630 ChooseRegOrImmed(src, opCode, target, /*canUseImmed*/ true,
631 machineRegNum, immedValue);
633 if (opType == MachineOperand::MO_VirtualRegister)
634 loadConstantToReg = true;
636 else if (isa<GlobalValue>(src))
637 loadConstantToReg = true;
639 if (loadConstantToReg) {
640 // `src' is constant and cannot fit in immed field for the ADD
641 // Insert instructions to "load" the constant into a register
642 target.getInstrInfo().CreateCodeToLoadConst(target, F, src, dest,
645 // Create a reg-to-reg copy instruction for the given type:
646 // -- For FP values, create a FMOVS or FMOVD instruction
647 // -- For non-FP values, create an add-with-0 instruction (opCode as above)
648 // Make `src' the second operand, in case it is a small constant!
651 if (resultType->isFloatingPoint())
652 MI = (BuildMI(resultType == Type::FloatTy? V9::FMOVS : V9::FMOVD, 2)
653 .addReg(src).addRegDef(dest));
655 const Type* Ty =isa<PointerType>(resultType)? Type::ULongTy :resultType;
656 MI = (BuildMI(opCode, 3)
657 .addSImm((int64_t) 0).addReg(src).addRegDef(dest));
664 // Helper function for sign-extension and zero-extension.
665 // For SPARC v9, we sign-extend the given operand using SLL; SRA/SRL.
667 CreateBitExtensionInstructions(bool signExtend,
668 const TargetMachine& target,
672 unsigned int numLowBits,
673 std::vector<MachineInstr*>& mvec,
674 MachineCodeForInstruction& mcfi)
678 assert(numLowBits <= 32 && "Otherwise, nothing should be done here!");
680 if (numLowBits < 32) {
681 // SLL is needed since operand size is < 32 bits.
682 TmpInstruction *tmpI = new TmpInstruction(mcfi, destVal->getType(),
683 srcVal, destVal, "make32");
684 mvec.push_back(BuildMI(V9::SLLXi6, 3).addReg(srcVal)
685 .addZImm(32-numLowBits).addRegDef(tmpI));
689 mvec.push_back(BuildMI(signExtend? V9::SRAi5 : V9::SRLi5, 3)
690 .addReg(srcVal).addZImm(32-numLowBits).addRegDef(destVal));
694 // Create instruction sequence to produce a sign-extended register value
695 // from an arbitrary-sized integer value (sized in bits, not bytes).
696 // The generated instructions are returned in `mvec'.
697 // Any temp. registers (TmpInstruction) created are recorded in mcfi.
698 // Any stack space required is allocated via MachineFunction.
701 UltraSparcInstrInfo::CreateSignExtensionInstructions(
702 const TargetMachine& target,
706 unsigned int numLowBits,
707 std::vector<MachineInstr*>& mvec,
708 MachineCodeForInstruction& mcfi) const
710 CreateBitExtensionInstructions(/*signExtend*/ true, target, F, srcVal,
711 destVal, numLowBits, mvec, mcfi);
715 // Create instruction sequence to produce a zero-extended register value
716 // from an arbitrary-sized integer value (sized in bits, not bytes).
717 // For SPARC v9, we sign-extend the given operand using SLL; SRL.
718 // The generated instructions are returned in `mvec'.
719 // Any temp. registers (TmpInstruction) created are recorded in mcfi.
720 // Any stack space required is allocated via MachineFunction.
723 UltraSparcInstrInfo::CreateZeroExtensionInstructions(
724 const TargetMachine& target,
728 unsigned int numLowBits,
729 std::vector<MachineInstr*>& mvec,
730 MachineCodeForInstruction& mcfi) const
732 CreateBitExtensionInstructions(/*signExtend*/ false, target, F, srcVal,
733 destVal, numLowBits, mvec, mcfi);