1 //===- SparcV9.td - Target Description for Sparc V9 Target ----------------===//
3 //===----------------------------------------------------------------------===//
7 include "SparcV9_Reg.td"
9 //===----------------------------------------------------------------------===//
11 //===----------------------------------------------------------------------===//
13 class InstV9 : Instruction { // Sparc instruction baseline
19 let Inst{31-30} = op; // Top two bits are the 'op' field
21 // Bit attributes specific to Sparc instructions
22 bit isPasi = 0; // Does this instruction affect an alternate addr space?
23 bit isDeprecated = 0; // Is this instruction deprecated?
24 bit isPrivileged = 0; // Is this a privileged instruction?
27 include "SparcV9_F2.td"
28 include "SparcV9_F3.td"
29 include "SparcV9_F4.td"
31 //===----------------------------------------------------------------------===//
32 // Instruction list...
35 // Section A.2: Add - p137
36 def ADDr : F3_1<2, 0b000000, "add">; // add rs1, rs2, rd
37 def ADDi : F3_2<2, 0b000000, "add">; // add rs1, imm, rd
38 def ADDccr : F3_1<2, 0b010000, "addcc">; // addcc rs1, rs2, rd
39 def ADDcci : F3_2<2, 0b010000, "addcc">; // addcc rs1, imm, rd
40 def ADDCr : F3_1<2, 0b001000, "addC">; // addC rs1, rs2, rd
41 def ADDCi : F3_2<2, 0b001000, "addC">; // addC rs1, imm, rd
42 def ADDCccr : F3_1<2, 0b011000, "addCcc">; // addCcc rs1, rs2, rd
43 def ADDCcci : F3_2<2, 0b011000, "addCcc">; // addCcc rs1, imm, rd
45 // Section A.3: Branch on Integer Register with Prediction - p138
47 def BRZ : F2_4<0b001, "brz">; // Branch on rs1 == 0
48 def BRLEZ : F2_4<0b010, "brlez">; // Branch on rs1 <= 0
49 def BRLZ : F2_4<0b011, "brlz">; // Branch on rs1 < 0
50 def BRNZ : F2_4<0b101, "brnz">; // Branch on rs1 != 0
51 def BRGZ : F2_4<0b110, "brgz">; // Branch on rs1 > 0
52 def BRGEZ : F2_4<0b111, "brgez">; // Branch on rs1 >= 0
55 // Section A.4: Branch on Floating-Point Condition Codes (FBfcc) p140
56 // The following deprecated instructions don't seem to play nice on Sparc
58 let isDeprecated = 1 in {
60 def FBA : F2_2<0b1000, "fba">; // Branch always
61 def FBN : F2_2<0b0000, "fbn">; // Branch never
62 def FBU : F2_2<0b0111, "fbu">; // Branch on unordered
63 def FBG : F2_2<0b0110, "fbg">; // Branch >
64 def FBUG : F2_2<0b0101, "fbug">; // Branch on unordered or >
65 def FBL : F2_2<0b0100, "fbl">; // Branch <
66 def FBUL : F2_2<0b0011, "fbul">; // Branch on unordered or <
67 def FBLG : F2_2<0b0010, "fblg">; // Branch < or >
68 def FBNE : F2_2<0b0001, "fbne">; // Branch !=
69 def FBE : F2_2<0b1001, "fbe">; // Branch ==
70 def FBUE : F2_2<0b1010, "fbue">; // Branch on unordered or ==
71 def FBGE : F2_2<0b1011, "fbge">; // Branch > or ==
72 def FBUGE : F2_2<0b1100, "fbuge">; // Branch unord or > or ==
73 def FBLE : F2_2<0b1101, "fble">; // Branch < or ==
74 def FBULE : F2_2<0b1110, "fbule">; // Branch unord or < or ==
75 def FBO : F2_2<0b1111, "fbo">; // Branch on ordered
80 // We now make these same opcodes represent the FBPfcc instructions
82 def FBA : F2_3<0b1000, "fba">; // Branch always
83 def FBN : F2_3<0b0000, "fbn">; // Branch never
84 def FBU : F2_3<0b0111, "fbu">; // Branch on unordered
85 def FBG : F2_3<0b0110, "fbg">; // Branch >
86 def FBUG : F2_3<0b0101, "fbug">; // Branch on unordered or >
87 def FBL : F2_3<0b0100, "fbl">; // Branch <
88 def FBUL : F2_3<0b0011, "fbul">; // Branch on unordered or <
89 def FBLG : F2_3<0b0010, "fblg">; // Branch < or >
90 def FBNE : F2_3<0b0001, "fbne">; // Branch !=
91 def FBE : F2_3<0b1001, "fbe">; // Branch ==
92 def FBUE : F2_3<0b1010, "fbue">; // Branch on unordered or ==
93 def FBGE : F2_3<0b1011, "fbge">; // Branch > or ==
94 def FBUGE : F2_3<0b1100, "fbuge">; // Branch unord or > or ==
95 def FBLE : F2_3<0b1101, "fble">; // Branch < or ==
96 def FBULE : F2_3<0b1110, "fbule">; // Branch unord or < or ==
97 def FBO : F2_3<0b1111, "fbo">; // Branch on ordered
100 // Section A.5: Branch on FP condition codes with prediction - p143
101 // Not used in the Sparc backend (directly)
104 def FBPA : F2_3<0b1000, "fba">; // Branch always
105 def FBPN : F2_3<0b0000, "fbn">; // Branch never
106 def FBPU : F2_3<0b0111, "fbu">; // Branch on unordered
107 def FBPG : F2_3<0b0110, "fbg">; // Branch >
108 def FBPUG : F2_3<0b0101, "fbug">; // Branch on unordered or >
109 def FBPL : F2_3<0b0100, "fbl">; // Branch <
110 def FBPUL : F2_3<0b0011, "fbul">; // Branch on unordered or <
111 def FBPLG : F2_3<0b0010, "fblg">; // Branch < or >
112 def FBPNE : F2_3<0b0001, "fbne">; // Branch !=
113 def FBPE : F2_3<0b1001, "fbe">; // Branch ==
114 def FBPUE : F2_3<0b1010, "fbue">; // Branch on unordered or ==
115 def FBPGE : F2_3<0b1011, "fbge">; // Branch > or ==
116 def FBPUGE : F2_3<0b1100, "fbuge">; // Branch unord or > or ==
117 def FBPLE : F2_3<0b1101, "fble">; // Branch < or ==
118 def FBPULE : F2_3<0b1110, "fbule">; // Branch unord or < or ==
119 def FBPO : F2_3<0b1111, "fbo">; // Branch on ordered
123 // Section A.6: Branch on Integer condition codes (Bicc) - p146
125 let isDeprecated = 1 in {
127 def BA : F2_2<0b1000, "ba">; // Branch always
128 def BN : F2_2<0b0000, "bn">; // Branch never
129 def BNE : F2_2<0b1001, "bne">; // Branch !=
130 def BE : F2_2<0b0001, "be">; // Branch ==
131 def BG : F2_2<0b1010, "bg">; // Branch >
132 def BLE : F2_2<0b0010, "ble">; // Branch <=
133 def BGE : F2_2<0b1011, "bge">; // Branch >=
134 def BL : F2_2<0b0011, "bl">; // Branch <
135 def BGU : F2_2<0b1100, "bgu">; // Branch unsigned >
136 def BLEU : F2_2<0b0100, "bleu">; // Branch unsigned <=
137 def BCC : F2_2<0b1101, "bcc">; // Branch unsigned >=
138 def BCS : F2_2<0b0101, "bcs">; // Branch unsigned <=
139 def BPOS : F2_2<0b1110, "bpos">; // Branch on positive
140 def BNEG : F2_2<0b0110, "bneg">; // Branch on negative
141 def BVC : F2_2<0b1111, "bvc">; // Branch on overflow clear
142 def BVS : F2_2<0b0111, "bvs">; // Branch on overflow set
147 // Using the format of A.7 instructions...
149 let cc = 0 in { // BA and BN don't read condition codes
150 def BA : F2_3<0b1000, "ba">; // Branch always
151 def BN : F2_3<0b0000, "bn">; // Branch never
153 def BNE : F2_3<0b1001, "bne">; // Branch !=
154 def BE : F2_3<0b0001, "be">; // Branch ==
155 def BG : F2_3<0b1010, "bg">; // Branch >
156 def BLE : F2_3<0b0010, "ble">; // Branch <=
157 def BGE : F2_3<0b1011, "bge">; // Branch >=
158 def BL : F2_3<0b0011, "bl">; // Branch <
159 def BGU : F2_3<0b1100, "bgu">; // Branch unsigned >
160 def BLEU : F2_3<0b0100, "bleu">; // Branch unsigned <=
161 def BCC : F2_3<0b1101, "bcc">; // Branch unsigned >=
162 def BCS : F2_3<0b0101, "bcs">; // Branch unsigned <=
163 def BPOS : F2_3<0b1110, "bpos">; // Branch on positive
164 def BNEG : F2_3<0b0110, "bneg">; // Branch on negative
165 def BVC : F2_3<0b1111, "bvc">; // Branch on overflow clear
166 def BVS : F2_3<0b0111, "bvs">; // Branch on overflow set
169 // Section A.7: Branch on integer condition codes with prediction - p148
170 // Not used in the Sparc backend
173 def BPA : F2_3<0b1000, "bpa">; // Branch always
174 def BPN : F2_3<0b0000, "bpn">; // Branch never
175 def BPNE : F2_3<0b1001, "bpne">; // Branch !=
176 def BPE : F2_3<0b0001, "bpe">; // Branch ==
177 def BPG : F2_3<0b1010, "bpg">; // Branch >
178 def BPLE : F2_3<0b0010, "bple">; // Branch <=
179 def BPGE : F2_3<0b1011, "bpge">; // Branch >=
180 def BPL : F2_3<0b0011, "bpl">; // Branch <
181 def BPGU : F2_3<0b1100, "bpgu">; // Branch unsigned >
182 def BPLEU : F2_3<0b0100, "bpleu">; // Branch unsigned <=
183 def BPCC : F2_3<0b1101, "bpcc">; // Branch unsigned >=
184 def BPCS : F2_3<0b0101, "bpcs">; // Branch unsigned <=
185 def BPPOS : F2_3<0b1110, "bppos">; // Branch on positive
186 def BPNEG : F2_3<0b0110, "bpneg">; // Branch on negative
187 def BPVC : F2_3<0b1111, "bpvc">; // Branch on overflow clear
188 def BPVS : F2_3<0b0111, "bpvs">; // Branch on overflow set
192 // Section A.8: CALL - p151, the only Format #1 instruction
196 let Inst{29-0} = disp;
201 // Section A.9: Compare and Swap - p176
202 // CASA/CASXA: are for alternate address spaces! Ignore them
205 // Section A.10: Divide (64-bit / 32-bit) - p178
206 // Not used in the Sparc backend
208 let isDeprecated = 1 in {
209 def UDIVr : F3_1<2, 0b001110, "udiv">; // udiv r, r, r
210 def UDIVi : F3_2<2, 0b001110, "udiv">; // udiv r, r, i
211 def SDIVr : F3_1<2, 0b001111, "sdiv">; // sdiv r, r, r
212 def SDIVi : F3_2<2, 0b001111, "sdiv">; // sdiv r, r, i
213 def UDIVCCr : F3_1<2, 0b011110, "udivcc">; // udivcc r, r, r
214 def UDIVCCi : F3_2<2, 0b011110, "udivcc">; // udivcc r, r, i
215 def SDIVCCr : F3_1<2, 0b011111, "sdivcc">; // sdivcc r, r, r
216 def SDIVCCi : F3_2<2, 0b011111, "sdivcc">; // sdivcc r, r, i
220 // Section A.11: DONE and RETRY - p181
221 // Not used in the Sparc backend
223 let isPrivileged = 1 in {
224 def DONE : F3_18<0, "done">; // done
225 def RETRY : F3_18<1, "retry">; // retry
229 // Section A.12: Floating-Point Add and Subtract - p156
230 def FADDS : F3_16<2, 0b110100, 0x41, "fadds">; // fadds frs1, frs2, frd
231 def FADDD : F3_16<2, 0b110100, 0x42, "faddd">; // faddd frs1, frs2, frd
232 def FADDQ : F3_16<2, 0b110100, 0x43, "faddq">; // faddq frs1, frs2, frd
233 def FSUBS : F3_16<2, 0b110100, 0x45, "fsubs">; // fsubs frs1, frs2, frd
234 def FSUBD : F3_16<2, 0b110100, 0x46, "fsubd">; // fsubd frs1, frs2, frd
235 def FSUBQ : F3_16<2, 0b110100, 0x47, "fsubq">; // fsubq frs1, frs2, frd
237 // Section A.13: Floating-point compare - p159
238 def FCMPS : F3_15<2, 0b110101, 0b001010001, "fcmps">; // fcmps %fcc, r1, r2
239 def FCMPD : F3_15<2, 0b110101, 0b001010010, "fcmpd">; // fcmpd %fcc, r1, r2
240 def FCMPQ : F3_15<2, 0b110101, 0b001010011, "fcmpq">; // fcmpq %fcc, r1, r2
241 // Currently unused in the Sparc backend
243 def FCMPES : F3_15<2, 0b110101, 0b001010101, "fcmpes">; // fcmpes %fcc, r1, r2
244 def FCMPED : F3_15<2, 0b110101, 0b001010110, "fcmped">; // fcmped %fcc, r1, r2
245 def FCMPEQ : F3_15<2, 0b110101, 0b001010111, "fcmpeq">; // fcmpeq %fcc, r1, r2
248 // Section A.14: Convert floating-point to integer - p161
249 def FSTOX : F3_14<2, 0b110100, 0b010000001, "fstox">; // fstox rs2, rd
250 def FDTOX : F3_14<2, 0b110100, 0b010000010, "fstox">; // fstox rs2, rd
251 def FQTOX : F3_14<2, 0b110100, 0b010000011, "fstox">; // fstox rs2, rd
252 def FSTOI : F3_14<2, 0b110100, 0b011010001, "fstoi">; // fstoi rs2, rd
253 def FDTOI : F3_14<2, 0b110100, 0b011010010, "fdtoi">; // fdtoi rs2, rd
254 def FQTOI : F3_14<2, 0b110100, 0b011010011, "fqtoi">; // fqtoi rs2, rd
256 // Section A.15: Convert between floating-point formats - p162
257 def FSTOD : F3_14<2, 0b110100, 0b011001001, "fstod">; // fstod rs2, rd
258 def FSTOQ : F3_14<2, 0b110100, 0b011001101, "fstoq">; // fstoq rs2, rd
259 def FDTOS : F3_14<2, 0b110100, 0b011000110, "fstos">; // fstos rs2, rd
260 def FDTOQ : F3_14<2, 0b110100, 0b011001110, "fdtoq">; // fdtoq rs2, rd
261 def FQTOS : F3_14<2, 0b110100, 0b011000111, "fqtos">; // fqtos rs2, rd
262 def FQTOD : F3_14<2, 0b110100, 0b011001011, "fqtod">; // fqtod rs2, rd
264 // Section A.16: Convert integer to floating-point - p163
265 def FXTOS : F3_14<2, 0b110100, 0b010000100, "fxtos">; // fxtos rs2, rd
266 def FXTOD : F3_14<2, 0b110100, 0b010001000, "fxtod">; // fxtod rs2, rd
267 def FXTOQ : F3_14<2, 0b110100, 0b010001100, "fxtoq">; // fxtoq rs2, rd
268 def FITOS : F3_14<2, 0b110100, 0b011000100, "fitos">; // fitos rs2, rd
269 def FITOD : F3_14<2, 0b110100, 0b011001000, "fitod">; // fitod rs2, rd
270 def FITOQ : F3_14<2, 0b110100, 0b011001100, "fitoq">; // fitoq rs2, rd
272 // Section A.17: Floating-Point Move - p164
273 def FMOVS : F3_14<2, 0b110100, 0b000000001, "fmovs">; // fmovs r, r
274 def FMOVD : F3_14<2, 0b110100, 0b000000010, "fmovs">; // fmovd r, r
275 //def FMOVQ : F3_14<2, 0b110100, 0b000000011, "fmovs">; // fmovq r, r
276 def FNEGS : F3_14<2, 0b110100, 0b000000101, "fnegs">; // fnegs r, r
277 def FNEGD : F3_14<2, 0b110100, 0b000000110, "fnegs">; // fnegs r, r
278 //def FNEGQ : F3_14<2, 0b110100, 0b000000111, "fnegs">; // fnegs r, r
279 def FABSS : F3_14<2, 0b110100, 0b000001001, "fabss">; // fabss r, r
280 def FABSD : F3_14<2, 0b110100, 0b000001010, "fabss">; // fabss r, r
281 //def FABSQ : F3_14<2, 0b110100, 0b000001011, "fabss">; // fabss r, r
283 // Section A.18: Floating-Point Multiply and Divide - p165
284 def FMULS : F3_16<2, 0b110100, 0b001001001, "fmuls">; // fmuls r, r, r
285 def FMULD : F3_16<2, 0b110100, 0b001001010, "fmuld">; // fmuld r, r, r
286 def FMULQ : F3_16<2, 0b110100, 0b001001011, "fmulq">; // fmulq r, r, r
287 def FSMULD : F3_16<2, 0b110100, 0b001101001, "fsmuld">; // fsmuls r, r, r
288 def FDMULQ : F3_16<2, 0b110100, 0b001101110, "fdmulq">; // fdmuls r, r, r
289 def FDIVS : F3_16<2, 0b110100, 0b001001101, "fdivs">; // fdivs r, r, r
290 def FDIVD : F3_16<2, 0b110100, 0b001001110, "fdivs">; // fdivd r, r, r
291 def FDIVQ : F3_16<2, 0b110100, 0b001001111, "fdivs">; // fdivq r, r, r
293 // Section A.19: Floating-Point Square Root - p166
294 def FSQRTS : F3_14<2, 0b110100, 0b000101001, "fsqrts">; // fsqrts r, r
295 def FSQRTD : F3_14<2, 0b110100, 0b000101010, "fsqrts">; // fsqrts r, r
296 def FSQRTQ : F3_14<2, 0b110100, 0b000101011, "fsqrts">; // fsqrts r, r
298 // A.20: Flush Instruction Memory - p167
299 // Not currently used
301 // A.21: Flush Register Windows - p169
302 // Not currently used
304 // A.22: Illegal instruction Trap - p170
305 // Not currently used
307 // A.23: Implementation-Dependent Instructions - p171
308 // Not currently used
310 // Section A.24: Jump and Link - p172
311 // Mimicking the Sparc's instr def...
312 def JMPLCALLr : F3_1<2, 0b111000, "jmpl">; // jmpl [rs1+rs2], rd
313 def JMPLCALLi : F3_2<2, 0b111000, "jmpl">; // jmpl [rs1+imm], rd
314 def JMPLRETr : F3_1<2, 0b111000, "jmpl">; // jmpl [rs1+rs2], rd
315 def JMPLRETi : F3_2<2, 0b111000, "jmpl">; // jmpl [rs1+imm], rd
317 // Section A.25: Load Floating-Point - p173
318 def LDFr : F3_1<3, 0b100000, "ld">; // ld [rs1+rs2], rd
319 def LDFi : F3_2<3, 0b100000, "ld">; // ld [rs1+imm], rd
320 def LDDFr : F3_1<3, 0b100011, "ldd">; // ldd [rs1+rs2], rd
321 def LDDFi : F3_2<3, 0b100011, "ldd">; // ldd [rs1+imm], rd
322 def LDQFr : F3_1<3, 0b100010, "ldq">; // ldq [rs1+rs2], rd
323 def LDQFi : F3_2<3, 0b100010, "ldq">; // ldq [rs1+imm], rd
324 let isDeprecated = 1 in {
326 def LDFSRr : F3_1<3, 0b100001, "ld">; // ld [rs1+rs2], rd
327 def LDFSRi : F3_2<3, 0b100001, "ld">; // ld [rs1+imm], rd
331 def LDXFSRr : F3_1<3, 0b100001, "ldx">; // ldx [rs1+rs2], rd
332 def LDXFSRi : F3_2<3, 0b100001, "ldx">; // ldx [rs1+imm], rd
335 // Section A.27: Load Integer - p178
336 def LDSBr : F3_1<3, 0b001001, "ldsb">; // ldsb [rs1+rs2], rd
337 def LDSBi : F3_2<3, 0b001001, "ldsb">; // ldsb [rs1+imm], rd
338 def LDSHr : F3_1<3, 0b001010, "ldsh">; // ldsh [rs1+rs2], rd
339 def LDSHi : F3_2<3, 0b001010, "ldsh">; // ldsh [rs1+imm], rd
340 def LDSWr : F3_1<3, 0b001000, "ldsw">; // ldsh [rs1+rs2], rd
341 def LDSWi : F3_2<3, 0b001000, "ldsw">; // ldsh [rs1+imm], rd
342 def LDUBr : F3_1<3, 0b000001, "ldub">; // ldub [rs1+rs2], rd
343 def LDUBi : F3_2<3, 0b000001, "ldub">; // ldub [rs1+imm], rd
344 def LDUHr : F3_1<3, 0b000010, "lduh">; // lduh [rs1+rs2], rd
345 def LDUHi : F3_2<3, 0b000010, "lduh">; // lduh [rs1+imm], rd
347 def LDUWr : F3_1<3, 0b000000, "lduw">; // lduw [rs1+rs2], rd
348 def LDUWi : F3_2<3, 0b000000, "lduw">; // lduw [rs1+imm], rd
349 def LDXr : F3_1<3, 0b001011, "ldx">; // ldx [rs1+rs2], rd
350 def LDXi : F3_2<3, 0b001011, "ldx">; // ldx [rs1+imm], rd
352 let isDeprecated = 1 in {
353 def LDDr : F3_1<3, 0b000011, "ldd">; // ldd [rs1+rs2], rd
354 def LDDi : F3_2<3, 0b000011, "ldd">; // ldd [rs1+imm], rd
358 // Section A.31: Logical operations
359 def ANDr : F3_1<2, 0b000001, "and">; // and rs1, rs2, rd
360 def ANDi : F3_2<2, 0b000001, "and">; // and rs1, imm, rd
361 def ANDccr : F3_1<2, 0b010001, "andcc">; // andcc rs1, rs2, rd
362 def ANDcci : F3_2<2, 0b010001, "andcc">; // andcc rs1, imm, rd
363 def ANDNr : F3_1<2, 0b000101, "andn">; // andn rs1, rs2, rd
364 def ANDNi : F3_2<2, 0b000101, "andn">; // andn rs1, imm, rd
365 def ANDNccr : F3_1<2, 0b010101, "andncc">; // andncc rs1, rs2, rd
366 def ANDNcci : F3_2<2, 0b010101, "andncc">; // andncc rs1, imm, rd
368 def ORr : F3_1<2, 0b000010, "or">; // or rs1, rs2, rd
369 def ORi : F3_2<2, 0b000010, "or">; // or rs1, imm, rd
370 def ORccr : F3_1<2, 0b010010, "orcc">; // orcc rs1, rs2, rd
371 def ORcci : F3_2<2, 0b010010, "orcc">; // orcc rs1, imm, rd
372 def ORNr : F3_1<2, 0b000110, "orn">; // orn rs1, rs2, rd
373 def ORNi : F3_2<2, 0b000110, "orn">; // orn rs1, imm, rd
374 def ORNccr : F3_1<2, 0b010110, "orncc">; // orncc rs1, rs2, rd
375 def ORNcci : F3_2<2, 0b010110, "orncc">; // orncc rs1, imm, rd
377 def XORr : F3_1<2, 0b000011, "xor">; // xor rs1, rs2, rd
378 def XORi : F3_2<2, 0b000011, "xor">; // xor rs1, imm, rd
379 def XORccr : F3_1<2, 0b010011, "xorcc">; // xorcc rs1, rs2, rd
380 def XORcci : F3_2<2, 0b010011, "xorcc">; // xorcc rs1, imm, rd
381 def XNORr : F3_1<2, 0b000111, "xnor">; // xnor rs1, rs2, rd
382 def XNORi : F3_2<2, 0b000111, "xnor">; // xnor rs1, imm, rd
383 def XNORccr : F3_1<2, 0b010111, "xnorcc">; // xnorcc rs1, rs2, rd
384 def XNORcci : F3_2<2, 0b010111, "xnorcc">; // xnorcc rs1, imm, rd
386 // Section A.32: Memory Barrier - p186
387 // Not currently used in the Sparc backend
389 // Section A.33: Move Floating-Point Register on Condition (FMOVcc)
390 // ======================= Single Floating Point ======================
391 // For integer condition codes
392 def FMOVSA : F4_7<2, 0b110101, 0b1000, 0b000001, "fmovsa">; // fmovsa cc, r, r
393 def FMOVSN : F4_7<2, 0b110101, 0b0000, 0b000001, "fmovsn">; // fmovsn cc, r, r
394 def FMOVSNE : F4_7<2, 0b110101, 0b1001, 0b000001, "fmovsne">; // fmovsne cc, r, r
395 def FMOVSE : F4_7<2, 0b110101, 0b0000, 0b000001, "fmovse">; // fmovse cc, r, r
396 def FMOVSG : F4_7<2, 0b110101, 0b1010, 0b000001, "fmovsg">; // fmovsg cc, r, r
397 def FMOVSLE : F4_7<2, 0b110101, 0b0000, 0b000001, "fmovsle">; // fmovsle cc, r, r
398 def FMOVSGE : F4_7<2, 0b110101, 0b1011, 0b000001, "fmovsge">; // fmovsge cc, r, r
399 def FMOVSL : F4_7<2, 0b110101, 0b0011, 0b000001, "fmovsl">; // fmovsl cc, r, r
400 def FMOVSGU : F4_7<2, 0b110101, 0b1100, 0b000001, "fmovsgu">; // fmovsgu cc, r, r
401 def FMOVSLEU : F4_7<2, 0b110101, 0b0100, 0b000001, "fmovsleu">; // fmovsleu cc, r, r
402 def FMOVSCC : F4_7<2, 0b110101, 0b1101, 0b000001, "fmovscc">; // fmovscc cc, r, r
403 def FMOVSCS : F4_7<2, 0b110101, 0b0101, 0b000001, "fmovscs">; // fmovscs cc, r, r
404 def FMOVSPOS : F4_7<2, 0b110101, 0b1110, 0b000001, "fmovspos">; // fmovspos cc, r, r
405 def FMOVSNEG : F4_7<2, 0b110101, 0b0110, 0b000001, "fmovsneg">; // fmovsneg cc, r, r
406 def FMOVSVC : F4_7<2, 0b110101, 0b1111, 0b000001, "fmovsvc">; // fmovsvc cc, r, r
407 def FMOVSVS : F4_7<2, 0b110101, 0b0111, 0b000001, "fmovsvs">; // fmovsvs cc, r, r
409 // For floating-point condition codes
410 def FMOVSFA : F4_7<2, 0b110101, 0b0100, 0b000001, "fmovsfa">; // fmovsfa cc,r,r
411 def FMOVSFN : F4_7<2, 0b110101, 0b0000, 0b000001, "fmovsfn">; // fmovsfa cc,r,r
412 def FMOVSFU : F4_7<2, 0b110101, 0b0111, 0b000001, "fmovsfu">; // fmovsfu cc,r,r
413 def FMOVSFG : F4_7<2, 0b110101, 0b0110, 0b000001, "fmovsfg">; // fmovsfg cc,r,r
414 def FMOVSFUG : F4_7<2, 0b110101, 0b0101, 0b000001, "fmovsfug">; // fmovsfug cc,r,r
415 def FMOVSFL : F4_7<2, 0b110101, 0b0100, 0b000001, "fmovsfl">; // fmovsfl cc,r,r
416 def FMOVSFUL : F4_7<2, 0b110101, 0b0011, 0b000001, "fmovsful">; // fmovsful cc,r,r
417 def FMOVSFLG : F4_7<2, 0b110101, 0b0010, 0b000001, "fmovsflg">; // fmovsflg cc,r,r
418 def FMOVSFNE : F4_7<2, 0b110101, 0b0001, 0b000001, "fmovsfne">; // fmovsfne cc,r,r
419 def FMOVSFE : F4_7<2, 0b110101, 0b1001, 0b000001, "fmovsfe">; // fmovsfe cc,r,r
420 def FMOVSFUE : F4_7<2, 0b110101, 0b1010, 0b000001, "fmovsfue">; // fmovsfue cc,r,r
421 def FMOVSFGE : F4_7<2, 0b110101, 0b1011, 0b000001, "fmovsge">; // fmovsge cc,r,r
422 def FMOVSFUGE : F4_7<2, 0b110101, 0b1100, 0b000001, "fmovsfuge">;// fmovsfuge cc,r,r
423 def FMOVSFLE : F4_7<2, 0b110101, 0b1101, 0b000001, "fmovsfle">; // fmovsfle cc,r,r
424 def FMOVSFULE : F4_7<2, 0b110101, 0b1110, 0b000001, "fmovsfule">;// fmovsfule cc,r,r
425 def FMOVSFO : F4_7<2, 0b110101, 0b1111, 0b000001, "fmovsfo">; // fmovsfo cc,r,r
427 // ======================= Double Floating Point ======================
428 // For integer condition codes
429 def FMOVDA : F4_7<2, 0b110101, 0b1000, 0b000010, "fmovda">; // fmovda cc, r, r
430 def FMOVDN : F4_7<2, 0b110101, 0b0000, 0b000010, "fmovdn">; // fmovdn cc, r, r
431 def FMOVDNE : F4_7<2, 0b110101, 0b1001, 0b000010, "fmovdne">; // fmovdne cc, r, r
432 def FMOVDE : F4_7<2, 0b110101, 0b0000, 0b000010, "fmovde">; // fmovde cc, r, r
433 def FMOVDG : F4_7<2, 0b110101, 0b1010, 0b000010, "fmovdg">; // fmovdg cc, r, r
434 def FMOVDLE : F4_7<2, 0b110101, 0b0000, 0b000010, "fmovdle">; // fmovdle cc, r, r
435 def FMOVDGE : F4_7<2, 0b110101, 0b1011, 0b000010, "fmovdge">; // fmovdge cc, r, r
436 def FMOVDL : F4_7<2, 0b110101, 0b0011, 0b000010, "fmovdl">; // fmovdl cc, r, r
437 def FMOVDGU : F4_7<2, 0b110101, 0b1100, 0b000010, "fmovdgu">; // fmovdgu cc, r, r
438 def FMOVDLEU : F4_7<2, 0b110101, 0b0100, 0b000010, "fmovdleu">; // fmovdleu cc, r, r
439 def FMOVDCC : F4_7<2, 0b110101, 0b1101, 0b000010, "fmovdcc">; // fmovdcc cc, r, r
440 def FMOVDCS : F4_7<2, 0b110101, 0b0101, 0b000010, "fmovdcs">; // fmovdcs cc, r, r
441 def FMOVDPOS : F4_7<2, 0b110101, 0b1110, 0b000010, "fmovdpos">; // fmovdpos cc, r, r
442 def FMOVDNEG : F4_7<2, 0b110101, 0b0110, 0b000010, "fmovdneg">; // fmovdneg cc, r, r
443 def FMOVDVC : F4_7<2, 0b110101, 0b1111, 0b000010, "fmovdvc">; // fmovdvc cc, r, r
444 def FMOVDVS : F4_7<2, 0b110101, 0b0111, 0b000010, "fmovdvs">; // fmovdvs cc, r, r
446 // For floating-point condition codes
447 def FMOVDFA : F4_7<2, 0b110101, 0b0100, 0b000010, "fmovdfa">; // fmovdfa cc,r,r
448 def FMOVDFN : F4_7<2, 0b110101, 0b0000, 0b000010, "fmovdfn">; // fmovdfa cc,r,r
449 def FMOVDFU : F4_7<2, 0b110101, 0b0111, 0b000010, "fmovdfu">; // fmovdfu cc,r,r
450 def FMOVDFG : F4_7<2, 0b110101, 0b0110, 0b000010, "fmovdfg">; // fmovdfg cc,r,r
451 def FMOVDFUG : F4_7<2, 0b110101, 0b0101, 0b000010, "fmovdfug">; // fmovdfug cc,r,r
452 def FMOVDFL : F4_7<2, 0b110101, 0b0100, 0b000010, "fmovdfl">; // fmovdfl cc,r,r
453 def FMOVDFUL : F4_7<2, 0b110101, 0b0011, 0b000010, "fmovdful">; // fmovdful cc,r,r
454 def FMOVDFLG : F4_7<2, 0b110101, 0b0010, 0b000010, "fmovdflg">; // fmovdflg cc,r,r
455 def FMOVDFNE : F4_7<2, 0b110101, 0b0001, 0b000010, "fmovdfne">; // fmovdfne cc,r,r
456 def FMOVDFE : F4_7<2, 0b110101, 0b1001, 0b000010, "fmovdfe">; // fmovdfe cc,r,r
457 def FMOVDFUE : F4_7<2, 0b110101, 0b1010, 0b000010, "fmovdfue">; // fmovdfue cc,r,r
458 def FMOVDFGE : F4_7<2, 0b110101, 0b1011, 0b000010, "fmovdge">; // fmovdge cc,r,r
459 def FMOVDFUGE : F4_7<2, 0b110101, 0b1100, 0b000010, "fmovdfuge">;// fmovdfuge cc,r,r
460 def FMOVDFLE : F4_7<2, 0b110101, 0b1101, 0b000010, "fmovdfle">; // fmovdfle cc,r,r
461 def FMOVDFULE : F4_7<2, 0b110101, 0b1110, 0b000010, "fmovdfule">;// fmovdfule cc,r,r
462 def FMOVDFO : F4_7<2, 0b110101, 0b1111, 0b000010, "fmovdfo">; // fmovdfo cc,r,r
464 // ======================= Quad Floating Point ======================
465 // For integer condition codes
466 def FMOVQA : F4_7<2, 0b110101, 0b1000, 0b000011, "fmovqa">; // fmovqa cc, r, r
467 def FMOVQN : F4_7<2, 0b110101, 0b0000, 0b000011, "fmovqn">; // fmovqn cc, r, r
468 def FMOVQNE : F4_7<2, 0b110101, 0b1001, 0b000011, "fmovqne">; // fmovqne cc, r, r
469 def FMOVQE : F4_7<2, 0b110101, 0b0000, 0b000011, "fmovqe">; // fmovqe cc, r, r
470 def FMOVQG : F4_7<2, 0b110101, 0b1010, 0b000011, "fmovqg">; // fmovqg cc, r, r
471 def FMOVQLE : F4_7<2, 0b110101, 0b0000, 0b000011, "fmovqle">; // fmovqle cc, r, r
472 def FMOVQGE : F4_7<2, 0b110101, 0b1011, 0b000011, "fmovqge">; // fmovqge cc, r, r
473 def FMOVQL : F4_7<2, 0b110101, 0b0011, 0b000011, "fmovql">; // fmovql cc, r, r
474 def FMOVQGU : F4_7<2, 0b110101, 0b1100, 0b000011, "fmovqgu">; // fmovqgu cc, r, r
475 def FMOVQLEU : F4_7<2, 0b110101, 0b0100, 0b000011, "fmovqleu">; // fmovqleu cc, r, r
476 def FMOVQCC : F4_7<2, 0b110101, 0b1101, 0b000011, "fmovqcc">; // fmovqcc cc, r, r
477 def FMOVQCS : F4_7<2, 0b110101, 0b0101, 0b000011, "fmovqcs">; // fmovqcs cc, r, r
478 def FMOVQPOS : F4_7<2, 0b110101, 0b1110, 0b000011, "fmovqpos">; // fmovqpos cc, r, r
479 def FMOVQNEG : F4_7<2, 0b110101, 0b0110, 0b000011, "fmovqneg">; // fmovqneg cc, r, r
480 def FMOVQVC : F4_7<2, 0b110101, 0b1111, 0b000011, "fmovqvc">; // fmovqvc cc, r, r
481 def FMOVQVS : F4_7<2, 0b110101, 0b0111, 0b000011, "fmovqvs">; // fmovqvs cc, r, r
483 // For floating-point condition codes
484 def FMOVQFA : F4_7<2, 0b110101, 0b0100, 0b000011, "fmovqfa">; // fmovqfa cc,r,r
485 def FMOVQFN : F4_7<2, 0b110101, 0b0000, 0b000011, "fmovqfn">; // fmovqfa cc,r,r
486 def FMOVQFU : F4_7<2, 0b110101, 0b0111, 0b000011, "fmovqfu">; // fmovqfu cc,r,r
487 def FMOVQFG : F4_7<2, 0b110101, 0b0110, 0b000011, "fmovqfg">; // fmovqfg cc,r,r
488 def FMOVQFUG : F4_7<2, 0b110101, 0b0101, 0b000011, "fmovqfug">; // fmovqfug cc,r,r
489 def FMOVQFL : F4_7<2, 0b110101, 0b0100, 0b000011, "fmovqfl">; // fmovqfl cc,r,r
490 def FMOVQFUL : F4_7<2, 0b110101, 0b0011, 0b000011, "fmovqful">; // fmovqful cc,r,r
491 def FMOVQFLG : F4_7<2, 0b110101, 0b0010, 0b000011, "fmovqflg">; // fmovqflg cc,r,r
492 def FMOVQFNE : F4_7<2, 0b110101, 0b0001, 0b000011, "fmovqfne">; // fmovqfne cc,r,r
493 def FMOVQFE : F4_7<2, 0b110101, 0b1001, 0b000011, "fmovqfe">; // fmovqfe cc,r,r
494 def FMOVQFUE : F4_7<2, 0b110101, 0b1010, 0b000011, "fmovqfue">; // fmovqfue cc,r,r
495 def FMOVQFGE : F4_7<2, 0b110101, 0b1011, 0b000011, "fmovqge">; // fmovqge cc,r,r
496 def FMOVQFUGE : F4_7<2, 0b110101, 0b1100, 0b000011, "fmovqfuge">;// fmovqfuge cc,r,r
497 def FMOVQFLE : F4_7<2, 0b110101, 0b1101, 0b000011, "fmovqfle">; // fmovqfle cc,r,r
498 def FMOVQFULE : F4_7<2, 0b110101, 0b1110, 0b000011, "fmovqfule">;// fmovqfule cc,r,r
499 def FMOVQFO : F4_7<2, 0b110101, 0b1111, 0b000011, "fmovqfo">; // fmovqfo cc,r,r
501 // Section A.34: Move FP Register on Integer Register condition (FMOVr) - p192
502 def FMOVRSZ : F4_6<2, 0b110101, 0b001, 0b00101, "fmovrsz">; //fmovsrz r,r,rd
503 def FMOVRSLEZ : F4_6<2, 0b110101, 0b010, 0b00101, "fmovrslez">;//fmovsrz r,r,rd
504 def FMOVRSLZ : F4_6<2, 0b110101, 0b011, 0b00101, "fmovrslz">; //fmovsrz r,r,rd
505 def FMOVRSNZ : F4_6<2, 0b110101, 0b101, 0b00101, "fmovrsne">; //fmovsrz r,r,rd
506 def FMOVRSGZ : F4_6<2, 0b110101, 0b110, 0b00101, "fmovrsgz">; //fmovsrz r,r,rd
507 def FMOVRSGEZ : F4_6<2, 0b110101, 0b111, 0b00101, "fmovrsgez">;//fmovsrz r,r,rd
509 def FMOVRDZ : F4_6<2, 0b110101, 0b001, 0b00110, "fmovrdz">; //fmovsrz r,r,rd
510 def FMOVRDLEZ : F4_6<2, 0b110101, 0b010, 0b00110, "fmovrdlez">;//fmovsrz r,r,rd
511 def FMOVRDLZ : F4_6<2, 0b110101, 0b011, 0b00110, "fmovrdlz">; //fmovsrz r,r,rd
512 def FMOVRDNZ : F4_6<2, 0b110101, 0b101, 0b00110, "fmovrdne">; //fmovsrz r,r,rd
513 def FMOVRDGZ : F4_6<2, 0b110101, 0b110, 0b00110, "fmovrdgz">; //fmovsrz r,r,rd
514 def FMOVRDGEZ : F4_6<2, 0b110101, 0b111, 0b00110, "fmovrdgez">;//fmovsrz r,r,rd
516 def FMOVRQZ : F4_6<2, 0b110101, 0b001, 0b00111, "fmovrqz">; //fmovsrz r,r,rd
517 def FMOVRQLEZ : F4_6<2, 0b110101, 0b010, 0b00111, "fmovrqlez">;//fmovsrz r,r,rd
518 def FMOVRQLZ : F4_6<2, 0b110101, 0b011, 0b00111, "fmovrqlz">; //fmovsrz r,r,rd
519 def FMOVRQNZ : F4_6<2, 0b110101, 0b101, 0b00111, "fmovrqne">; //fmovsrz r,r,rd
520 def FMOVRQGZ : F4_6<2, 0b110101, 0b110, 0b00111, "fmovrqgz">; //fmovsrz r,r,rd
521 def FMOVRQGEZ : F4_6<2, 0b110101, 0b111, 0b00111, "fmovrqgez">;//fmovsrz r,r,rd
524 // Section A.35: Move Integer Register on Condition (MOVcc) - p194
525 // For integer condition codes
526 def MOVAr : F4_3<2, 0b101100, 0b1000, "mova">; // mova i/xcc, rs2, rd
527 def MOVAi : F4_4<2, 0b101100, 0b1000, "mova">; // mova i/xcc, imm, rd
528 def MOVNr : F4_3<2, 0b101100, 0b0000, "movn">; // movn i/xcc, rs2, rd
529 def MOVNi : F4_4<2, 0b101100, 0b0000, "movn">; // movn i/xcc, imm, rd
530 def MOVNEr : F4_3<2, 0b101100, 0b1001, "movne">; // movne i/xcc, rs2, rd
531 def MOVNEi : F4_4<2, 0b101100, 0b1001, "movne">; // movne i/xcc, imm, rd
532 def MOVEr : F4_3<2, 0b101100, 0b0001, "move">; // move i/xcc, rs2, rd
533 def MOVEi : F4_4<2, 0b101100, 0b0001, "move">; // move i/xcc, imm, rd
534 def MOVGr : F4_3<2, 0b101100, 0b1010, "movg">; // movg i/xcc, rs2, rd
535 def MOVGi : F4_4<2, 0b101100, 0b1010, "movg">; // movg i/xcc, imm, rd
536 def MOVLEr : F4_3<2, 0b101100, 0b0010, "movle">; // movle i/xcc, rs2, rd
537 def MOVLEi : F4_4<2, 0b101100, 0b0010, "movle">; // movle i/xcc, imm, rd
538 def MOVGEr : F4_3<2, 0b101100, 0b1011, "movge">; // movge i/xcc, rs2, rd
539 def MOVGEi : F4_4<2, 0b101100, 0b1011, "movge">; // movge i/xcc, imm, rd
540 def MOVLr : F4_3<2, 0b101100, 0b0011, "movl">; // movl i/xcc, rs2, rd
541 def MOVLi : F4_4<2, 0b101100, 0b0011, "movl">; // movl i/xcc, imm, rd
542 def MOVGUr : F4_3<2, 0b101100, 0b1100, "movgu">; // movgu i/xcc, rs2, rd
543 def MOVGUi : F4_4<2, 0b101100, 0b1100, "movgu">; // movgu i/xcc, imm, rd
544 def MOVLEUr : F4_3<2, 0b101100, 0b0100, "movleu">; // movleu i/xcc, rs2, rd
545 def MOVLEUi : F4_4<2, 0b101100, 0b0100, "movleu">; // movleu i/xcc, imm, rd
546 def MOVCCr : F4_3<2, 0b101100, 0b1101, "movcc">; // movcc i/xcc, rs2, rd
547 def MOVCCi : F4_4<2, 0b101100, 0b1101, "movcc">; // movcc i/xcc, imm, rd
548 def MOVCSr : F4_3<2, 0b101100, 0b0101, "movcs">; // movcs i/xcc, rs2, rd
549 def MOVCSi : F4_4<2, 0b101100, 0b0101, "movcs">; // movcs i/xcc, imm, rd
550 def MOVPOSr : F4_3<2, 0b101100, 0b1110, "movpos">; // movpos i/xcc, rs2, rd
551 def MOVPOSi : F4_4<2, 0b101100, 0b1110, "movpos">; // movpos i/xcc, imm, rd
552 def MOVNEGr : F4_3<2, 0b101100, 0b0110, "movneg">; // movneg i/xcc, rs2, rd
553 def MOVNEGi : F4_4<2, 0b101100, 0b0110, "movneg">; // movneg i/xcc, imm, rd
554 def MOVVCr : F4_3<2, 0b101100, 0b1111, "movvc">; // movvc i/xcc, rs2, rd
555 def MOVVCi : F4_4<2, 0b101100, 0b1111, "movvc">; // movvc i/xcc, imm, rd
556 def MOVVSr : F4_3<2, 0b101100, 0b0111, "movvs">; // movvs i/xcc, rs2, rd
557 def MOVVSi : F4_4<2, 0b101100, 0b0111, "movvs">; // movvs i/xcc, imm, rd
559 // For floating-point condition codes
560 def MOVFAr : F4_3<2, 0b101100, 0b1000, "movfa">; // movfa i/xcc, rs2, rd
561 def MOVFAi : F4_4<2, 0b101100, 0b1000, "movfa">; // movfa i/xcc, imm, rd
562 def MOVFNr : F4_3<2, 0b101100, 0b0000, "movfn">; // movfn i/xcc, rs2, rd
563 def MOVFNi : F4_4<2, 0b101100, 0b0000, "movfn">; // movfn i/xcc, imm, rd
564 def MOVFUr : F4_3<2, 0b101100, 0b0111, "movfu">; // movfu i/xcc, rs2, rd
565 def MOVFUi : F4_4<2, 0b101100, 0b0111, "movfu">; // movfu i/xcc, imm, rd
566 def MOVFGr : F4_3<2, 0b101100, 0b0110, "movfg">; // movfg i/xcc, rs2, rd
567 def MOVFGi : F4_4<2, 0b101100, 0b0110, "movfg">; // movfg i/xcc, imm, rd
568 def MOVFUGr : F4_3<2, 0b101100, 0b0101, "movfug">; // movfug i/xcc, rs2, rd
569 def MOVFUGi : F4_4<2, 0b101100, 0b0101, "movfug">; // movfug i/xcc, imm, rd
570 def MOVFLr : F4_3<2, 0b101100, 0b0100, "movfl">; // movfl i/xcc, rs2, rd
571 def MOVFLi : F4_4<2, 0b101100, 0b0100, "movfl">; // movfl i/xcc, imm, rd
572 def MOVFULr : F4_3<2, 0b101100, 0b0011, "movful">; // movful i/xcc, rs2, rd
573 def MOVFULi : F4_4<2, 0b101100, 0b0011, "movful">; // movful i/xcc, imm, rd
574 def MOVFLGr : F4_3<2, 0b101100, 0b0010, "movflg">; // movflg i/xcc, rs2, rd
575 def MOVFLGi : F4_4<2, 0b101100, 0b0010, "movflg">; // movflg i/xcc, imm, rd
576 def MOVFNEr : F4_3<2, 0b101100, 0b0001, "movfne">; // movfne i/xcc, rs2, rd
577 def MOVFNEi : F4_4<2, 0b101100, 0b0001, "movfne">; // movfne i/xcc, imm, rd
578 def MOVFEr : F4_3<2, 0b101100, 0b1001, "movfe">; // movfe i/xcc, rs2, rd
579 def MOVFEi : F4_4<2, 0b101100, 0b1001, "movfe">; // movfe i/xcc, imm, rd
580 def MOVFUEr : F4_3<2, 0b101100, 0b1010, "movfue">; // movfue i/xcc, rs2, rd
581 def MOVFUEi : F4_4<2, 0b101100, 0b1010, "movfue">; // movfue i/xcc, imm, rd
582 def MOVFGEr : F4_3<2, 0b101100, 0b1011, "movfge">; // movfge i/xcc, rs2, rd
583 def MOVFGEi : F4_4<2, 0b101100, 0b1011, "movfge">; // movfge i/xcc, imm, rd
584 def MOVFUGEr : F4_3<2, 0b101100, 0b1100, "movfuge">; // movfuge i/xcc, rs2, rd
585 def MOVFUGEi : F4_4<2, 0b101100, 0b1100, "movfuge">; // movfuge i/xcc, imm, rd
586 def MOVFLEr : F4_3<2, 0b101100, 0b1101, "movfle">; // movfle i/xcc, rs2, rd
587 def MOVFLEi : F4_4<2, 0b101100, 0b1101, "movfle">; // movfle i/xcc, imm, rd
588 def MOVFULEr : F4_3<2, 0b101100, 0b1110, "movfule">; // movfule i/xcc, rs2, rd
589 def MOVFULEi : F4_4<2, 0b101100, 0b1110, "movfule">; // movfule i/xcc, imm, rd
590 def MOVFOr : F4_3<2, 0b101100, 0b1111, "movfo">; // movfo i/xcc, rs2, rd
591 def MOVFOi : F4_4<2, 0b101100, 0b1111, "movfo">; // movfo i/xcc, imm, rd
593 // Section A.36: Move Integer Register on Register Condition (MOVR) - p198
594 def MOVRZr : F3_5<2, 0b101111, 0b001, "movrz">; // movrz rs1, rs2, rd
595 def MOVRZi : F3_6<2, 0b101111, 0b001, "movrz">; // movrz rs1, imm, rd
596 def MOVRLEZr : F3_5<2, 0b101111, 0b010, "movrlez">; // movrlez rs1, rs2, rd
597 def MOVRLEZi : F3_6<2, 0b101111, 0b010, "movrlez">; // movrlez rs1, imm, rd
598 def MOVRLZr : F3_5<2, 0b101111, 0b011, "movrlz">; // movrlz rs1, rs2, rd
599 def MOVRLZi : F3_6<2, 0b101111, 0b011, "movrlz">; // movrlz rs1, imm, rd
600 def MOVRNZr : F3_5<2, 0b101111, 0b101, "movrnz">; // movrnz rs1, rs2, rd
601 def MOVRNZi : F3_6<2, 0b101111, 0b101, "movrnz">; // movrnz rs1, imm, rd
602 def MOVRGZr : F3_5<2, 0b101111, 0b110, "movrgz">; // movrgz rs1, rs2, rd
603 def MOVRGZi : F3_6<2, 0b101111, 0b110, "movrgz">; // movrgz rs1, imm, rd
604 def MOVRGEZr : F3_5<2, 0b101111, 0b111, "movrgez">; // movrgez rs1, rs2, rd
605 def MOVRGEZi : F3_6<2, 0b101111, 0b111, "movrgez">; // movrgez rs1, imm, rd
607 // Section A.37: Multiply and Divide (64-bit) - p199
608 def MULXr : F3_1<2, 0b001001, "mulx">; // mulx r, r, r
609 def MULXi : F3_2<2, 0b001001, "mulx">; // mulx r, i, r
610 def SDIVXr : F3_1<2, 0b101101, "sdivx">; // sdivx r, r, r
611 def SDIVXi : F3_2<2, 0b101101, "sdivx">; // sdivx r, i, r
612 def UDIVXr : F3_1<2, 0b001101, "udivx">; // udivx r, r, r
613 def UDIVXi : F3_2<2, 0b001101, "udivx">; // udivx r, i, r
615 // Section A.38: Multiply (32-bit) - p200
616 // Not used in the Sparc backend
618 let Inst{13} = 0 in {
619 def UMULr : F3_1<2, 0b001010, "umul">; // umul r, r, r
620 def SMULr : F3_1<2, 0b001011, "smul">; // smul r, r, r
621 def UMULCCr : F3_1<2, 0b011010, "umulcc">; // mulcc r, r, r
622 def SMULCCr : F3_1<2, 0b011011, "smulcc">; // smulcc r, r, r
624 let Inst{13} = 1 in {
625 def UMULi : F3_1<2, 0b001010, "umul">; // umul r, i, r
626 def SMULi : F3_1<2, 0b001011, "smul">; // smul r, i, r
627 def UMULCCi : F3_1<2, 0b011010, "umulcc">; // umulcc r, i, r
628 def SMULCCi : F3_1<2, 0b011011, "smulcc">; // smulcc r, i, r
632 // Section A.39: Multiply Step - p202
633 // Not currently used in the Sparc backend
635 // Section A.40: No operation - p204
636 // NOP is really a pseudo-instruction (special case of SETHI)
640 def NOP : F2_1<"nop">; // nop
645 // Section A.41: Population Count - p205
646 // Not currently used in the Sparc backend
648 // Section A.42: Prefetch Data - p206
649 // Not currently used in the Sparc backend
651 // Section A.43: Read Privileged Register - p211
652 // Not currently used in the Sparc backend
654 // Section A.44: Read State Register
655 // The only instr from this section currently used is RDCCR
657 def RDCCR : F3_17<2, 0b101000, "rd">; // rd %ccr, r
660 // Section A.45: RETURN - p216
661 let isReturn = 1 in {
662 def RETURNr : F3_3<2, 0b111001, "return">; // return
663 def RETURNi : F3_4<2, 0b111001, "return">; // return
666 // Section A.46: SAVE and RESTORE - p217
667 def SAVEr : F3_1<2, 0b111100, "save">; // save r, r, r
668 def SAVEi : F3_2<2, 0b111100, "save">; // save r, i, r
669 def RESTOREr : F3_1<2, 0b111101, "restore">; // restore r, r, r
670 def RESTOREi : F3_2<2, 0b111101, "restore">; // restore r, i, r
672 // Section A.47: SAVED and RESTORED - p219
673 // Not currently used in Sparc backend
675 // Section A.48: SETHI - p220
677 def SETHI : F2_1<"sethi">; // sethi
680 // Section A.49: Shift - p221
681 // Not currently used in the Sparc backend
683 uses 5 least significant bits of rs2
685 def SLLr5 : F3_11<2, 0b100101, "sll">; // sll r, r, r
686 def SRLr5 : F3_11<2, 0b100110, "srl">; // srl r, r, r
687 def SRAr5 : F3_11<2, 0b100111, "sra">; // sra r, r, r
688 def SLLXr5 : F3_11<2, 0b100101, "sllx">; // sllx r, r, r
689 def SRLXr5 : F3_11<2, 0b100110, "srlx">; // srlx r, r, r
690 def SRAXr5 : F3_11<2, 0b100111, "srax">; // srax r, r, r
694 // uses 6 least significant bits of rs2
696 def SLLr5 : F3_11<2, 0b100101, "sll">; // sll r, r, r
697 def SRLr5 : F3_11<2, 0b100110, "srl">; // srl r, r, r
698 def SRAr5 : F3_11<2, 0b100111, "sra">; // sra r, r, r
701 def SLLXr6 : F3_11<2, 0b100101, "sllx">; // sllx r, r, r
702 def SRLXr6 : F3_11<2, 0b100110, "srlx">; // srlx r, r, r
703 def SRAXr6 : F3_11<2, 0b100111, "srax">; // srax r, r, r
706 def SLLi5 : F3_12<2, 0b100101, "sll">; // sll r, shcnt32, r
707 def SRLi5 : F3_12<2, 0b100110, "srl">; // srl r, shcnt32, r
708 def SRAi5 : F3_12<2, 0b100111, "sra">; // sra r, shcnt32, r
709 def SLLXi6 : F3_13<2, 0b100101, "sllx">; // sllx r, shcnt64, r
710 def SRLXi6 : F3_13<2, 0b100110, "srlx">; // srlx r, shcnt64, r
711 def SRAXi6 : F3_13<2, 0b100111, "srax">; // srax r, shcnt64, r
713 // Section A.50: Sofware-Initiated Reset - p223
714 // Not currently used in the Sparc backend
716 // Section A.51: Store Barrier - p224
717 // Not currently used in the Sparc backend
719 // Section A.52: Store Floating-point - p225
720 // Store instructions all want their rd register first
721 def STFr : F3_1rd<3, 0b100100, "st">; // st r, [r+r]
722 def STFi : F3_2rd<3, 0b100100, "st">; // st r, [r+i]
723 def STDFr : F3_1rd<3, 0b100111, "std">; // std r, [r+r]
724 def STDFi : F3_2rd<3, 0b100111, "std">; // std r, [r+i]
726 // Not currently used in the Sparc backend
728 def STQFr : F3_1rd<3, 0b100110, "stq">; // stq r, [r+r]
729 def STQFi : F3_2rd<3, 0b100110, "stq">; // stq r, [r+i]
732 // FIXME: An encoding needs to be chosen here, because STFSRx expect rd=0,
733 // while STXFSRx expect rd=1, but assembly syntax dictates %fsr as first arg.
734 // These are being disabled because they aren't used in the Sparc backend.
736 let isDeprecated = 1 in {
737 def STFSRr : F3_1<3, 0b100101, "st">; // st %fsr, [r+r]
738 def STFSRi : F3_2<3, 0b100101, "st">; // st %fsr, [r+i]
741 def STXFSRr : F3_1<3, 0b100101, "stx">; // stx %fsr, [r+r]
742 def STXFSRi : F3_2<3, 0b100101, "stx">; // stx %fsr, [r+i]
744 // Section A.53: Store Floating-Point into Alternate Space - p227
745 // Not currently used in the Sparc backend
747 // Section A.54: Store Integer - p229
748 // Store instructions all want their rd register first
749 def STBr : F3_1rd<3, 0b000101, "stb">; // stb r, [r+r]
750 def STBi : F3_2rd<3, 0b000101, "stb">; // stb r, [r+i]
751 def STHr : F3_1rd<3, 0b000110, "sth">; // sth r, [r+r]
752 def STHi : F3_2rd<3, 0b000110, "sth">; // sth r, [r+i]
753 def STWr : F3_1rd<3, 0b000100, "stw">; // stw r, [r+r]
754 def STWi : F3_2rd<3, 0b000100, "stw">; // stw r, [r+i]
755 def STXr : F3_1rd<3, 0b001110, "stx">; // stx r, [r+r]
756 def STXi : F3_2rd<3, 0b001110, "stx">; // stx r, [r+i]
758 // Section A.55: Store Integer into Alternate Space - p231
759 // Not currently used in the Sparc backend
761 // Section A.56: Subtract - p233
762 def SUBr : F3_1<2, 0b000100, "sub">; // sub r, r, r
763 def SUBi : F3_2<2, 0b000100, "sub">; // sub r, i, r
764 def SUBccr : F3_1<2, 0b010100, "subcc">; // subcc r, r, r
765 def SUBcci : F3_2<2, 0b010100, "subcc">; // subcc r, i, r
766 def SUBCr : F3_1<2, 0b001100, "subc">; // subc r, r, r
767 def SUBCi : F3_2<2, 0b001100, "subc">; // subc r, i, r
768 def SUBCccr : F3_1<2, 0b011100, "subccc">; // subccc r, r, r
769 def SUBCcci : F3_2<2, 0b011100, "subccc">; // subccc r, i, r
773 // Section A.63: Write State Register - p244
775 def WRCCRr : F3_1<2, 0b110000, "wr">; // wr r, r, %y/ccr/etc
776 def WRCCRi : F3_2<2, 0b110000, "wr">; // wr r, i, %y/ccr/etc