1 //===-- PhyRegAlloc.cpp ---------------------------------------------------===//
3 // Register allocation for LLVM.
5 //===----------------------------------------------------------------------===//
7 #include "llvm/CodeGen/RegisterAllocation.h"
8 #include "llvm/CodeGen/RegAllocCommon.h"
9 #include "llvm/CodeGen/IGNode.h"
10 #include "llvm/CodeGen/PhyRegAlloc.h"
11 #include "llvm/CodeGen/MachineInstrBuilder.h"
12 #include "llvm/CodeGen/MachineInstrAnnot.h"
13 #include "llvm/CodeGen/MachineFunction.h"
14 #include "llvm/CodeGen/MachineFunctionInfo.h"
15 #include "llvm/CodeGen/FunctionLiveVarInfo.h"
16 #include "llvm/Analysis/LoopInfo.h"
17 #include "llvm/Target/TargetMachine.h"
18 #include "llvm/Target/TargetFrameInfo.h"
19 #include "llvm/Target/TargetInstrInfo.h"
20 #include "llvm/Function.h"
21 #include "llvm/Type.h"
22 #include "llvm/iOther.h"
23 #include "Support/STLExtras.h"
24 #include "Support/CommandLine.h"
29 RegAllocDebugLevel_t DEBUG_RA;
31 static cl::opt<RegAllocDebugLevel_t, true>
32 DRA_opt("dregalloc", cl::Hidden, cl::location(DEBUG_RA),
33 cl::desc("enable register allocation debugging information"),
35 clEnumValN(RA_DEBUG_None , "n", "disable debug output"),
36 clEnumValN(RA_DEBUG_Results, "y", "debug output for allocation results"),
37 clEnumValN(RA_DEBUG_Coloring, "c", "debug output for graph coloring step"),
38 clEnumValN(RA_DEBUG_Interference,"ig","debug output for interference graphs"),
39 clEnumValN(RA_DEBUG_LiveRanges , "lr","debug output for live ranges"),
40 clEnumValN(RA_DEBUG_Verbose, "v", "extra debug output"),
43 //----------------------------------------------------------------------------
44 // RegisterAllocation pass front end...
45 //----------------------------------------------------------------------------
47 class RegisterAllocator : public FunctionPass {
48 TargetMachine &Target;
50 inline RegisterAllocator(TargetMachine &T) : Target(T) {}
52 const char *getPassName() const { return "Register Allocation"; }
54 bool runOnFunction(Function &F) {
56 cerr << "\n********* Function "<< F.getName() << " ***********\n";
58 PhyRegAlloc PRA(&F, Target, &getAnalysis<FunctionLiveVarInfo>(),
59 &getAnalysis<LoopInfo>());
60 PRA.allocateRegisters();
62 if (DEBUG_RA) cerr << "\nRegister allocation complete!\n";
66 virtual void getAnalysisUsage(AnalysisUsage &AU) const {
67 AU.addRequired<LoopInfo>();
68 AU.addRequired<FunctionLiveVarInfo>();
73 Pass *getRegisterAllocator(TargetMachine &T) {
74 return new RegisterAllocator(T);
77 //----------------------------------------------------------------------------
78 // Constructor: Init local composite objects and create register classes.
79 //----------------------------------------------------------------------------
80 PhyRegAlloc::PhyRegAlloc(Function *F, const TargetMachine& tm,
81 FunctionLiveVarInfo *Lvi, LoopInfo *LDC)
82 : TM(tm), Fn(F), MF(MachineFunction::get(F)), LVI(Lvi),
83 LRI(F, tm, RegClassList), MRI(tm.getRegInfo()),
84 NumOfRegClasses(MRI.getNumOfRegClasses()), LoopDepthCalc(LDC) {
86 // create each RegisterClass and put in RegClassList
88 for (unsigned rc=0; rc != NumOfRegClasses; rc++)
89 RegClassList.push_back(new RegClass(F, MRI.getMachineRegClass(rc),
94 //----------------------------------------------------------------------------
95 // Destructor: Deletes register classes
96 //----------------------------------------------------------------------------
97 PhyRegAlloc::~PhyRegAlloc() {
98 for ( unsigned rc=0; rc < NumOfRegClasses; rc++)
99 delete RegClassList[rc];
101 AddedInstrMap.clear();
104 //----------------------------------------------------------------------------
105 // This method initally creates interference graphs (one in each reg class)
106 // and IGNodeList (one in each IG). The actual nodes will be pushed later.
107 //----------------------------------------------------------------------------
108 void PhyRegAlloc::createIGNodeListsAndIGs() {
109 if (DEBUG_RA >= RA_DEBUG_LiveRanges) cerr << "Creating LR lists ...\n";
112 LiveRangeMapType::const_iterator HMI = LRI.getLiveRangeMap()->begin();
115 LiveRangeMapType::const_iterator HMIEnd = LRI.getLiveRangeMap()->end();
117 for (; HMI != HMIEnd ; ++HMI ) {
119 LiveRange *L = HMI->second; // get the LiveRange
122 cerr << "\n**** ?!?WARNING: NULL LIVE RANGE FOUND FOR: "
123 << RAV(HMI->first) << "****\n";
127 // if the Value * is not null, and LR is not yet written to the IGNodeList
128 if (!(L->getUserIGNode()) ) {
129 RegClass *const RC = // RegClass of first value in the LR
130 RegClassList[ L->getRegClass()->getID() ];
131 RC->addLRToIG(L); // add this LR to an IG
137 for ( unsigned rc=0; rc < NumOfRegClasses ; rc++)
138 RegClassList[rc]->createInterferenceGraph();
140 if (DEBUG_RA >= RA_DEBUG_LiveRanges) cerr << "LRLists Created!\n";
144 //----------------------------------------------------------------------------
145 // This method will add all interferences at for a given instruction.
146 // Interence occurs only if the LR of Def (Inst or Arg) is of the same reg
147 // class as that of live var. The live var passed to this function is the
148 // LVset AFTER the instruction
149 //----------------------------------------------------------------------------
151 void PhyRegAlloc::addInterference(const Value *Def,
152 const ValueSet *LVSet,
155 ValueSet::const_iterator LIt = LVSet->begin();
157 // get the live range of instruction
159 const LiveRange *const LROfDef = LRI.getLiveRangeForValue( Def );
161 IGNode *const IGNodeOfDef = LROfDef->getUserIGNode();
162 assert( IGNodeOfDef );
164 RegClass *const RCOfDef = LROfDef->getRegClass();
166 // for each live var in live variable set
168 for ( ; LIt != LVSet->end(); ++LIt) {
170 if (DEBUG_RA >= RA_DEBUG_Verbose)
171 cerr << "< Def=" << RAV(Def) << ", Lvar=" << RAV(*LIt) << "> ";
173 // get the live range corresponding to live var
175 LiveRange *LROfVar = LRI.getLiveRangeForValue(*LIt);
177 // LROfVar can be null if it is a const since a const
178 // doesn't have a dominating def - see Assumptions above
181 if (LROfDef != LROfVar) // do not set interf for same LR
182 if (RCOfDef == LROfVar->getRegClass()) // 2 reg classes are the same
183 RCOfDef->setInterference( LROfDef, LROfVar);
189 //----------------------------------------------------------------------------
190 // For a call instruction, this method sets the CallInterference flag in
191 // the LR of each variable live int the Live Variable Set live after the
192 // call instruction (except the return value of the call instruction - since
193 // the return value does not interfere with that call itself).
194 //----------------------------------------------------------------------------
196 void PhyRegAlloc::setCallInterferences(const MachineInstr *MInst,
197 const ValueSet *LVSetAft) {
199 if (DEBUG_RA >= RA_DEBUG_Interference)
200 cerr << "\n For call inst: " << *MInst;
202 ValueSet::const_iterator LIt = LVSetAft->begin();
204 // for each live var in live variable set after machine inst
206 for ( ; LIt != LVSetAft->end(); ++LIt) {
208 // get the live range corresponding to live var
210 LiveRange *const LR = LRI.getLiveRangeForValue(*LIt );
212 // LR can be null if it is a const since a const
213 // doesn't have a dominating def - see Assumptions above
216 if (DEBUG_RA >= RA_DEBUG_Interference) {
217 cerr << "\n\tLR after Call: ";
220 LR->setCallInterference();
221 if (DEBUG_RA >= RA_DEBUG_Interference) {
222 cerr << "\n ++After adding call interference for LR: " ;
229 // Now find the LR of the return value of the call
230 // We do this because, we look at the LV set *after* the instruction
231 // to determine, which LRs must be saved across calls. The return value
232 // of the call is live in this set - but it does not interfere with call
233 // (i.e., we can allocate a volatile register to the return value)
235 CallArgsDescriptor* argDesc = CallArgsDescriptor::get(MInst);
237 if (const Value *RetVal = argDesc->getReturnValue()) {
238 LiveRange *RetValLR = LRI.getLiveRangeForValue( RetVal );
239 assert( RetValLR && "No LR for RetValue of call");
240 RetValLR->clearCallInterference();
243 // If the CALL is an indirect call, find the LR of the function pointer.
244 // That has a call interference because it conflicts with outgoing args.
245 if (const Value *AddrVal = argDesc->getIndirectFuncPtr()) {
246 LiveRange *AddrValLR = LRI.getLiveRangeForValue( AddrVal );
247 assert( AddrValLR && "No LR for indirect addr val of call");
248 AddrValLR->setCallInterference();
256 //----------------------------------------------------------------------------
257 // This method will walk thru code and create interferences in the IG of
258 // each RegClass. Also, this method calculates the spill cost of each
259 // Live Range (it is done in this method to save another pass over the code).
260 //----------------------------------------------------------------------------
261 void PhyRegAlloc::buildInterferenceGraphs()
264 if (DEBUG_RA >= RA_DEBUG_Interference)
265 cerr << "Creating interference graphs ...\n";
267 unsigned BBLoopDepthCost;
268 for (MachineFunction::iterator BBI = MF.begin(), BBE = MF.end();
270 const MachineBasicBlock &MBB = *BBI;
271 const BasicBlock *BB = MBB.getBasicBlock();
273 // find the 10^(loop_depth) of this BB
275 BBLoopDepthCost = (unsigned)pow(10.0, LoopDepthCalc->getLoopDepth(BB));
277 // get the iterator for machine instructions
279 MachineBasicBlock::const_iterator MII = MBB.begin();
281 // iterate over all the machine instructions in BB
283 for ( ; MII != MBB.end(); ++MII) {
284 const MachineInstr *MInst = *MII;
286 // get the LV set after the instruction
288 const ValueSet &LVSetAI = LVI->getLiveVarSetAfterMInst(MInst, BB);
289 bool isCallInst = TM.getInstrInfo().isCall(MInst->getOpCode());
292 // set the isCallInterference flag of each live range wich extends
293 // accross this call instruction. This information is used by graph
294 // coloring algo to avoid allocating volatile colors to live ranges
295 // that span across calls (since they have to be saved/restored)
297 setCallInterferences(MInst, &LVSetAI);
300 // iterate over all MI operands to find defs
302 for (MachineInstr::const_val_op_iterator OpI = MInst->begin(),
303 OpE = MInst->end(); OpI != OpE; ++OpI) {
304 if (OpI.isDef()) // create a new LR iff this operand is a def
305 addInterference(*OpI, &LVSetAI, isCallInst);
307 // Calculate the spill cost of each live range
309 LiveRange *LR = LRI.getLiveRangeForValue(*OpI);
310 if (LR) LR->addSpillCost(BBLoopDepthCost);
314 // if there are multiple defs in this instruction e.g. in SETX
316 if (TM.getInstrInfo().isPseudoInstr(MInst->getOpCode()))
317 addInterf4PseudoInstr(MInst);
320 // Also add interference for any implicit definitions in a machine
321 // instr (currently, only calls have this).
323 unsigned NumOfImpRefs = MInst->getNumImplicitRefs();
324 if ( NumOfImpRefs > 0 ) {
325 for (unsigned z=0; z < NumOfImpRefs; z++)
326 if (MInst->implicitRefIsDefined(z) )
327 addInterference( MInst->getImplicitRef(z), &LVSetAI, isCallInst );
331 } // for all machine instructions in BB
332 } // for all BBs in function
335 // add interferences for function arguments. Since there are no explict
336 // defs in the function for args, we have to add them manually
338 addInterferencesForArgs();
340 if (DEBUG_RA >= RA_DEBUG_Interference)
341 cerr << "Interference graphs calculated!\n";
346 //--------------------------------------------------------------------------
347 // Pseudo instructions will be exapnded to multiple instructions by the
348 // assembler. Consequently, all the opernds must get distinct registers.
349 // Therefore, we mark all operands of a pseudo instruction as they interfere
351 //--------------------------------------------------------------------------
352 void PhyRegAlloc::addInterf4PseudoInstr(const MachineInstr *MInst) {
354 bool setInterf = false;
356 // iterate over MI operands to find defs
358 for (MachineInstr::const_val_op_iterator It1 = MInst->begin(),
359 ItE = MInst->end(); It1 != ItE; ++It1) {
360 const LiveRange *LROfOp1 = LRI.getLiveRangeForValue(*It1);
361 assert((LROfOp1 || !It1.isDef()) && "No LR for Def in PSEUDO insruction");
363 MachineInstr::const_val_op_iterator It2 = It1;
364 for (++It2; It2 != ItE; ++It2) {
365 const LiveRange *LROfOp2 = LRI.getLiveRangeForValue(*It2);
368 RegClass *RCOfOp1 = LROfOp1->getRegClass();
369 RegClass *RCOfOp2 = LROfOp2->getRegClass();
371 if (RCOfOp1 == RCOfOp2 ){
372 RCOfOp1->setInterference( LROfOp1, LROfOp2 );
376 } // for all other defs in machine instr
377 } // for all operands in an instruction
379 if (!setInterf && MInst->getNumOperands() > 2) {
380 cerr << "\nInterf not set for any operand in pseudo instr:\n";
382 assert(0 && "Interf not set for pseudo instr with > 2 operands" );
388 //----------------------------------------------------------------------------
389 // This method will add interferences for incoming arguments to a function.
390 //----------------------------------------------------------------------------
392 void PhyRegAlloc::addInterferencesForArgs() {
393 // get the InSet of root BB
394 const ValueSet &InSet = LVI->getInSetOfBB(&Fn->front());
396 for (Function::const_aiterator AI = Fn->abegin(); AI != Fn->aend(); ++AI) {
397 // add interferences between args and LVars at start
398 addInterference(AI, &InSet, false);
400 if (DEBUG_RA >= RA_DEBUG_Interference)
401 cerr << " - %% adding interference for argument " << RAV(AI) << "\n";
406 //----------------------------------------------------------------------------
407 // This method is called after register allocation is complete to set the
408 // allocated reisters in the machine code. This code will add register numbers
409 // to MachineOperands that contain a Value. Also it calls target specific
410 // methods to produce caller saving instructions. At the end, it adds all
411 // additional instructions produced by the register allocator to the
412 // instruction stream.
413 //----------------------------------------------------------------------------
415 //-----------------------------
416 // Utility functions used below
417 //-----------------------------
419 InsertBefore(MachineInstr* newMI,
420 MachineBasicBlock& MBB,
421 MachineBasicBlock::iterator& MII)
423 MII = MBB.insert(MII, newMI);
428 InsertAfter(MachineInstr* newMI,
429 MachineBasicBlock& MBB,
430 MachineBasicBlock::iterator& MII)
432 ++MII; // insert before the next instruction
433 MII = MBB.insert(MII, newMI);
437 SubstituteInPlace(MachineInstr* newMI,
438 MachineBasicBlock& MBB,
439 MachineBasicBlock::iterator MII)
445 PrependInstructions(vector<MachineInstr *> &IBef,
446 MachineBasicBlock& MBB,
447 MachineBasicBlock::iterator& MII,
448 const std::string& msg)
452 MachineInstr* OrigMI = *MII;
453 std::vector<MachineInstr *>::iterator AdIt;
454 for (AdIt = IBef.begin(); AdIt != IBef.end() ; ++AdIt)
457 if (OrigMI) cerr << "For MInst:\n " << *OrigMI;
458 cerr << msg << "PREPENDed instr:\n " << **AdIt << "\n";
460 InsertBefore(*AdIt, MBB, MII);
466 AppendInstructions(std::vector<MachineInstr *> &IAft,
467 MachineBasicBlock& MBB,
468 MachineBasicBlock::iterator& MII,
469 const std::string& msg)
473 MachineInstr* OrigMI = *MII;
474 std::vector<MachineInstr *>::iterator AdIt;
475 for ( AdIt = IAft.begin(); AdIt != IAft.end() ; ++AdIt )
478 if (OrigMI) cerr << "For MInst:\n " << *OrigMI;
479 cerr << msg << "APPENDed instr:\n " << **AdIt << "\n";
481 InsertAfter(*AdIt, MBB, MII);
487 void PhyRegAlloc::updateMachineCode() {
488 // Insert any instructions needed at method entry
489 MachineBasicBlock::iterator MII = MF.front().begin();
490 PrependInstructions(AddedInstrAtEntry.InstrnsBefore, MF.front(), MII,
491 "At function entry: \n");
492 assert(AddedInstrAtEntry.InstrnsAfter.empty() &&
493 "InstrsAfter should be unnecessary since we are just inserting at "
494 "the function entry point here.");
496 for (MachineFunction::iterator BBI = MF.begin(), BBE = MF.end();
499 // iterate over all the machine instructions in BB
500 MachineBasicBlock &MBB = *BBI;
501 for (MachineBasicBlock::iterator MII = MBB.begin();
502 MII != MBB.end(); ++MII) {
504 MachineInstr *MInst = *MII;
505 unsigned Opcode = MInst->getOpCode();
507 // do not process Phis
508 if (TM.getInstrInfo().isDummyPhiInstr(Opcode))
511 // Reset tmp stack positions so they can be reused for each machine instr.
512 MF.getInfo()->popAllTempValues();
514 // Now insert speical instructions (if necessary) for call/return
517 if (TM.getInstrInfo().isCall(Opcode) ||
518 TM.getInstrInfo().isReturn(Opcode)) {
519 AddedInstrns &AI = AddedInstrMap[MInst];
521 if (TM.getInstrInfo().isCall(Opcode))
522 MRI.colorCallArgs(MInst, LRI, &AI, *this, MBB.getBasicBlock());
523 else if (TM.getInstrInfo().isReturn(Opcode))
524 MRI.colorRetValue(MInst, LRI, &AI);
527 // Set the registers for operands in the machine instruction
528 // if a register was successfully allocated. If not, insert
529 // code to spill the register value.
531 for (unsigned OpNum=0; OpNum < MInst->getNumOperands(); ++OpNum)
533 MachineOperand& Op = MInst->getOperand(OpNum);
534 if (Op.getType() == MachineOperand::MO_VirtualRegister ||
535 Op.getType() == MachineOperand::MO_CCRegister)
537 const Value *const Val = Op.getVRegValue();
539 LiveRange *const LR = LRI.getLiveRangeForValue(Val);
540 if (!LR) // consts or labels will have no live range
542 // if register is not allocated, mark register as invalid
543 if (Op.getAllocatedRegNum() == -1)
544 MInst->SetRegForOperand(OpNum, MRI.getInvalidRegNum());
549 MInst->SetRegForOperand(OpNum,
550 MRI.getUnifiedRegNum(LR->getRegClass()->getID(),
553 // LR did NOT receive a color (register). Insert spill code.
554 insertCode4SpilledLR(LR, MInst, MBB.getBasicBlock(), OpNum);
556 } // for each operand
558 // Now add instructions that the register allocator inserts before/after
559 // this machine instructions (done only for calls/rets/incoming args)
560 // We do this here, to ensure that spill for an instruction is inserted
561 // closest as possible to an instruction (see above insertCode4Spill...)
563 // First, if the instruction in the delay slot of a branch needs
564 // instructions inserted, move it out of the delay slot and before the
565 // branch because putting code before or after it would be VERY BAD!
567 unsigned bumpIteratorBy = 0;
568 if (MII != MBB.begin())
569 if (unsigned predDelaySlots =
570 TM.getInstrInfo().getNumDelaySlots((*(MII-1))->getOpCode()))
572 assert(predDelaySlots==1 && "Not handling multiple delay slots!");
573 if (TM.getInstrInfo().isBranch((*(MII-1))->getOpCode())
574 && (AddedInstrMap.count(MInst) ||
575 AddedInstrMap[MInst].InstrnsAfter.size() > 0))
577 // Current instruction is in the delay slot of a branch and it
578 // needs spill code inserted before or after it.
579 // Move it before the preceding branch.
580 InsertBefore(MInst, MBB, --MII);
581 MachineInstr* nopI = BuildMI(TM.getInstrInfo().getNOPOpCode(),1);
582 SubstituteInPlace(nopI, MBB, MII+1); // replace orig with NOP
583 --MII; // point to MInst in new location
584 bumpIteratorBy = 2; // later skip the branch and the NOP!
588 // If there are instructions to be added, *before* this machine
589 // instruction, add them now.
591 if (AddedInstrMap.count(MInst)) {
592 PrependInstructions(AddedInstrMap[MInst].InstrnsBefore, MBB, MII,"");
595 // If there are instructions to be added *after* this machine
596 // instruction, add them now
598 if (!AddedInstrMap[MInst].InstrnsAfter.empty()) {
600 // if there are delay slots for this instruction, the instructions
601 // added after it must really go after the delayed instruction(s)
602 // So, we move the InstrAfter of the current instruction to the
603 // corresponding delayed instruction
605 TM.getInstrInfo().getNumDelaySlots(MInst->getOpCode())) {
607 // Delayed instructions are typically branches or calls. Let's make
608 // sure this is not a branch, otherwise "insert-after" is meaningless,
609 // and should never happen for any reason (spill code, register
611 assert(! TM.getInstrInfo().isBranch(MInst->getOpCode()) &&
612 ! TM.getInstrInfo().isReturn(MInst->getOpCode()) &&
613 "INTERNAL ERROR: Register allocator should not be inserting "
614 "any code after a branch or return!");
616 move2DelayedInstr(MInst, *(MII+delay) );
619 // Here we can add the "instructions after" to the current
620 // instruction since there are no delay slots for this instruction
621 AppendInstructions(AddedInstrMap[MInst].InstrnsAfter, MBB, MII,"");
625 // If we mucked with the instruction order above, adjust the loop iterator
627 MII = MII + bumpIteratorBy;
629 } // for each machine instruction
635 //----------------------------------------------------------------------------
636 // This method inserts spill code for AN operand whose LR was spilled.
637 // This method may be called several times for a single machine instruction
638 // if it contains many spilled operands. Each time it is called, it finds
639 // a register which is not live at that instruction and also which is not
640 // used by other spilled operands of the same instruction. Then it uses
641 // this register temporarily to accomodate the spilled value.
642 //----------------------------------------------------------------------------
643 void PhyRegAlloc::insertCode4SpilledLR(const LiveRange *LR,
645 const BasicBlock *BB,
646 const unsigned OpNum) {
648 assert((! TM.getInstrInfo().isCall(MInst->getOpCode()) || OpNum == 0) &&
649 "Outgoing arg of a call must be handled elsewhere (func arg ok)");
650 assert(! TM.getInstrInfo().isReturn(MInst->getOpCode()) &&
651 "Return value of a ret must be handled elsewhere");
653 MachineOperand& Op = MInst->getOperand(OpNum);
654 bool isDef = MInst->operandIsDefined(OpNum);
655 bool isDefAndUse = MInst->operandIsDefinedAndUsed(OpNum);
656 unsigned RegType = MRI.getRegType( LR );
657 int SpillOff = LR->getSpillOffFromFP();
658 RegClass *RC = LR->getRegClass();
659 const ValueSet &LVSetBef = LVI->getLiveVarSetBeforeMInst(MInst, BB);
661 MF.getInfo()->pushTempValue(MRI.getSpilledRegSize(RegType) );
663 vector<MachineInstr*> MIBef, MIAft;
664 vector<MachineInstr*> AdIMid;
666 // Choose a register to hold the spilled value. This may insert code
667 // before and after MInst to free up the value. If so, this code should
668 // be first and last in the spill sequence before/after MInst.
669 int TmpRegU = getUsableUniRegAtMI(RegType, &LVSetBef, MInst, MIBef, MIAft);
671 // Set the operand first so that it this register does not get used
672 // as a scratch register for later calls to getUsableUniRegAtMI below
673 MInst->SetRegForOperand(OpNum, TmpRegU);
675 // get the added instructions for this instruction
676 AddedInstrns &AI = AddedInstrMap[MInst];
678 // We may need a scratch register to copy the spilled value to/from memory.
679 // This may itself have to insert code to free up a scratch register.
680 // Any such code should go before (after) the spill code for a load (store).
681 int scratchRegType = -1;
683 if (MRI.regTypeNeedsScratchReg(RegType, scratchRegType))
685 scratchReg = getUsableUniRegAtMI(scratchRegType, &LVSetBef,
686 MInst, MIBef, MIAft);
687 assert(scratchReg != MRI.getInvalidRegNum());
688 MInst->insertUsedReg(scratchReg);
691 if (!isDef || isDefAndUse) {
692 // for a USE, we have to load the value of LR from stack to a TmpReg
693 // and use the TmpReg as one operand of instruction
695 // actual loading instruction(s)
696 MRI.cpMem2RegMI(AdIMid, MRI.getFramePointer(), SpillOff, TmpRegU, RegType,
699 // the actual load should be after the instructions to free up TmpRegU
700 MIBef.insert(MIBef.end(), AdIMid.begin(), AdIMid.end());
704 if (isDef) { // if this is a Def
705 // for a DEF, we have to store the value produced by this instruction
706 // on the stack position allocated for this LR
708 // actual storing instruction(s)
709 MRI.cpReg2MemMI(AdIMid, TmpRegU, MRI.getFramePointer(), SpillOff, RegType,
712 MIAft.insert(MIAft.begin(), AdIMid.begin(), AdIMid.end());
715 // Finally, insert the entire spill code sequences before/after MInst
716 AI.InstrnsBefore.insert(AI.InstrnsBefore.end(), MIBef.begin(), MIBef.end());
717 AI.InstrnsAfter.insert(AI.InstrnsAfter.begin(), MIAft.begin(), MIAft.end());
720 cerr << "\nFor Inst:\n " << *MInst;
721 cerr << "SPILLED LR# " << LR->getUserIGNode()->getIndex();
722 cerr << "; added Instructions:";
723 for_each(MIBef.begin(), MIBef.end(), std::mem_fun(&MachineInstr::dump));
724 for_each(MIAft.begin(), MIAft.end(), std::mem_fun(&MachineInstr::dump));
729 //----------------------------------------------------------------------------
730 // We can use the following method to get a temporary register to be used
731 // BEFORE any given machine instruction. If there is a register available,
732 // this method will simply return that register and set MIBef = MIAft = NULL.
733 // Otherwise, it will return a register and MIAft and MIBef will contain
734 // two instructions used to free up this returned register.
735 // Returned register number is the UNIFIED register number
736 //----------------------------------------------------------------------------
738 int PhyRegAlloc::getUsableUniRegAtMI(const int RegType,
739 const ValueSet *LVSetBef,
741 std::vector<MachineInstr*>& MIBef,
742 std::vector<MachineInstr*>& MIAft) {
744 RegClass* RC = getRegClassByID(MRI.getRegClassIDOfRegType(RegType));
746 int RegU = getUnusedUniRegAtMI(RC, MInst, LVSetBef);
749 // we couldn't find an unused register. Generate code to free up a reg by
750 // saving it on stack and restoring after the instruction
752 int TmpOff = MF.getInfo()->pushTempValue(MRI.getSpilledRegSize(RegType));
754 RegU = getUniRegNotUsedByThisInst(RC, MInst);
756 // Check if we need a scratch register to copy this register to memory.
757 int scratchRegType = -1;
758 if (MRI.regTypeNeedsScratchReg(RegType, scratchRegType))
760 int scratchReg = getUsableUniRegAtMI(scratchRegType, LVSetBef,
761 MInst, MIBef, MIAft);
762 assert(scratchReg != MRI.getInvalidRegNum());
764 // We may as well hold the value in the scratch register instead
765 // of copying it to memory and back. But we have to mark the
766 // register as used by this instruction, so it does not get used
767 // as a scratch reg. by another operand or anyone else.
768 MInst->insertUsedReg(scratchReg);
769 MRI.cpReg2RegMI(MIBef, RegU, scratchReg, RegType);
770 MRI.cpReg2RegMI(MIAft, scratchReg, RegU, RegType);
773 { // the register can be copied directly to/from memory so do it.
774 MRI.cpReg2MemMI(MIBef, RegU, MRI.getFramePointer(), TmpOff, RegType);
775 MRI.cpMem2RegMI(MIAft, MRI.getFramePointer(), TmpOff, RegU, RegType);
782 //----------------------------------------------------------------------------
783 // This method is called to get a new unused register that can be used to
784 // accomodate a spilled value.
785 // This method may be called several times for a single machine instruction
786 // if it contains many spilled operands. Each time it is called, it finds
787 // a register which is not live at that instruction and also which is not
788 // used by other spilled operands of the same instruction.
789 // Return register number is relative to the register class. NOT
791 //----------------------------------------------------------------------------
792 int PhyRegAlloc::getUnusedUniRegAtMI(RegClass *RC,
793 const MachineInstr *MInst,
794 const ValueSet *LVSetBef) {
796 unsigned NumAvailRegs = RC->getNumOfAvailRegs();
798 std::vector<bool> &IsColorUsedArr = RC->getIsColorUsedArr();
800 for (unsigned i=0; i < NumAvailRegs; i++) // Reset array
801 IsColorUsedArr[i] = false;
803 ValueSet::const_iterator LIt = LVSetBef->begin();
805 // for each live var in live variable set after machine inst
806 for ( ; LIt != LVSetBef->end(); ++LIt) {
808 // get the live range corresponding to live var
809 LiveRange *const LRofLV = LRI.getLiveRangeForValue(*LIt );
811 // LR can be null if it is a const since a const
812 // doesn't have a dominating def - see Assumptions above
813 if (LRofLV && LRofLV->getRegClass() == RC && LRofLV->hasColor() )
814 IsColorUsedArr[ LRofLV->getColor() ] = true;
817 // It is possible that one operand of this MInst was already spilled
818 // and it received some register temporarily. If that's the case,
819 // it is recorded in machine operand. We must skip such registers.
821 setRelRegsUsedByThisInst(RC, MInst);
823 for (unsigned c=0; c < NumAvailRegs; c++) // find first unused color
824 if (!IsColorUsedArr[c])
825 return MRI.getUnifiedRegNum(RC->getID(), c);
831 //----------------------------------------------------------------------------
832 // Get any other register in a register class, other than what is used
833 // by operands of a machine instruction. Returns the unified reg number.
834 //----------------------------------------------------------------------------
835 int PhyRegAlloc::getUniRegNotUsedByThisInst(RegClass *RC,
836 const MachineInstr *MInst) {
838 vector<bool> &IsColorUsedArr = RC->getIsColorUsedArr();
839 unsigned NumAvailRegs = RC->getNumOfAvailRegs();
841 for (unsigned i=0; i < NumAvailRegs ; i++) // Reset array
842 IsColorUsedArr[i] = false;
844 setRelRegsUsedByThisInst(RC, MInst);
846 for (unsigned c=0; c < RC->getNumOfAvailRegs(); c++)// find first unused color
847 if (!IsColorUsedArr[c])
848 return MRI.getUnifiedRegNum(RC->getID(), c);
850 assert(0 && "FATAL: No free register could be found in reg class!!");
855 //----------------------------------------------------------------------------
856 // This method modifies the IsColorUsedArr of the register class passed to it.
857 // It sets the bits corresponding to the registers used by this machine
858 // instructions. Both explicit and implicit operands are set.
859 //----------------------------------------------------------------------------
860 void PhyRegAlloc::setRelRegsUsedByThisInst(RegClass *RC,
861 const MachineInstr *MInst ) {
863 vector<bool> &IsColorUsedArr = RC->getIsColorUsedArr();
865 // Add the registers already marked as used by the instruction.
866 // This should include any scratch registers that are used to save
867 // values across the instruction (e.g., for saving state register values).
868 const vector<bool> ®sUsed = MInst->getRegsUsed();
869 for (unsigned i = 0, e = regsUsed.size(); i != e; ++i)
871 unsigned classId = 0;
872 int classRegNum = MRI.getClassRegNum(i, classId);
873 if (RC->getID() == classId)
875 assert(classRegNum < (int) IsColorUsedArr.size() &&
876 "Illegal register number for this reg class?");
877 IsColorUsedArr[classRegNum] = true;
881 // Now add registers allocated to the live ranges of values used in
882 // the instruction. These are not yet recorded in the instruction.
883 for (unsigned OpNum=0; OpNum < MInst->getNumOperands(); ++OpNum)
885 const MachineOperand& Op = MInst->getOperand(OpNum);
887 if (MInst->getOperandType(OpNum) == MachineOperand::MO_VirtualRegister ||
888 MInst->getOperandType(OpNum) == MachineOperand::MO_CCRegister)
889 if (const Value* Val = Op.getVRegValue())
890 if (MRI.getRegClassIDOfValue(Val) == RC->getID())
891 if (Op.getAllocatedRegNum() == -1)
892 if (LiveRange *LROfVal = LRI.getLiveRangeForValue(Val))
893 if (LROfVal->hasColor() )
894 // this operand is in a LR that received a color
895 IsColorUsedArr[LROfVal->getColor()] = true;
898 // If there are implicit references, mark their allocated regs as well
900 for (unsigned z=0; z < MInst->getNumImplicitRefs(); z++)
902 LRofImpRef = LRI.getLiveRangeForValue(MInst->getImplicitRef(z)))
903 if (LRofImpRef->hasColor())
904 // this implicit reference is in a LR that received a color
905 IsColorUsedArr[LRofImpRef->getColor()] = true;
909 //----------------------------------------------------------------------------
910 // If there are delay slots for an instruction, the instructions
911 // added after it must really go after the delayed instruction(s).
912 // So, we move the InstrAfter of that instruction to the
913 // corresponding delayed instruction using the following method.
915 //----------------------------------------------------------------------------
916 void PhyRegAlloc::move2DelayedInstr(const MachineInstr *OrigMI,
917 const MachineInstr *DelayedMI) {
919 // "added after" instructions of the original instr
920 std::vector<MachineInstr *> &OrigAft = AddedInstrMap[OrigMI].InstrnsAfter;
922 // "added instructions" of the delayed instr
923 AddedInstrns &DelayAdI = AddedInstrMap[DelayedMI];
925 // "added after" instructions of the delayed instr
926 std::vector<MachineInstr *> &DelayedAft = DelayAdI.InstrnsAfter;
928 // go thru all the "added after instructions" of the original instruction
929 // and append them to the "addded after instructions" of the delayed
931 DelayedAft.insert(DelayedAft.end(), OrigAft.begin(), OrigAft.end());
933 // empty the "added after instructions" of the original instruction
937 //----------------------------------------------------------------------------
938 // This method prints the code with registers after register allocation is
940 //----------------------------------------------------------------------------
941 void PhyRegAlloc::printMachineCode()
944 cerr << "\n;************** Function " << Fn->getName()
945 << " *****************\n";
947 for (MachineFunction::iterator BBI = MF.begin(), BBE = MF.end();
949 cerr << "\n"; printLabel(BBI->getBasicBlock()); cerr << ": ";
951 // get the iterator for machine instructions
952 MachineBasicBlock& MBB = *BBI;
953 MachineBasicBlock::iterator MII = MBB.begin();
955 // iterate over all the machine instructions in BB
956 for ( ; MII != MBB.end(); ++MII) {
957 MachineInstr *MInst = *MII;
960 cerr << TM.getInstrInfo().getName(MInst->getOpCode());
962 for (unsigned OpNum=0; OpNum < MInst->getNumOperands(); ++OpNum) {
963 MachineOperand& Op = MInst->getOperand(OpNum);
965 if (Op.getType() == MachineOperand::MO_VirtualRegister ||
966 Op.getType() == MachineOperand::MO_CCRegister /*||
967 Op.getType() == MachineOperand::MO_PCRelativeDisp*/ ) {
969 const Value *const Val = Op.getVRegValue () ;
970 // ****this code is temporary till NULL Values are fixed
972 cerr << "\t<*NULL*>";
976 // if a label or a constant
977 if (isa<BasicBlock>(Val)) {
978 cerr << "\t"; printLabel( Op.getVRegValue () );
980 // else it must be a register value
981 const int RegNum = Op.getAllocatedRegNum();
983 cerr << "\t" << "%" << MRI.getUnifiedRegName( RegNum );
985 cerr << "(" << Val->getName() << ")";
987 cerr << "(" << Val << ")";
992 const LiveRange *LROfVal = LRI.getLiveRangeForValue(Val);
994 if (LROfVal->hasSpillOffset() )
999 else if (Op.getType() == MachineOperand::MO_MachineRegister) {
1000 cerr << "\t" << "%" << MRI.getUnifiedRegName(Op.getMachineRegNum());
1004 cerr << "\t" << Op; // use dump field
1009 unsigned NumOfImpRefs = MInst->getNumImplicitRefs();
1010 if (NumOfImpRefs > 0) {
1011 cerr << "\tImplicit:";
1013 for (unsigned z=0; z < NumOfImpRefs; z++)
1014 cerr << RAV(MInst->getImplicitRef(z)) << "\t";
1017 } // for all machine instructions
1027 //----------------------------------------------------------------------------
1029 //----------------------------------------------------------------------------
1030 void PhyRegAlloc::colorIncomingArgs()
1032 MRI.colorMethodArgs(Fn, LRI, &AddedInstrAtEntry);
1036 //----------------------------------------------------------------------------
1037 // Used to generate a label for a basic block
1038 //----------------------------------------------------------------------------
1039 void PhyRegAlloc::printLabel(const Value *Val) {
1041 cerr << Val->getName();
1043 cerr << "Label" << Val;
1047 //----------------------------------------------------------------------------
1048 // This method calls setSugColorUsable method of each live range. This
1049 // will determine whether the suggested color of LR is really usable.
1050 // A suggested color is not usable when the suggested color is volatile
1051 // AND when there are call interferences
1052 //----------------------------------------------------------------------------
1054 void PhyRegAlloc::markUnusableSugColors()
1056 // hash map iterator
1057 LiveRangeMapType::const_iterator HMI = (LRI.getLiveRangeMap())->begin();
1058 LiveRangeMapType::const_iterator HMIEnd = (LRI.getLiveRangeMap())->end();
1060 for (; HMI != HMIEnd ; ++HMI ) {
1062 LiveRange *L = HMI->second; // get the LiveRange
1064 if (L->hasSuggestedColor()) {
1065 int RCID = L->getRegClass()->getID();
1066 if (MRI.isRegVolatile( RCID, L->getSuggestedColor()) &&
1067 L->isCallInterference() )
1068 L->setSuggestedColorUsable( false );
1070 L->setSuggestedColorUsable( true );
1072 } // if L->hasSuggestedColor()
1074 } // for all LR's in hash map
1079 //----------------------------------------------------------------------------
1080 // The following method will set the stack offsets of the live ranges that
1081 // are decided to be spillled. This must be called just after coloring the
1082 // LRs using the graph coloring algo. For each live range that is spilled,
1083 // this method allocate a new spill position on the stack.
1084 //----------------------------------------------------------------------------
1086 void PhyRegAlloc::allocateStackSpace4SpilledLRs() {
1087 if (DEBUG_RA) cerr << "\nSetting LR stack offsets for spills...\n";
1089 LiveRangeMapType::const_iterator HMI = LRI.getLiveRangeMap()->begin();
1090 LiveRangeMapType::const_iterator HMIEnd = LRI.getLiveRangeMap()->end();
1092 for ( ; HMI != HMIEnd ; ++HMI) {
1093 if (HMI->first && HMI->second) {
1094 LiveRange *L = HMI->second; // get the LiveRange
1095 if (!L->hasColor()) { // NOTE: ** allocating the size of long Type **
1096 int stackOffset = MF.getInfo()->allocateSpilledValue(Type::LongTy);
1097 L->setSpillOffFromFP(stackOffset);
1099 cerr << " LR# " << L->getUserIGNode()->getIndex()
1100 << ": stack-offset = " << stackOffset << "\n";
1103 } // for all LR's in hash map
1108 //----------------------------------------------------------------------------
1109 // The entry pont to Register Allocation
1110 //----------------------------------------------------------------------------
1112 void PhyRegAlloc::allocateRegisters()
1115 // make sure that we put all register classes into the RegClassList
1116 // before we call constructLiveRanges (now done in the constructor of
1117 // PhyRegAlloc class).
1119 LRI.constructLiveRanges(); // create LR info
1121 if (DEBUG_RA >= RA_DEBUG_LiveRanges)
1122 LRI.printLiveRanges();
1124 createIGNodeListsAndIGs(); // create IGNode list and IGs
1126 buildInterferenceGraphs(); // build IGs in all reg classes
1129 if (DEBUG_RA >= RA_DEBUG_LiveRanges) {
1130 // print all LRs in all reg classes
1131 for ( unsigned rc=0; rc < NumOfRegClasses ; rc++)
1132 RegClassList[rc]->printIGNodeList();
1134 // print IGs in all register classes
1135 for ( unsigned rc=0; rc < NumOfRegClasses ; rc++)
1136 RegClassList[rc]->printIG();
1139 LRI.coalesceLRs(); // coalesce all live ranges
1141 if (DEBUG_RA >= RA_DEBUG_LiveRanges) {
1142 // print all LRs in all reg classes
1143 for (unsigned rc=0; rc < NumOfRegClasses; rc++)
1144 RegClassList[rc]->printIGNodeList();
1146 // print IGs in all register classes
1147 for (unsigned rc=0; rc < NumOfRegClasses; rc++)
1148 RegClassList[rc]->printIG();
1152 // mark un-usable suggested color before graph coloring algorithm.
1153 // When this is done, the graph coloring algo will not reserve
1154 // suggested color unnecessarily - they can be used by another LR
1156 markUnusableSugColors();
1158 // color all register classes using the graph coloring algo
1159 for (unsigned rc=0; rc < NumOfRegClasses ; rc++)
1160 RegClassList[rc]->colorAllRegs();
1162 // Atter graph coloring, if some LRs did not receive a color (i.e, spilled)
1163 // a poistion for such spilled LRs
1165 allocateStackSpace4SpilledLRs();
1167 MF.getInfo()->popAllTempValues(); // TODO **Check
1169 // color incoming args - if the correct color was not received
1170 // insert code to copy to the correct register
1172 colorIncomingArgs();
1174 // Now update the machine code with register names and add any
1175 // additional code inserted by the register allocator to the instruction
1178 updateMachineCode();
1181 cerr << "\n**** Machine Code After Register Allocation:\n\n";