2 //***************************************************************************
7 // Scheduling graph based on SSA graph plus extra dependence edges
8 // capturing dependences due to machine resources (machine registers,
9 // CC registers, and any others).
12 // 7/20/01 - Vikram Adve - Created
13 //**************************************************************************/
15 #include "SchedGraph.h"
16 #include "llvm/InstrTypes.h"
17 #include "llvm/Instruction.h"
18 #include "llvm/BasicBlock.h"
19 #include "llvm/Method.h"
20 #include "llvm/CodeGen/MachineInstr.h"
21 #include "llvm/Target/MachineInstrInfo.h"
22 #include "llvm/Target/MachineRegInfo.h"
23 #include "llvm/Support/StringExtras.h"
27 //*********************** Internal Data Structures *************************/
29 typedef vector< pair<SchedGraphNode*, unsigned int> > RefVec;
31 // The following needs to be a class, not a typedef, so we can use
32 // an opaque declaration in SchedGraph.h
33 class RegToRefVecMap: public hash_map<int, RefVec> {
34 typedef hash_map<int, RefVec>:: iterator iterator;
35 typedef hash_map<int, RefVec>::const_iterator const_iterator;
39 // class SchedGraphEdge
43 SchedGraphEdge::SchedGraphEdge(SchedGraphNode* _src,
44 SchedGraphNode* _sink,
45 SchedGraphEdgeDepType _depType,
46 DataDepOrderType _depOrderType,
51 depOrderType(_depOrderType),
53 minDelay((_minDelay >= 0)? _minDelay : _src->getLatency())
55 src->addOutEdge(this);
56 sink->addInEdge(this);
61 SchedGraphEdge::SchedGraphEdge(SchedGraphNode* _src,
62 SchedGraphNode* _sink,
64 DataDepOrderType _depOrderType,
69 depOrderType(_depOrderType),
71 minDelay((_minDelay >= 0)? _minDelay : _src->getLatency())
73 src->addOutEdge(this);
74 sink->addInEdge(this);
79 SchedGraphEdge::SchedGraphEdge(SchedGraphNode* _src,
80 SchedGraphNode* _sink,
82 DataDepOrderType _depOrderType,
86 depType(MachineRegister),
87 depOrderType(_depOrderType),
88 minDelay((_minDelay >= 0)? _minDelay : _src->getLatency()),
89 machineRegNum(_regNum)
91 src->addOutEdge(this);
92 sink->addInEdge(this);
97 SchedGraphEdge::SchedGraphEdge(SchedGraphNode* _src,
98 SchedGraphNode* _sink,
99 ResourceId _resourceId,
103 depType(MachineResource),
104 depOrderType(NonDataDep),
105 minDelay((_minDelay >= 0)? _minDelay : _src->getLatency()),
106 resourceId(_resourceId)
108 src->addOutEdge(this);
109 sink->addInEdge(this);
113 SchedGraphEdge::~SchedGraphEdge()
117 void SchedGraphEdge::dump(int indent=0) const {
118 printIndent(indent); cout << *this;
123 // class SchedGraphNode
127 SchedGraphNode::SchedGraphNode(unsigned int _nodeId,
128 const Instruction* _instr,
129 const MachineInstr* _minstr,
130 const TargetMachine& target)
138 MachineOpCode mopCode = minstr->getOpCode();
139 latency = target.getInstrInfo().hasResultInterlock(mopCode)
140 ? target.getInstrInfo().minLatency(mopCode)
141 : target.getInstrInfo().maxLatency(mopCode);
147 SchedGraphNode::~SchedGraphNode()
151 void SchedGraphNode::dump(int indent=0) const {
152 printIndent(indent); cout << *this;
157 SchedGraphNode::addInEdge(SchedGraphEdge* edge)
159 inEdges.push_back(edge);
164 SchedGraphNode::addOutEdge(SchedGraphEdge* edge)
166 outEdges.push_back(edge);
170 SchedGraphNode::removeInEdge(const SchedGraphEdge* edge)
172 assert(edge->getSink() == this);
174 for (iterator I = beginInEdges(); I != endInEdges(); ++I)
183 SchedGraphNode::removeOutEdge(const SchedGraphEdge* edge)
185 assert(edge->getSrc() == this);
187 for (iterator I = beginOutEdges(); I != endOutEdges(); ++I)
202 SchedGraph::SchedGraph(const BasicBlock* bb,
203 const TargetMachine& target)
206 this->buildGraph(target);
211 SchedGraph::~SchedGraph()
213 for (iterator I=begin(); I != end(); ++I)
215 SchedGraphNode* node = (*I).second;
217 // for each node, delete its out-edges
218 for (SchedGraphNode::iterator I = node->beginOutEdges();
219 I != node->endOutEdges(); ++I)
222 // then delete the node itself.
229 SchedGraph::dump() const
231 cout << " Sched Graph for Basic Blocks: ";
232 for (unsigned i=0, N=bbVec.size(); i < N; i++)
234 cout << (bbVec[i]->hasName()? bbVec[i]->getName() : "block")
235 << " (" << bbVec[i] << ")"
236 << ((i == N-1)? "" : ", ");
239 cout << endl << endl << " Actual Root nodes : ";
240 for (unsigned i=0, N=graphRoot->outEdges.size(); i < N; i++)
241 cout << graphRoot->outEdges[i]->getSink()->getNodeId()
242 << ((i == N-1)? "" : ", ");
244 cout << endl << " Graph Nodes:" << endl;
245 for (const_iterator I=begin(); I != end(); ++I)
246 cout << endl << * (*I).second;
253 SchedGraph::eraseIncomingEdges(SchedGraphNode* node, bool addDummyEdges)
255 // Delete and disconnect all in-edges for the node
256 for (SchedGraphNode::iterator I = node->beginInEdges();
257 I != node->endInEdges(); ++I)
259 SchedGraphNode* srcNode = (*I)->getSrc();
260 srcNode->removeOutEdge(*I);
264 srcNode != getRoot() &&
265 srcNode->beginOutEdges() == srcNode->endOutEdges())
266 { // srcNode has no more out edges, so add an edge to dummy EXIT node
267 assert(node != getLeaf() && "Adding edge that was just removed?");
268 (void) new SchedGraphEdge(srcNode, getLeaf(),
269 SchedGraphEdge::CtrlDep, SchedGraphEdge::NonDataDep, 0);
273 node->inEdges.clear();
277 SchedGraph::eraseOutgoingEdges(SchedGraphNode* node, bool addDummyEdges)
279 // Delete and disconnect all out-edges for the node
280 for (SchedGraphNode::iterator I = node->beginOutEdges();
281 I != node->endOutEdges(); ++I)
283 SchedGraphNode* sinkNode = (*I)->getSink();
284 sinkNode->removeInEdge(*I);
288 sinkNode != getLeaf() &&
289 sinkNode->beginInEdges() == sinkNode->endInEdges())
290 { //sinkNode has no more in edges, so add an edge from dummy ENTRY node
291 assert(node != getRoot() && "Adding edge that was just removed?");
292 (void) new SchedGraphEdge(getRoot(), sinkNode,
293 SchedGraphEdge::CtrlDep, SchedGraphEdge::NonDataDep, 0);
297 node->outEdges.clear();
301 SchedGraph::eraseIncidentEdges(SchedGraphNode* node, bool addDummyEdges)
303 this->eraseIncomingEdges(node, addDummyEdges);
304 this->eraseOutgoingEdges(node, addDummyEdges);
309 SchedGraph::addDummyEdges()
311 assert(graphRoot->outEdges.size() == 0);
313 for (const_iterator I=begin(); I != end(); ++I)
315 SchedGraphNode* node = (*I).second;
316 assert(node != graphRoot && node != graphLeaf);
317 if (node->beginInEdges() == node->endInEdges())
318 (void) new SchedGraphEdge(graphRoot, node, SchedGraphEdge::CtrlDep,
319 SchedGraphEdge::NonDataDep, 0);
320 if (node->beginOutEdges() == node->endOutEdges())
321 (void) new SchedGraphEdge(node, graphLeaf, SchedGraphEdge::CtrlDep,
322 SchedGraphEdge::NonDataDep, 0);
328 SchedGraph::addCDEdges(const TerminatorInst* term,
329 const TargetMachine& target)
331 const MachineInstrInfo& mii = target.getInstrInfo();
332 MachineCodeForVMInstr& termMvec = term->getMachineInstrVec();
334 // Find the first branch instr in the sequence of machine instrs for term
337 while (! mii.isBranch(termMvec[first]->getOpCode()))
339 assert(first < termMvec.size() &&
340 "No branch instructions for BR? Ok, but weird! Delete assertion.");
341 if (first == termMvec.size())
344 SchedGraphNode* firstBrNode = this->getGraphNodeForInstr(termMvec[first]);
346 // Add CD edges from each instruction in the sequence to the
347 // *last preceding* branch instr. in the sequence
349 for (int i = (int) termMvec.size()-1; i > (int) first; i--)
351 SchedGraphNode* toNode = this->getGraphNodeForInstr(termMvec[i]);
352 assert(toNode && "No node for instr generated for branch?");
354 for (int j = i-1; j >= 0; j--)
355 if (mii.isBranch(termMvec[j]->getOpCode()))
357 SchedGraphNode* brNode = this->getGraphNodeForInstr(termMvec[j]);
358 assert(brNode && "No node for instr generated for branch?");
359 (void) new SchedGraphEdge(brNode, toNode, SchedGraphEdge::CtrlDep,
360 SchedGraphEdge::NonDataDep, 0);
361 break; // only one incoming edge is enough
365 // Add CD edges from each instruction preceding the first branch
366 // to the first branch
368 for (int i = first-1; i >= 0; i--)
370 SchedGraphNode* fromNode = this->getGraphNodeForInstr(termMvec[i]);
371 assert(fromNode && "No node for instr generated for branch?");
372 (void) new SchedGraphEdge(fromNode, firstBrNode, SchedGraphEdge::CtrlDep,
373 SchedGraphEdge::NonDataDep, 0);
376 // Now add CD edges to the first branch instruction in the sequence
377 // from all preceding instructions in the basic block.
379 const BasicBlock* bb = term->getParent();
380 for (BasicBlock::const_iterator II = bb->begin(); II != bb->end(); ++II)
382 if ((*II) == (const Instruction*) term) // special case, handled above
385 assert(! (*II)->isTerminator() && "Two terminators in basic block?");
387 const MachineCodeForVMInstr& mvec = (*II)->getMachineInstrVec();
388 for (unsigned i=0, N=mvec.size(); i < N; i++)
390 SchedGraphNode* fromNode = this->getGraphNodeForInstr(mvec[i]);
391 if (fromNode == NULL)
392 continue; // dummy instruction, e.g., PHI
394 (void) new SchedGraphEdge(fromNode, firstBrNode,
395 SchedGraphEdge::CtrlDep,
396 SchedGraphEdge::NonDataDep, 0);
398 // If we find any other machine instructions (other than due to
399 // the terminator) that also have delay slots, add an outgoing edge
400 // from the instruction to the instructions in the delay slots.
402 unsigned d = mii.getNumDelaySlots(mvec[i]->getOpCode());
403 assert(i+d < N && "Insufficient delay slots for instruction?");
405 for (unsigned j=1; j <= d; j++)
407 SchedGraphNode* toNode = this->getGraphNodeForInstr(mvec[i+j]);
408 assert(toNode && "No node for machine instr in delay slot?");
409 (void) new SchedGraphEdge(fromNode, toNode,
410 SchedGraphEdge::CtrlDep,
411 SchedGraphEdge::NonDataDep, 0);
419 SchedGraph::addMemEdges(const vector<const Instruction*>& memVec,
420 const TargetMachine& target)
422 const MachineInstrInfo& mii = target.getInstrInfo();
424 for (unsigned im=0, NM=memVec.size(); im < NM; im++)
426 const Instruction* fromInstr = memVec[im];
427 bool fromIsLoad = fromInstr->getOpcode() == Instruction::Load;
429 for (unsigned jm=im+1; jm < NM; jm++)
431 const Instruction* toInstr = memVec[jm];
432 bool toIsLoad = toInstr->getOpcode() == Instruction::Load;
433 SchedGraphEdge::DataDepOrderType depOrderType;
437 if (toIsLoad) continue; // both instructions are loads
438 depOrderType = SchedGraphEdge::AntiDep;
442 depOrderType = (toIsLoad)? SchedGraphEdge::TrueDep
443 : SchedGraphEdge::OutputDep;
446 MachineCodeForVMInstr& fromInstrMvec=fromInstr->getMachineInstrVec();
447 MachineCodeForVMInstr& toInstrMvec = toInstr->getMachineInstrVec();
449 // We have two VM memory instructions, and at least one is a store.
450 // Add edges between all machine load/store instructions.
452 for (unsigned i=0, N=fromInstrMvec.size(); i < N; i++)
454 MachineOpCode fromOpCode = fromInstrMvec[i]->getOpCode();
455 if (mii.isLoad(fromOpCode) || mii.isStore(fromOpCode))
457 SchedGraphNode* fromNode =
458 this->getGraphNodeForInstr(fromInstrMvec[i]);
459 assert(fromNode && "No node for memory instr?");
461 for (unsigned j=0, M=toInstrMvec.size(); j < M; j++)
463 MachineOpCode toOpCode = toInstrMvec[j]->getOpCode();
464 if (mii.isLoad(toOpCode) || mii.isStore(toOpCode))
466 SchedGraphNode* toNode =
467 this->getGraphNodeForInstr(toInstrMvec[j]);
468 assert(toNode && "No node for memory instr?");
470 (void) new SchedGraphEdge(fromNode, toNode,
471 SchedGraphEdge::MemoryDep,
483 SchedGraph::addMachineRegEdges(RegToRefVecMap& regToRefVecMap,
484 const TargetMachine& target)
486 assert(bbVec.size() == 1 && "Only handling a single basic block here");
488 // This assumes that such hardwired registers are never allocated
489 // to any LLVM value (since register allocation happens later), i.e.,
490 // any uses or defs of this register have been made explicit!
491 // Also assumes that two registers with different numbers are
494 for (RegToRefVecMap::iterator I = regToRefVecMap.begin();
495 I != regToRefVecMap.end(); ++I)
497 int regNum = (*I).first;
498 RefVec& regRefVec = (*I).second;
500 // regRefVec is ordered by control flow order in the basic block
501 for (unsigned i=0; i < regRefVec.size(); ++i)
503 SchedGraphNode* node = regRefVec[i].first;
504 unsigned int opNum = regRefVec[i].second;
505 bool isDef = node->getMachineInstr()->operandIsDefined(opNum);
507 for (unsigned p=0; p < i; ++p)
509 SchedGraphNode* prevNode = regRefVec[p].first;
510 if (prevNode != node)
512 unsigned int prevOpNum = regRefVec[p].second;
514 prevNode->getMachineInstr()->operandIsDefined(prevOpNum);
517 new SchedGraphEdge(prevNode, node, regNum,
518 (prevIsDef)? SchedGraphEdge::OutputDep
519 : SchedGraphEdge::AntiDep);
521 new SchedGraphEdge(prevNode, node, regNum,
522 SchedGraphEdge::TrueDep);
531 SchedGraph::addSSAEdge(SchedGraphNode* node,
533 const TargetMachine& target)
535 if (!val->isInstruction()) return;
537 const Instruction* thisVMInstr = node->getInstr();
538 const Instruction* defVMInstr = val->castInstructionAsserting();
540 // Phi instructions are the only ones that produce a value but don't get
541 // any non-dummy machine instructions. Return here as an optimization.
543 if (defVMInstr->isPHINode())
546 // Now add the graph edge for the appropriate machine instruction(s).
547 // Note that multiple machine instructions generated for the
548 // def VM instruction may modify the register for the def value.
550 MachineCodeForVMInstr& defMvec = defVMInstr->getMachineInstrVec();
551 const MachineInstrInfo& mii = target.getInstrInfo();
553 for (unsigned i=0, N=defMvec.size(); i < N; i++)
554 for (int o=0, N = mii.getNumOperands(defMvec[i]->getOpCode()); o < N; o++)
556 const MachineOperand& defOp = defMvec[i]->getOperand(o);
559 && (defOp.getOperandType() == MachineOperand::MO_VirtualRegister
560 || defOp.getOperandType() == MachineOperand::MO_CCRegister)
561 && (defOp.getVRegValue() == val))
563 // this instruction does define value `val'.
564 // if there is a node for it in the same graph, add an edge.
565 SchedGraphNode* defNode = this->getGraphNodeForInstr(defMvec[i]);
566 if (defNode != NULL && defNode != node)
567 (void) new SchedGraphEdge(defNode, node, val);
574 SchedGraph::addEdgesForInstruction(const MachineInstr& minstr,
575 RegToRefVecMap& regToRefVecMap,
576 const TargetMachine& target)
578 SchedGraphNode* node = this->getGraphNodeForInstr(&minstr);
582 assert(node->getInstr() && "Should be no dummy nodes here!");
583 const Instruction& instr = * node->getInstr();
585 // Add edges for all operands of the machine instruction.
586 // Also, record all machine register references to add reg. deps. later.
588 for (unsigned i=0, numOps=minstr.getNumOperands(); i < numOps; i++)
590 const MachineOperand& mop = minstr.getOperand(i);
592 // if this writes to a machine register other than the hardwired
593 // "zero" register, record the reference.
594 if (mop.getOperandType() == MachineOperand::MO_MachineRegister
595 && (mop.getMachineRegNum()
596 != (unsigned) target.getRegInfo().getZeroRegNum()))
598 regToRefVecMap[mop.getMachineRegNum()].push_back(make_pair(node, i));
601 // ignore all other def operands
602 if (minstr.operandIsDefined(i))
605 switch(mop.getOperandType())
607 case MachineOperand::MO_VirtualRegister:
608 case MachineOperand::MO_CCRegister:
609 if (mop.getVRegValue())
610 addSSAEdge(node, mop.getVRegValue(), target);
613 case MachineOperand::MO_MachineRegister:
616 case MachineOperand::MO_SignExtendedImmed:
617 case MachineOperand::MO_UnextendedImmed:
618 case MachineOperand::MO_PCRelativeDisp:
619 break; // nothing to do for immediate fields
622 assert(0 && "Unknown machine operand type in SchedGraph builder");
627 // Add edges for values implicitly used by the machine instruction sequence
628 // for the VM instruction but not made explicit operands. Examples include
629 // function arguments to a Call instructions or the return value of a Ret
630 // instruction. We'll conservatively add the dependences to every machine
631 // machine instruction in the instruction sequence for this VM instr
632 // (at least for now, there is never more than one machine instr).
634 const vector<const Value*>& implicitUses =
635 instr.getMachineInstrVec().getImplicitUses();
636 for (unsigned i=0; i < implicitUses.size(); ++i)
637 addSSAEdge(node, implicitUses[i], target);
642 SchedGraph::addNonSSAEdgesForValue(const Instruction* instr,
643 const TargetMachine& target)
645 assert(instr->isInstruction());
646 if (instr->isPHINode())
649 MachineCodeForVMInstr& mvec = instr->getMachineInstrVec();
650 const MachineInstrInfo& mii = target.getInstrInfo();
653 for (unsigned i=0, N=mvec.size(); i < N; i++)
654 for (int o=0, N = mii.getNumOperands(mvec[i]->getOpCode()); o < N; o++)
656 const MachineOperand& op = mvec[i]->getOperand(o);
658 if ((op.getOperandType() == MachineOperand::MO_VirtualRegister ||
659 op.getOperandType() == MachineOperand::MO_CCRegister)
660 && op.getVRegValue() == (Value*) instr)
662 // this operand is a definition or use of value `instr'
663 SchedGraphNode* node = this->getGraphNodeForInstr(mvec[i]);
664 assert(node && "No node for machine instruction in this BB?");
665 refVec.push_back(make_pair(node, o));
669 // refVec is ordered by control flow order of the machine instructions
670 for (unsigned i=0; i < refVec.size(); ++i)
672 SchedGraphNode* node = refVec[i].first;
673 unsigned int opNum = refVec[i].second;
674 bool isDef = node->getMachineInstr()->operandIsDefined(opNum);
677 // add output and/or anti deps to this definition
678 for (unsigned p=0; p < i; ++p)
680 SchedGraphNode* prevNode = refVec[p].first;
681 if (prevNode != node)
683 bool prevIsDef = prevNode->getMachineInstr()->
684 operandIsDefined(refVec[p].second);
685 new SchedGraphEdge(prevNode, node, SchedGraphEdge::DefUseDep,
686 (prevIsDef)? SchedGraphEdge::OutputDep
687 : SchedGraphEdge::AntiDep);
695 SchedGraph::buildNodesforVMInstr(const TargetMachine& target,
696 const Instruction* instr)
698 const MachineInstrInfo& mii = target.getInstrInfo();
699 const MachineCodeForVMInstr& mvec = instr->getMachineInstrVec();
700 for (unsigned i=0; i < mvec.size(); i++)
701 if (! mii.isDummyPhiInstr(mvec[i]->getOpCode()))
703 SchedGraphNode* node = new SchedGraphNode(getNumNodes(),
704 instr, mvec[i], target);
705 this->noteGraphNodeForInstr(mvec[i], node);
711 SchedGraph::buildGraph(const TargetMachine& target)
713 const MachineInstrInfo& mii = target.getInstrInfo();
714 const BasicBlock* bb = bbVec[0];
716 assert(bbVec.size() == 1 && "Only handling a single basic block here");
718 // Use this data structures to note all LLVM memory instructions.
719 // We use this to add memory dependence edges without a second full walk.
721 vector<const Instruction*> memVec;
723 // Use this data structures to note any uses or definitions of
724 // machine registers so we can add edges for those later without
725 // extra passes over the nodes.
726 // The vector holds an ordered list of references to the machine reg,
727 // ordered according to control-flow order. This only works for a
728 // single basic block, hence the assertion. Each reference is identified
729 // by the pair: <node, operand-number>.
731 RegToRefVecMap regToRefVecMap;
733 // Make a dummy root node. We'll add edges to the real roots later.
734 graphRoot = new SchedGraphNode(0, NULL, NULL, target);
735 graphLeaf = new SchedGraphNode(1, NULL, NULL, target);
737 //----------------------------------------------------------------
738 // First add nodes for all the machine instructions in the basic block
739 // because this greatly simplifies identifying which edges to add.
740 // Do this one VM instruction at a time since the SchedGraphNode needs that.
741 // Also, remember the load/store instructions to add memory deps later.
742 //----------------------------------------------------------------
744 for (BasicBlock::const_iterator II = bb->begin(); II != bb->end(); ++II)
746 const Instruction *instr = *II;
748 // Build graph nodes for this VM instruction
749 buildNodesforVMInstr(target, instr);
751 // Remember the load/store instructions to add memory deps later.
752 if (instr->getOpcode() == Instruction::Load ||
753 instr->getOpcode() == Instruction::Store)
754 memVec.push_back(instr);
757 //----------------------------------------------------------------
758 // Now add edges for the following (all are incoming edges except (4)):
759 // (1) operands of the machine instruction, including hidden operands
760 // (2) machine register dependences
761 // (3) memory load/store dependences
762 // (3) other resource dependences for the machine instruction, if any
763 // (4) output dependences when multiple machine instructions define the
764 // same value; all must have been generated from a single VM instrn
765 // (5) control dependences to branch instructions generated for the
766 // terminator instruction of the BB. Because of delay slots and
767 // 2-way conditional branches, multiple CD edges are needed
768 // (see addCDEdges for details).
769 // Also, note any uses or defs of machine registers.
771 //----------------------------------------------------------------
773 // First, add edges to the terminator instruction of the basic block.
774 this->addCDEdges(bb->getTerminator(), target);
776 // Then add memory dep edges: store->load, load->store, and store->store
777 this->addMemEdges(memVec, target);
779 // Then add other edges for all instructions in the block.
780 // Do this in machine code order and find all references to machine regs.
781 MachineCodeForBasicBlock& mvec = bb->getMachineInstrVec();
782 for (unsigned i=0, N=mvec.size(); i < N; i++)
783 addEdgesForInstruction(*mvec[i], regToRefVecMap, target);
785 // Since the code is no longer in SSA form, add output dep. edges
786 // between machine instructions that define the same Value, and anti-dep.
787 // edges from those to other machine instructions for the same VM instr.
788 // We assume that all machine instructions that define a value are
789 // generated from the VM instruction corresponding to that value.
791 for (BasicBlock::const_iterator II = bb->begin(); II != bb->end(); ++II)
793 const Instruction *instr = *II;
794 this->addNonSSAEdgesForValue(instr, target);
797 // Then add edges for dependences on machine registers
798 this->addMachineRegEdges(regToRefVecMap, target);
800 // Finally, add edges from the dummy root and to dummy leaf
801 this->addDummyEdges();
806 // class SchedGraphSet
810 SchedGraphSet::SchedGraphSet(const Method* _method,
811 const TargetMachine& target) :
814 buildGraphsForMethod(method, target);
819 SchedGraphSet::~SchedGraphSet()
821 // delete all the graphs
822 for (iterator I=begin(); I != end(); ++I)
828 SchedGraphSet::dump() const
830 cout << "======== Sched graphs for method `"
831 << (method->hasName()? method->getName() : "???")
832 << "' ========" << endl << endl;
834 for (const_iterator I=begin(); I != end(); ++I)
837 cout << endl << "====== End graphs for method `"
838 << (method->hasName()? method->getName() : "")
839 << "' ========" << endl << endl;
844 SchedGraphSet::buildGraphsForMethod(const Method *method,
845 const TargetMachine& target)
847 for (Method::const_iterator BI = method->begin(); BI != method->end(); ++BI)
849 SchedGraph* graph = new SchedGraph(*BI, target);
850 this->noteGraphForBlock(*BI, graph);
857 operator<<(ostream& os, const SchedGraphEdge& edge)
859 os << "edge [" << edge.src->getNodeId() << "] -> ["
860 << edge.sink->getNodeId() << "] : ";
862 switch(edge.depType) {
863 case SchedGraphEdge::CtrlDep: os<< "Control Dep"; break;
864 case SchedGraphEdge::DefUseDep: os<< "Reg Value " << edge.val; break;
865 case SchedGraphEdge::MemoryDep: os<< "Mem Value " << edge.val; break;
866 case SchedGraphEdge::MachineRegister: os<< "Reg " <<edge.machineRegNum;break;
867 case SchedGraphEdge::MachineResource: os<<"Resource "<<edge.resourceId;break;
868 default: assert(0); break;
871 os << " : delay = " << edge.minDelay << endl;
877 operator<<(ostream& os, const SchedGraphNode& node)
880 os << "Node " << node.nodeId << " : "
881 << "latency = " << node.latency << endl;
885 if (node.getMachineInstr() == NULL)
886 os << "(Dummy node)" << endl;
889 os << *node.getMachineInstr() << endl;
892 os << node.inEdges.size() << " Incoming Edges:" << endl;
893 for (unsigned i=0, N=node.inEdges.size(); i < N; i++)
896 os << * node.inEdges[i];
900 os << node.outEdges.size() << " Outgoing Edges:" << endl;
901 for (unsigned i=0, N=node.outEdges.size(); i < N; i++)
904 os << * node.outEdges[i];