1 //===- InstrScheduling.cpp - Generic Instruction Scheduling support -------===//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by the LLVM research group and is distributed under
6 // the University of Illinois Open Source License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file implements the llvm/CodeGen/InstrScheduling.h interface, along with
11 // generic support routines for instruction scheduling.
13 //===----------------------------------------------------------------------===//
15 #include "SchedPriorities.h"
16 #include "llvm/BasicBlock.h"
17 #include "llvm/CodeGen/MachineInstr.h"
18 #include "llvm/CodeGen/MachineFunction.h"
19 #include "llvm/Target/TargetMachine.h"
20 #include "../../Target/SparcV9/MachineCodeForInstruction.h"
21 #include "../../Target/SparcV9/LiveVar/FunctionLiveVarInfo.h"
22 #include "Support/CommandLine.h"
28 SchedDebugLevel_t SchedDebugLevel;
30 static cl::opt<bool> EnableFillingDelaySlots("sched-fill-delay-slots",
31 cl::desc("Fill branch delay slots during local scheduling"));
33 static cl::opt<SchedDebugLevel_t, true>
34 SDL_opt("dsched", cl::Hidden, cl::location(SchedDebugLevel),
35 cl::desc("enable instruction scheduling debugging information"),
37 clEnumValN(Sched_NoDebugInfo, "n", "disable debug output"),
38 clEnumValN(Sched_PrintMachineCode, "y", "print machine code after scheduling"),
39 clEnumValN(Sched_PrintSchedTrace, "t", "print trace of scheduling actions"),
40 clEnumValN(Sched_PrintSchedGraphs, "g", "print scheduling graphs"),
44 //************************* Internal Data Types *****************************/
47 class SchedulingManager;
50 //----------------------------------------------------------------------
53 // Represents a group of instructions scheduled to be issued
55 //----------------------------------------------------------------------
58 InstrGroup(const InstrGroup&); // DO NOT IMPLEMENT
59 void operator=(const InstrGroup&); // DO NOT IMPLEMENT
62 inline const SchedGraphNode* operator[](unsigned int slotNum) const {
63 assert(slotNum < group.size());
64 return group[slotNum];
68 friend class InstrSchedule;
70 inline void addInstr(const SchedGraphNode* node, unsigned int slotNum) {
71 assert(slotNum < group.size());
72 group[slotNum] = node;
75 /*ctor*/ InstrGroup(unsigned int nslots)
76 : group(nslots, NULL) {}
78 /*ctor*/ InstrGroup(); // disable: DO NOT IMPLEMENT
81 std::vector<const SchedGraphNode*> group;
85 //----------------------------------------------------------------------
86 // class ScheduleIterator:
88 // Iterates over the machine instructions in the for a single basic block.
89 // The schedule is represented by an InstrSchedule object.
90 //----------------------------------------------------------------------
92 template<class _NodeType>
93 class ScheduleIterator : public forward_iterator<_NodeType, ptrdiff_t> {
97 const InstrSchedule& S;
99 typedef ScheduleIterator<_NodeType> _Self;
101 /*ctor*/ inline ScheduleIterator(const InstrSchedule& _schedule,
104 : cycleNum(_cycleNum), slotNum(_slotNum), S(_schedule) {
108 /*ctor*/ inline ScheduleIterator(const _Self& x)
109 : cycleNum(x.cycleNum), slotNum(x.slotNum), S(x.S) {}
111 inline bool operator==(const _Self& x) const {
112 return (slotNum == x.slotNum && cycleNum== x.cycleNum && &S==&x.S);
115 inline bool operator!=(const _Self& x) const { return !operator==(x); }
117 inline _NodeType* operator*() const;
118 inline _NodeType* operator->() const { return operator*(); }
120 _Self& operator++(); // Preincrement
121 inline _Self operator++(int) { // Postincrement
122 _Self tmp(*this); ++*this; return tmp;
125 static _Self begin(const InstrSchedule& _schedule);
126 static _Self end( const InstrSchedule& _schedule);
129 inline _Self& operator=(const _Self& x); // DISABLE -- DO NOT IMPLEMENT
130 void skipToNextInstr();
134 //----------------------------------------------------------------------
135 // class InstrSchedule:
137 // Represents the schedule of machine instructions for a single basic block.
138 //----------------------------------------------------------------------
140 class InstrSchedule {
141 const unsigned int nslots;
142 unsigned int numInstr;
143 std::vector<InstrGroup*> groups; // indexed by cycle number
144 std::vector<cycles_t> startTime; // indexed by node id
146 InstrSchedule(InstrSchedule&); // DO NOT IMPLEMENT
147 void operator=(InstrSchedule&); // DO NOT IMPLEMENT
150 typedef ScheduleIterator<SchedGraphNode> iterator;
151 typedef ScheduleIterator<const SchedGraphNode> const_iterator;
153 iterator begin() { return iterator::begin(*this); }
154 const_iterator begin() const { return const_iterator::begin(*this); }
155 iterator end() { return iterator::end(*this); }
156 const_iterator end() const { return const_iterator::end(*this); }
158 public: // constructors and destructor
159 /*ctor*/ InstrSchedule (unsigned int _nslots,
160 unsigned int _numNodes);
161 /*dtor*/ ~InstrSchedule ();
163 public: // accessor functions to query chosen schedule
164 const SchedGraphNode* getInstr (unsigned int slotNum,
166 const InstrGroup* igroup = this->getIGroup(c);
167 return (igroup == NULL)? NULL : (*igroup)[slotNum];
170 inline InstrGroup* getIGroup (cycles_t c) {
171 if ((unsigned)c >= groups.size())
173 if (groups[c] == NULL)
174 groups[c] = new InstrGroup(nslots);
178 inline const InstrGroup* getIGroup (cycles_t c) const {
179 assert((unsigned)c < groups.size());
183 inline cycles_t getStartTime (unsigned int nodeId) const {
184 assert(nodeId < startTime.size());
185 return startTime[nodeId];
188 unsigned int getNumInstructions() const {
192 inline void scheduleInstr (const SchedGraphNode* node,
193 unsigned int slotNum,
195 InstrGroup* igroup = this->getIGroup(cycle);
196 if (!((*igroup)[slotNum] == NULL)) {
197 std::cerr << "Slot already filled?\n";
200 igroup->addInstr(node, slotNum);
201 assert(node->getNodeId() < startTime.size());
202 startTime[node->getNodeId()] = cycle;
207 friend class ScheduleIterator<SchedGraphNode>;
208 friend class ScheduleIterator<const SchedGraphNode>;
209 /*ctor*/ InstrSchedule (); // Disable: DO NOT IMPLEMENT.
212 template<class NodeType>
213 inline NodeType *ScheduleIterator<NodeType>::operator*() const {
214 assert(cycleNum < S.groups.size());
215 return (*S.groups[cycleNum])[slotNum];
220 InstrSchedule::InstrSchedule(unsigned int _nslots, unsigned int _numNodes)
223 groups(2 * _numNodes / _nslots), // 2 x lower-bound for #cycles
224 startTime(_numNodes, (cycles_t) -1) // set all to -1
230 InstrSchedule::~InstrSchedule()
232 for (unsigned c=0, NC=groups.size(); c < NC; c++)
233 if (groups[c] != NULL)
234 delete groups[c]; // delete InstrGroup objects
238 template<class _NodeType>
241 ScheduleIterator<_NodeType>::skipToNextInstr()
243 while(cycleNum < S.groups.size() && S.groups[cycleNum] == NULL)
244 ++cycleNum; // skip cycles with no instructions
246 while (cycleNum < S.groups.size() &&
247 (*S.groups[cycleNum])[slotNum] == NULL)
250 if (slotNum == S.nslots) {
253 while(cycleNum < S.groups.size() && S.groups[cycleNum] == NULL)
254 ++cycleNum; // skip cycles with no instructions
259 template<class _NodeType>
261 ScheduleIterator<_NodeType>&
262 ScheduleIterator<_NodeType>::operator++() // Preincrement
265 if (slotNum == S.nslots) {
273 template<class _NodeType>
274 ScheduleIterator<_NodeType>
275 ScheduleIterator<_NodeType>::begin(const InstrSchedule& _schedule)
277 return _Self(_schedule, 0, 0);
280 template<class _NodeType>
281 ScheduleIterator<_NodeType>
282 ScheduleIterator<_NodeType>::end(const InstrSchedule& _schedule)
284 return _Self(_schedule, _schedule.groups.size(), 0);
288 //----------------------------------------------------------------------
289 // class DelaySlotInfo:
291 // Record information about delay slots for a single branch instruction.
292 // Delay slots are simply indexed by slot number 1 ... numDelaySlots
293 //----------------------------------------------------------------------
295 class DelaySlotInfo {
296 const SchedGraphNode* brNode;
298 std::vector<const SchedGraphNode*> delayNodeVec;
299 cycles_t delayedNodeCycle;
300 unsigned delayedNodeSlotNum;
302 DelaySlotInfo(const DelaySlotInfo &); // DO NOT IMPLEMENT
303 void operator=(const DelaySlotInfo&); // DO NOT IMPLEMENT
305 /*ctor*/ DelaySlotInfo (const SchedGraphNode* _brNode,
307 : brNode(_brNode), ndelays(_ndelays),
308 delayedNodeCycle(0), delayedNodeSlotNum(0) {}
310 inline unsigned getNumDelays () {
314 inline const std::vector<const SchedGraphNode*>& getDelayNodeVec() {
318 inline void addDelayNode (const SchedGraphNode* node) {
319 delayNodeVec.push_back(node);
320 assert(delayNodeVec.size() <= ndelays && "Too many delay slot instrs!");
323 inline void recordChosenSlot (cycles_t cycle, unsigned slotNum) {
324 delayedNodeCycle = cycle;
325 delayedNodeSlotNum = slotNum;
328 unsigned scheduleDelayedNode (SchedulingManager& S);
332 //----------------------------------------------------------------------
333 // class SchedulingManager:
335 // Represents the schedule of machine instructions for a single basic block.
336 //----------------------------------------------------------------------
338 class SchedulingManager {
339 SchedulingManager(SchedulingManager &); // DO NOT IMPLEMENT
340 void operator=(const SchedulingManager &); // DO NOT IMPLEMENT
341 public: // publicly accessible data members
342 const unsigned nslots;
343 const TargetSchedInfo& schedInfo;
344 SchedPriorities& schedPrio;
345 InstrSchedule isched;
348 unsigned totalInstrCount;
350 cycles_t nextEarliestIssueTime; // next cycle we can issue
352 std::vector<hash_set<const SchedGraphNode*> > choicesForSlot;
353 std::vector<const SchedGraphNode*> choiceVec; // indexed by node ptr
354 std::vector<int> numInClass; // indexed by sched class
355 std::vector<cycles_t> nextEarliestStartTime; // indexed by opCode
356 hash_map<const SchedGraphNode*, DelaySlotInfo*> delaySlotInfoForBranches;
357 // indexed by branch node ptr
360 SchedulingManager(const TargetMachine& _target, const SchedGraph* graph,
361 SchedPriorities& schedPrio);
362 ~SchedulingManager() {
363 for (hash_map<const SchedGraphNode*,
364 DelaySlotInfo*>::iterator I = delaySlotInfoForBranches.begin(),
365 E = delaySlotInfoForBranches.end(); I != E; ++I)
369 //----------------------------------------------------------------------
370 // Simplify access to the machine instruction info
371 //----------------------------------------------------------------------
373 inline const TargetInstrInfo& getInstrInfo () const {
374 return schedInfo.getInstrInfo();
377 //----------------------------------------------------------------------
378 // Interface for checking and updating the current time
379 //----------------------------------------------------------------------
381 inline cycles_t getTime () const {
385 inline cycles_t getEarliestIssueTime() const {
386 return nextEarliestIssueTime;
389 inline cycles_t getEarliestStartTimeForOp(MachineOpCode opCode) const {
390 assert(opCode < (int) nextEarliestStartTime.size());
391 return nextEarliestStartTime[opCode];
394 // Update current time to specified cycle
395 inline void updateTime (cycles_t c) {
397 schedPrio.updateTime(c);
400 //----------------------------------------------------------------------
401 // Functions to manage the choices for the current cycle including:
402 // -- a vector of choices by priority (choiceVec)
403 // -- vectors of the choices for each instruction slot (choicesForSlot[])
404 // -- number of choices in each sched class, used to check issue conflicts
405 // between choices for a single cycle
406 //----------------------------------------------------------------------
408 inline unsigned int getNumChoices () const {
409 return choiceVec.size();
412 inline unsigned getNumChoicesInClass (const InstrSchedClass& sc) const {
413 assert(sc < numInClass.size() && "Invalid op code or sched class!");
414 return numInClass[sc];
417 inline const SchedGraphNode* getChoice(unsigned int i) const {
418 // assert(i < choiceVec.size()); don't check here.
422 inline hash_set<const SchedGraphNode*>& getChoicesForSlot(unsigned slotNum) {
423 assert(slotNum < nslots);
424 return choicesForSlot[slotNum];
427 inline void addChoice (const SchedGraphNode* node) {
428 // Append the instruction to the vector of choices for current cycle.
429 // Increment numInClass[c] for the sched class to which the instr belongs.
430 choiceVec.push_back(node);
431 const InstrSchedClass& sc = schedInfo.getSchedClass(node->getOpcode());
432 assert(sc < numInClass.size());
436 inline void addChoiceToSlot (unsigned int slotNum,
437 const SchedGraphNode* node) {
438 // Add the instruction to the choice set for the specified slot
439 assert(slotNum < nslots);
440 choicesForSlot[slotNum].insert(node);
443 inline void resetChoices () {
445 for (unsigned int s=0; s < nslots; s++)
446 choicesForSlot[s].clear();
447 for (unsigned int c=0; c < numInClass.size(); c++)
451 //----------------------------------------------------------------------
452 // Code to query and manage the partial instruction schedule so far
453 //----------------------------------------------------------------------
455 inline unsigned int getNumScheduled () const {
456 return isched.getNumInstructions();
459 inline unsigned int getNumUnscheduled() const {
460 return totalInstrCount - isched.getNumInstructions();
463 inline bool isScheduled (const SchedGraphNode* node) const {
464 return (isched.getStartTime(node->getNodeId()) >= 0);
467 inline void scheduleInstr (const SchedGraphNode* node,
468 unsigned int slotNum,
471 assert(! isScheduled(node) && "Instruction already scheduled?");
473 // add the instruction to the schedule
474 isched.scheduleInstr(node, slotNum, cycle);
476 // update the earliest start times of all nodes that conflict with `node'
477 // and the next-earliest time anything can issue if `node' causes bubbles
478 updateEarliestStartTimes(node, cycle);
480 // remove the instruction from the choice sets for all slots
481 for (unsigned s=0; s < nslots; s++)
482 choicesForSlot[s].erase(node);
484 // and decrement the instr count for the sched class to which it belongs
485 const InstrSchedClass& sc = schedInfo.getSchedClass(node->getOpcode());
486 assert(sc < numInClass.size());
490 //----------------------------------------------------------------------
491 // Create and retrieve delay slot info for delayed instructions
492 //----------------------------------------------------------------------
494 inline DelaySlotInfo* getDelaySlotInfoForInstr(const SchedGraphNode* bn,
495 bool createIfMissing=false)
497 hash_map<const SchedGraphNode*, DelaySlotInfo*>::const_iterator
498 I = delaySlotInfoForBranches.find(bn);
499 if (I != delaySlotInfoForBranches.end())
502 if (!createIfMissing) return 0;
504 DelaySlotInfo *dinfo =
505 new DelaySlotInfo(bn, getInstrInfo().getNumDelaySlots(bn->getOpcode()));
506 return delaySlotInfoForBranches[bn] = dinfo;
510 SchedulingManager(); // DISABLED: DO NOT IMPLEMENT
511 void updateEarliestStartTimes(const SchedGraphNode* node, cycles_t schedTime);
516 SchedulingManager::SchedulingManager(const TargetMachine& target,
517 const SchedGraph* graph,
518 SchedPriorities& _schedPrio)
519 : nslots(target.getSchedInfo()->getMaxNumIssueTotal()),
520 schedInfo(*target.getSchedInfo()),
521 schedPrio(_schedPrio),
522 isched(nslots, graph->getNumNodes()),
523 totalInstrCount(graph->getNumNodes() - 2),
524 nextEarliestIssueTime(0),
525 choicesForSlot(nslots),
526 numInClass(target.getSchedInfo()->getNumSchedClasses(), 0), // set all to 0
527 nextEarliestStartTime(target.getInstrInfo()->getNumOpcodes(),
528 (cycles_t) 0) // set all to 0
532 // Note that an upper bound on #choices for each slot is = nslots since
533 // we use this vector to hold a feasible set of instructions, and more
534 // would be infeasible. Reserve that much memory since it is probably small.
535 for (unsigned int i=0; i < nslots; i++)
536 choicesForSlot[i].resize(nslots);
541 SchedulingManager::updateEarliestStartTimes(const SchedGraphNode* node,
544 if (schedInfo.numBubblesAfter(node->getOpcode()) > 0)
545 { // Update next earliest time before which *nothing* can issue.
546 nextEarliestIssueTime = std::max(nextEarliestIssueTime,
547 curTime + 1 + schedInfo.numBubblesAfter(node->getOpcode()));
550 const std::vector<MachineOpCode>&
551 conflictVec = schedInfo.getConflictList(node->getOpcode());
553 for (unsigned i=0; i < conflictVec.size(); i++)
555 MachineOpCode toOp = conflictVec[i];
556 cycles_t est=schedTime + schedInfo.getMinIssueGap(node->getOpcode(),toOp);
557 assert(toOp < (int) nextEarliestStartTime.size());
558 if (nextEarliestStartTime[toOp] < est)
559 nextEarliestStartTime[toOp] = est;
563 //************************* Internal Functions *****************************/
567 AssignInstructionsToSlots(class SchedulingManager& S, unsigned maxIssue)
569 // find the slot to start from, in the current cycle
570 unsigned int startSlot = 0;
571 cycles_t curTime = S.getTime();
573 assert(maxIssue > 0 && maxIssue <= S.nslots - startSlot);
575 // If only one instruction can be issued, do so.
577 for (unsigned s=startSlot; s < S.nslots; s++)
578 if (S.getChoicesForSlot(s).size() > 0) {
579 // found the one instruction
580 S.scheduleInstr(*S.getChoicesForSlot(s).begin(), s, curTime);
584 // Otherwise, choose from the choices for each slot
586 InstrGroup* igroup = S.isched.getIGroup(S.getTime());
587 assert(igroup != NULL && "Group creation failed?");
589 // Find a slot that has only a single choice, and take it.
590 // If all slots have 0 or multiple choices, pick the first slot with
591 // choices and use its last instruction (just to avoid shifting the vector).
593 for (numIssued = 0; numIssued < maxIssue; numIssued++) {
595 for (unsigned s=startSlot; s < S.nslots; s++)
596 if ((*igroup)[s] == NULL && S.getChoicesForSlot(s).size() == 1) {
597 chosenSlot = (int) s;
601 if (chosenSlot == -1)
602 for (unsigned s=startSlot; s < S.nslots; s++)
603 if ((*igroup)[s] == NULL && S.getChoicesForSlot(s).size() > 0) {
604 chosenSlot = (int) s;
608 if (chosenSlot != -1) {
609 // Insert the chosen instr in the chosen slot and
610 // erase it from all slots.
611 const SchedGraphNode* node= *S.getChoicesForSlot(chosenSlot).begin();
612 S.scheduleInstr(node, chosenSlot, curTime);
616 assert(numIssued > 0 && "Should not happen when maxIssue > 0!");
621 // For now, just assume we are scheduling within a single basic block.
622 // Get the machine instruction vector for the basic block and clear it,
623 // then append instructions in scheduled order.
624 // Also, re-insert the dummy PHI instructions that were at the beginning
625 // of the basic block, since they are not part of the schedule.
628 RecordSchedule(MachineBasicBlock &MBB, const SchedulingManager& S)
630 const TargetInstrInfo& mii = S.schedInfo.getInstrInfo();
632 // Lets make sure we didn't lose any instructions, except possibly
633 // some NOPs from delay slots. Also, PHIs are not included in the schedule.
634 unsigned numInstr = 0;
635 for (MachineBasicBlock::iterator I=MBB.begin(); I != MBB.end(); ++I)
636 if (! mii.isNop(I->getOpcode()) &&
637 ! mii.isDummyPhiInstr(I->getOpcode()))
639 assert(S.isched.getNumInstructions() >= numInstr &&
640 "Lost some non-NOP instructions during scheduling!");
642 if (S.isched.getNumInstructions() == 0)
643 return; // empty basic block!
645 // First find the dummy instructions at the start of the basic block
646 MachineBasicBlock::iterator I = MBB.begin();
647 for ( ; I != MBB.end(); ++I)
648 if (! mii.isDummyPhiInstr(I->getOpcode()))
651 // Remove all except the dummy PHI instructions from MBB, and
652 // pre-allocate create space for the ones we will put back in.
653 while (I != MBB.end())
656 InstrSchedule::const_iterator NIend = S.isched.end();
657 for (InstrSchedule::const_iterator NI = S.isched.begin(); NI != NIend; ++NI)
658 MBB.push_back(const_cast<MachineInstr*>((*NI)->getMachineInstr()));
664 MarkSuccessorsReady(SchedulingManager& S, const SchedGraphNode* node)
666 // Check if any successors are now ready that were not already marked
667 // ready before, and that have not yet been scheduled.
669 for (sg_succ_const_iterator SI = succ_begin(node); SI !=succ_end(node); ++SI)
670 if (! (*SI)->isDummyNode()
671 && ! S.isScheduled(*SI)
672 && ! S.schedPrio.nodeIsReady(*SI))
674 // successor not scheduled and not marked ready; check *its* preds.
676 bool succIsReady = true;
677 for (sg_pred_const_iterator P=pred_begin(*SI); P != pred_end(*SI); ++P)
678 if (! (*P)->isDummyNode() && ! S.isScheduled(*P)) {
683 if (succIsReady) // add the successor to the ready list
684 S.schedPrio.insertReady(*SI);
689 // Choose up to `nslots' FEASIBLE instructions and assign each
690 // instruction to all possible slots that do not violate feasibility.
691 // FEASIBLE means it should be guaranteed that the set
692 // of chosen instructions can be issued in a single group.
695 // maxIssue : total number of feasible instructions
696 // S.choicesForSlot[i=0..nslots] : set of instructions feasible in slot i
699 FindSlotChoices(SchedulingManager& S,
700 DelaySlotInfo*& getDelaySlotInfo)
702 // initialize result vectors to empty
705 // find the slot to start from, in the current cycle
706 unsigned int startSlot = 0;
707 InstrGroup* igroup = S.isched.getIGroup(S.getTime());
708 for (int s = S.nslots - 1; s >= 0; s--)
709 if ((*igroup)[s] != NULL) {
714 // Make sure we pick at most one instruction that would break the group.
715 // Also, if we do pick one, remember which it was.
716 unsigned int indexForBreakingNode = S.nslots;
717 unsigned int indexForDelayedInstr = S.nslots;
718 DelaySlotInfo* delaySlotInfo = NULL;
720 getDelaySlotInfo = NULL;
722 // Choose instructions in order of priority.
723 // Add choices to the choice vector in the SchedulingManager class as
724 // we choose them so that subsequent choices will be correctly tested
725 // for feasibility, w.r.t. higher priority choices for the same cycle.
727 while (S.getNumChoices() < S.nslots - startSlot) {
728 const SchedGraphNode* nextNode=S.schedPrio.getNextHighest(S,S.getTime());
729 if (nextNode == NULL)
730 break; // no more instructions for this cycle
732 if (S.getInstrInfo().getNumDelaySlots(nextNode->getOpcode()) > 0) {
733 delaySlotInfo = S.getDelaySlotInfoForInstr(nextNode);
734 if (delaySlotInfo != NULL) {
735 if (indexForBreakingNode < S.nslots)
736 // cannot issue a delayed instr in the same cycle as one
737 // that breaks the issue group or as another delayed instr
740 indexForDelayedInstr = S.getNumChoices();
742 } else if (S.schedInfo.breaksIssueGroup(nextNode->getOpcode())) {
743 if (indexForBreakingNode < S.nslots)
744 // have a breaking instruction already so throw this one away
747 indexForBreakingNode = S.getNumChoices();
750 if (nextNode != NULL) {
751 S.addChoice(nextNode);
753 if (S.schedInfo.isSingleIssue(nextNode->getOpcode())) {
754 assert(S.getNumChoices() == 1 &&
755 "Prioritizer returned invalid instr for this cycle!");
760 if (indexForDelayedInstr < S.nslots)
761 break; // leave the rest for delay slots
764 assert(S.getNumChoices() <= S.nslots);
765 assert(! (indexForDelayedInstr < S.nslots &&
766 indexForBreakingNode < S.nslots) && "Cannot have both in a cycle");
768 // Assign each chosen instruction to all possible slots for that instr.
769 // But if only one instruction was chosen, put it only in the first
770 // feasible slot; no more analysis will be needed.
772 if (indexForDelayedInstr >= S.nslots &&
773 indexForBreakingNode >= S.nslots)
774 { // No instructions that break the issue group or that have delay slots.
775 // This is the common case, so handle it separately for efficiency.
777 if (S.getNumChoices() == 1) {
778 MachineOpCode opCode = S.getChoice(0)->getOpcode();
780 for (s=startSlot; s < S.nslots; s++)
781 if (S.schedInfo.instrCanUseSlot(opCode, s))
783 assert(s < S.nslots && "No feasible slot for this opCode?");
784 S.addChoiceToSlot(s, S.getChoice(0));
786 for (unsigned i=0; i < S.getNumChoices(); i++) {
787 MachineOpCode opCode = S.getChoice(i)->getOpcode();
788 for (unsigned int s=startSlot; s < S.nslots; s++)
789 if (S.schedInfo.instrCanUseSlot(opCode, s))
790 S.addChoiceToSlot(s, S.getChoice(i));
793 } else if (indexForDelayedInstr < S.nslots) {
794 // There is an instruction that needs delay slots.
795 // Try to assign that instruction to a higher slot than any other
796 // instructions in the group, so that its delay slots can go
800 assert(indexForDelayedInstr == S.getNumChoices() - 1 &&
801 "Instruction with delay slots should be last choice!");
802 assert(delaySlotInfo != NULL && "No delay slot info for instr?");
804 const SchedGraphNode* delayedNode = S.getChoice(indexForDelayedInstr);
805 MachineOpCode delayOpCode = delayedNode->getOpcode();
806 unsigned ndelays= S.getInstrInfo().getNumDelaySlots(delayOpCode);
808 unsigned delayedNodeSlot = S.nslots;
811 // Find the last possible slot for the delayed instruction that leaves
812 // at least `d' slots vacant after it (d = #delay slots)
813 for (int s = S.nslots-ndelays-1; s >= (int) startSlot; s--)
814 if (S.schedInfo.instrCanUseSlot(delayOpCode, s)) {
819 highestSlotUsed = -1;
820 for (unsigned i=0; i < S.getNumChoices() - 1; i++) {
821 // Try to assign every other instruction to a lower numbered
822 // slot than delayedNodeSlot.
823 MachineOpCode opCode =S.getChoice(i)->getOpcode();
824 bool noSlotFound = true;
826 for (s=startSlot; s < delayedNodeSlot; s++)
827 if (S.schedInfo.instrCanUseSlot(opCode, s)) {
828 S.addChoiceToSlot(s, S.getChoice(i));
832 // No slot before `delayedNodeSlot' was found for this opCode
833 // Use a later slot, and allow some delay slots to fall in
836 for ( ; s < S.nslots; s++)
837 if (S.schedInfo.instrCanUseSlot(opCode, s)) {
838 S.addChoiceToSlot(s, S.getChoice(i));
842 assert(s < S.nslots && "No feasible slot for instruction?");
844 highestSlotUsed = std::max(highestSlotUsed, (int) s);
847 assert(highestSlotUsed <= (int) S.nslots-1 && "Invalid slot used?");
849 // We will put the delayed node in the first slot after the
850 // highest slot used. But we just mark that for now, and
851 // schedule it separately because we want to schedule the delay
852 // slots for the node at the same time.
853 cycles_t dcycle = S.getTime();
854 unsigned int dslot = highestSlotUsed + 1;
855 if (dslot == S.nslots) {
859 delaySlotInfo->recordChosenSlot(dcycle, dslot);
860 getDelaySlotInfo = delaySlotInfo;
862 // There is an instruction that breaks the issue group.
863 // For such an instruction, assign to the last possible slot in
864 // the current group, and then don't assign any other instructions
866 assert(indexForBreakingNode < S.nslots);
867 const SchedGraphNode* breakingNode=S.getChoice(indexForBreakingNode);
868 unsigned breakingSlot = INT_MAX;
869 unsigned int nslotsToUse = S.nslots;
871 // Find the last possible slot for this instruction.
872 for (int s = S.nslots-1; s >= (int) startSlot; s--)
873 if (S.schedInfo.instrCanUseSlot(breakingNode->getOpcode(), s)) {
877 assert(breakingSlot < S.nslots &&
878 "No feasible slot for `breakingNode'?");
880 // Higher priority instructions than the one that breaks the group:
881 // These can be assigned to all slots, but will be assigned only
882 // to earlier slots if possible.
884 i < S.getNumChoices() && i < indexForBreakingNode; i++)
886 MachineOpCode opCode =S.getChoice(i)->getOpcode();
888 // If a higher priority instruction cannot be assigned to
889 // any earlier slots, don't schedule the breaking instruction.
891 bool foundLowerSlot = false;
892 nslotsToUse = S.nslots; // May be modified in the loop
893 for (unsigned int s=startSlot; s < nslotsToUse; s++)
894 if (S.schedInfo.instrCanUseSlot(opCode, s)) {
895 if (breakingSlot < S.nslots && s < breakingSlot) {
896 foundLowerSlot = true;
897 nslotsToUse = breakingSlot; // RESETS LOOP UPPER BOUND!
900 S.addChoiceToSlot(s, S.getChoice(i));
904 breakingSlot = INT_MAX; // disable breaking instr
907 // Assign the breaking instruction (if any) to a single slot
908 // Otherwise, just ignore the instruction. It will simply be
909 // scheduled in a later cycle.
910 if (breakingSlot < S.nslots) {
911 S.addChoiceToSlot(breakingSlot, breakingNode);
912 nslotsToUse = breakingSlot;
914 nslotsToUse = S.nslots;
916 // For lower priority instructions than the one that breaks the
917 // group, only assign them to slots lower than the breaking slot.
918 // Otherwise, just ignore the instruction.
919 for (unsigned i=indexForBreakingNode+1; i < S.getNumChoices(); i++) {
920 MachineOpCode opCode = S.getChoice(i)->getOpcode();
921 for (unsigned int s=startSlot; s < nslotsToUse; s++)
922 if (S.schedInfo.instrCanUseSlot(opCode, s))
923 S.addChoiceToSlot(s, S.getChoice(i));
925 } // endif (no delay slots and no breaking slots)
927 return S.getNumChoices();
932 ChooseOneGroup(SchedulingManager& S)
934 assert(S.schedPrio.getNumReady() > 0
935 && "Don't get here without ready instructions.");
937 cycles_t firstCycle = S.getTime();
938 DelaySlotInfo* getDelaySlotInfo = NULL;
940 // Choose up to `nslots' feasible instructions and their possible slots.
941 unsigned numIssued = FindSlotChoices(S, getDelaySlotInfo);
943 while (numIssued == 0) {
944 S.updateTime(S.getTime()+1);
945 numIssued = FindSlotChoices(S, getDelaySlotInfo);
948 AssignInstructionsToSlots(S, numIssued);
950 if (getDelaySlotInfo != NULL)
951 numIssued += getDelaySlotInfo->scheduleDelayedNode(S);
953 // Print trace of scheduled instructions before newly ready ones
954 if (SchedDebugLevel >= Sched_PrintSchedTrace) {
955 for (cycles_t c = firstCycle; c <= S.getTime(); c++) {
956 std::cerr << " Cycle " << (long)c <<" : Scheduled instructions:\n";
957 const InstrGroup* igroup = S.isched.getIGroup(c);
958 for (unsigned int s=0; s < S.nslots; s++) {
960 if ((*igroup)[s] != NULL)
961 std::cerr << * ((*igroup)[s])->getMachineInstr() << "\n";
963 std::cerr << "<none>\n";
973 ForwardListSchedule(SchedulingManager& S)
976 const SchedGraphNode* node;
978 S.schedPrio.initialize();
980 while ((N = S.schedPrio.getNumReady()) > 0) {
981 cycles_t nextCycle = S.getTime();
983 // Choose one group of instructions for a cycle, plus any delay slot
984 // instructions (which may overflow into successive cycles).
985 // This will advance S.getTime() to the last cycle in which
986 // instructions are actually issued.
988 unsigned numIssued = ChooseOneGroup(S);
989 assert(numIssued > 0 && "Deadlock in list scheduling algorithm?");
991 // Notify the priority manager of scheduled instructions and mark
992 // any successors that may now be ready
994 for (cycles_t c = nextCycle; c <= S.getTime(); c++) {
995 const InstrGroup* igroup = S.isched.getIGroup(c);
996 for (unsigned int s=0; s < S.nslots; s++)
997 if ((node = (*igroup)[s]) != NULL) {
998 S.schedPrio.issuedReadyNodeAt(S.getTime(), node);
999 MarkSuccessorsReady(S, node);
1003 // Move to the next the next earliest cycle for which
1004 // an instruction can be issued, or the next earliest in which
1005 // one will be ready, or to the next cycle, whichever is latest.
1007 S.updateTime(std::max(S.getTime() + 1,
1008 std::max(S.getEarliestIssueTime(),
1009 S.schedPrio.getEarliestReadyTime())));
1014 //---------------------------------------------------------------------
1015 // Code for filling delay slots for delayed terminator instructions
1016 // (e.g., BRANCH and RETURN). Delay slots for non-terminator
1017 // instructions (e.g., CALL) are not handled here because they almost
1018 // always can be filled with instructions from the call sequence code
1019 // before a call. That's preferable because we incur many tradeoffs here
1020 // when we cannot find single-cycle instructions that can be reordered.
1021 //----------------------------------------------------------------------
1024 NodeCanFillDelaySlot(const SchedulingManager& S,
1025 const SchedGraphNode* node,
1026 const SchedGraphNode* brNode,
1027 bool nodeIsPredecessor)
1029 assert(! node->isDummyNode());
1031 // don't put a branch in the delay slot of another branch
1032 if (S.getInstrInfo().isBranch(node->getOpcode()))
1035 // don't put a single-issue instruction in the delay slot of a branch
1036 if (S.schedInfo.isSingleIssue(node->getOpcode()))
1039 // don't put a load-use dependence in the delay slot of a branch
1040 const TargetInstrInfo& mii = S.getInstrInfo();
1042 for (SchedGraphNode::const_iterator EI = node->beginInEdges();
1043 EI != node->endInEdges(); ++EI)
1044 if (! ((SchedGraphNode*)(*EI)->getSrc())->isDummyNode()
1045 && mii.isLoad(((SchedGraphNode*)(*EI)->getSrc())->getOpcode())
1046 && (*EI)->getDepType() == SchedGraphEdge::CtrlDep)
1049 // Finally, if the instruction precedes the branch, we make sure the
1050 // instruction can be reordered relative to the branch. We simply check
1051 // if the instr. has only 1 outgoing edge, viz., a CD edge to the branch.
1053 if (nodeIsPredecessor) {
1054 bool onlyCDEdgeToBranch = true;
1055 for (SchedGraphNode::const_iterator OEI = node->beginOutEdges();
1056 OEI != node->endOutEdges(); ++OEI)
1057 if (! ((SchedGraphNode*)(*OEI)->getSink())->isDummyNode()
1058 && ((*OEI)->getSink() != brNode
1059 || (*OEI)->getDepType() != SchedGraphEdge::CtrlDep))
1061 onlyCDEdgeToBranch = false;
1065 if (!onlyCDEdgeToBranch)
1074 MarkNodeForDelaySlot(SchedulingManager& S,
1076 SchedGraphNode* node,
1077 const SchedGraphNode* brNode,
1078 bool nodeIsPredecessor)
1080 if (nodeIsPredecessor) {
1081 // If node is in the same basic block (i.e., precedes brNode),
1082 // remove it and all its incident edges from the graph. Make sure we
1083 // add dummy edges for pred/succ nodes that become entry/exit nodes.
1084 graph->eraseIncidentEdges(node, /*addDummyEdges*/ true);
1086 // If the node was from a target block, add the node to the graph
1087 // and add a CD edge from brNode to node.
1088 assert(0 && "NOT IMPLEMENTED YET");
1091 DelaySlotInfo* dinfo = S.getDelaySlotInfoForInstr(brNode, /*create*/ true);
1092 dinfo->addDelayNode(node);
1097 FindUsefulInstructionsForDelaySlots(SchedulingManager& S,
1098 SchedGraphNode* brNode,
1099 std::vector<SchedGraphNode*>& sdelayNodeVec)
1101 const TargetInstrInfo& mii = S.getInstrInfo();
1103 mii.getNumDelaySlots(brNode->getOpcode());
1108 sdelayNodeVec.reserve(ndelays);
1110 // Use a separate vector to hold the feasible multi-cycle nodes.
1111 // These will be used if not enough single-cycle nodes are found.
1113 std::vector<SchedGraphNode*> mdelayNodeVec;
1115 for (sg_pred_iterator P = pred_begin(brNode);
1116 P != pred_end(brNode) && sdelayNodeVec.size() < ndelays; ++P)
1117 if (! (*P)->isDummyNode() &&
1118 ! mii.isNop((*P)->getOpcode()) &&
1119 NodeCanFillDelaySlot(S, *P, brNode, /*pred*/ true))
1121 if (mii.maxLatency((*P)->getOpcode()) > 1)
1122 mdelayNodeVec.push_back(*P);
1124 sdelayNodeVec.push_back(*P);
1127 // If not enough single-cycle instructions were found, select the
1128 // lowest-latency multi-cycle instructions and use them.
1129 // Note that this is the most efficient code when only 1 (or even 2)
1130 // values need to be selected.
1132 while (sdelayNodeVec.size() < ndelays && mdelayNodeVec.size() > 0) {
1134 mii.maxLatency(mdelayNodeVec[0]->getOpcode());
1135 unsigned minIndex = 0;
1136 for (unsigned i=1; i < mdelayNodeVec.size(); i++)
1139 mii.maxLatency(mdelayNodeVec[i]->getOpcode());
1146 sdelayNodeVec.push_back(mdelayNodeVec[minIndex]);
1147 if (sdelayNodeVec.size() < ndelays) // avoid the last erase!
1148 mdelayNodeVec.erase(mdelayNodeVec.begin() + minIndex);
1153 // Remove the NOPs currently in delay slots from the graph.
1154 // Mark instructions specified in sdelayNodeVec to replace them.
1155 // If not enough useful instructions were found, mark the NOPs to be used
1156 // for filling delay slots, otherwise, otherwise just discard them.
1158 static void ReplaceNopsWithUsefulInstr(SchedulingManager& S,
1159 SchedGraphNode* node,
1160 // FIXME: passing vector BY VALUE!!!
1161 std::vector<SchedGraphNode*> sdelayNodeVec,
1164 std::vector<SchedGraphNode*> nopNodeVec; // this will hold unused NOPs
1165 const TargetInstrInfo& mii = S.getInstrInfo();
1166 const MachineInstr* brInstr = node->getMachineInstr();
1167 unsigned ndelays= mii.getNumDelaySlots(brInstr->getOpcode());
1168 assert(ndelays > 0 && "Unnecessary call to replace NOPs");
1170 // Remove the NOPs currently in delay slots from the graph.
1171 // If not enough useful instructions were found, use the NOPs to
1172 // fill delay slots, otherwise, just discard them.
1174 unsigned int firstDelaySlotIdx = node->getOrigIndexInBB() + 1;
1175 MachineBasicBlock& MBB = node->getMachineBasicBlock();
1176 MachineBasicBlock::iterator MBBI = MBB.begin();
1177 std::advance(MBBI, firstDelaySlotIdx - 1);
1178 if (!(&*MBBI++ == brInstr)) {
1179 std::cerr << "Incorrect instr. index in basic block for brInstr";
1183 // First find all useful instructions already in the delay slots
1184 // and USE THEM. We'll throw away the unused alternatives below
1186 MachineBasicBlock::iterator Tmp = MBBI;
1187 for (unsigned i = 0; i != ndelays; ++i, ++MBBI)
1188 if (!mii.isNop(MBBI->getOpcode()))
1189 sdelayNodeVec.insert(sdelayNodeVec.begin(),
1190 graph->getGraphNodeForInstr(MBBI));
1193 // Then find the NOPs and keep only as many as are needed.
1194 // Put the rest in nopNodeVec to be deleted.
1195 for (unsigned i=firstDelaySlotIdx; i < firstDelaySlotIdx+ndelays; ++i, ++MBBI)
1196 if (mii.isNop(MBBI->getOpcode()))
1197 if (sdelayNodeVec.size() < ndelays)
1198 sdelayNodeVec.push_back(graph->getGraphNodeForInstr(MBBI));
1200 nopNodeVec.push_back(graph->getGraphNodeForInstr(MBBI));
1202 //remove the MI from the Machine Code For Instruction
1203 const TerminatorInst *TI = MBB.getBasicBlock()->getTerminator();
1204 MachineCodeForInstruction& llvmMvec =
1205 MachineCodeForInstruction::get((const Instruction *)TI);
1207 for(MachineCodeForInstruction::iterator mciI=llvmMvec.begin(),
1208 mciE=llvmMvec.end(); mciI!=mciE; ++mciI){
1210 llvmMvec.erase(mciI);
1214 assert(sdelayNodeVec.size() >= ndelays);
1216 // If some delay slots were already filled, throw away that many new choices
1217 if (sdelayNodeVec.size() > ndelays)
1218 sdelayNodeVec.resize(ndelays);
1220 // Mark the nodes chosen for delay slots. This removes them from the graph.
1221 for (unsigned i=0; i < sdelayNodeVec.size(); i++)
1222 MarkNodeForDelaySlot(S, graph, sdelayNodeVec[i], node, true);
1224 // And remove the unused NOPs from the graph.
1225 for (unsigned i=0; i < nopNodeVec.size(); i++)
1226 graph->eraseIncidentEdges(nopNodeVec[i], /*addDummyEdges*/ true);
1230 // For all delayed instructions, choose instructions to put in the delay
1231 // slots and pull those out of the graph. Mark them for the delay slots
1232 // in the DelaySlotInfo object for that graph node. If no useful work
1233 // is found for a delay slot, use the NOP that is currently in that slot.
1235 // We try to fill the delay slots with useful work for all instructions
1236 // EXCEPT CALLS AND RETURNS.
1237 // For CALLs and RETURNs, it is nearly always possible to use one of the
1238 // call sequence instrs and putting anything else in the delay slot could be
1239 // suboptimal. Also, it complicates generating the calling sequence code in
1243 ChooseInstructionsForDelaySlots(SchedulingManager& S, MachineBasicBlock &MBB,
1246 const TargetInstrInfo& mii = S.getInstrInfo();
1248 Instruction *termInstr = (Instruction*)MBB.getBasicBlock()->getTerminator();
1249 MachineCodeForInstruction &termMvec=MachineCodeForInstruction::get(termInstr);
1250 std::vector<SchedGraphNode*> delayNodeVec;
1251 const MachineInstr* brInstr = NULL;
1253 if (EnableFillingDelaySlots &&
1254 termInstr->getOpcode() != Instruction::Ret)
1256 // To find instructions that need delay slots without searching the full
1257 // machine code, we assume that the only delayed instructions are CALLs
1258 // or instructions generated for the terminator inst.
1259 // Find the first branch instr in the sequence of machine instrs for term
1262 while (first < termMvec.size() &&
1263 ! mii.isBranch(termMvec[first]->getOpcode()))
1267 assert(first < termMvec.size() &&
1268 "No branch instructions for BR? Ok, but weird! Delete assertion.");
1270 brInstr = (first < termMvec.size())? termMvec[first] : NULL;
1272 // Compute a vector of the nodes chosen for delay slots and then
1273 // mark delay slots to replace NOPs with these useful instructions.
1275 if (brInstr != NULL) {
1276 SchedGraphNode* brNode = graph->getGraphNodeForInstr(brInstr);
1277 FindUsefulInstructionsForDelaySlots(S, brNode, delayNodeVec);
1278 ReplaceNopsWithUsefulInstr(S, brNode, delayNodeVec, graph);
1282 // Also mark delay slots for other delayed instructions to hold NOPs.
1283 // Simply passing in an empty delayNodeVec will have this effect.
1284 // If brInstr is not handled above (EnableFillingDelaySlots == false),
1285 // brInstr will be NULL so this will handle the branch instrs. as well.
1287 delayNodeVec.clear();
1288 for (MachineBasicBlock::iterator I = MBB.begin(), E = MBB.end(); I != E; ++I)
1289 if (I != brInstr && mii.getNumDelaySlots(I->getOpcode()) > 0) {
1290 SchedGraphNode* node = graph->getGraphNodeForInstr(I);
1291 ReplaceNopsWithUsefulInstr(S, node, delayNodeVec, graph);
1297 // Schedule the delayed branch and its delay slots
1300 DelaySlotInfo::scheduleDelayedNode(SchedulingManager& S)
1302 assert(delayedNodeSlotNum < S.nslots && "Illegal slot for branch");
1303 assert(S.isched.getInstr(delayedNodeSlotNum, delayedNodeCycle) == NULL
1304 && "Slot for branch should be empty");
1306 unsigned int nextSlot = delayedNodeSlotNum;
1307 cycles_t nextTime = delayedNodeCycle;
1309 S.scheduleInstr(brNode, nextSlot, nextTime);
1311 for (unsigned d=0; d < ndelays; d++) {
1313 if (nextSlot == S.nslots) {
1318 // Find the first feasible instruction for this delay slot
1319 // Note that we only check for issue restrictions here.
1320 // We do *not* check for flow dependences but rely on pipeline
1321 // interlocks to resolve them. Machines without interlocks
1322 // will require this code to be modified.
1323 for (unsigned i=0; i < delayNodeVec.size(); i++) {
1324 const SchedGraphNode* dnode = delayNodeVec[i];
1325 if ( ! S.isScheduled(dnode)
1326 && S.schedInfo.instrCanUseSlot(dnode->getOpcode(), nextSlot)
1327 && instrIsFeasible(S, dnode->getOpcode())) {
1328 S.scheduleInstr(dnode, nextSlot, nextTime);
1334 // Update current time if delay slots overflowed into later cycles.
1335 // Do this here because we know exactly which cycle is the last cycle
1336 // that contains delay slots. The next loop doesn't compute that.
1337 if (nextTime > S.getTime())
1338 S.updateTime(nextTime);
1340 // Now put any remaining instructions in the unfilled delay slots.
1341 // This could lead to suboptimal performance but needed for correctness.
1342 nextSlot = delayedNodeSlotNum;
1343 nextTime = delayedNodeCycle;
1344 for (unsigned i=0; i < delayNodeVec.size(); i++)
1345 if (! S.isScheduled(delayNodeVec[i])) {
1346 do { // find the next empty slot
1348 if (nextSlot == S.nslots) {
1352 } while (S.isched.getInstr(nextSlot, nextTime) != NULL);
1354 S.scheduleInstr(delayNodeVec[i], nextSlot, nextTime);
1362 // Check if the instruction would conflict with instructions already
1363 // chosen for the current cycle
1366 ConflictsWithChoices(const SchedulingManager& S,
1367 MachineOpCode opCode)
1369 // Check if the instruction must issue by itself, and some feasible
1370 // choices have already been made for this cycle
1371 if (S.getNumChoices() > 0 && S.schedInfo.isSingleIssue(opCode))
1374 // For each class that opCode belongs to, check if there are too many
1375 // instructions of that class.
1377 const InstrSchedClass sc = S.schedInfo.getSchedClass(opCode);
1378 return (S.getNumChoicesInClass(sc) == S.schedInfo.getMaxIssueForClass(sc));
1382 //************************* External Functions *****************************/
1385 //---------------------------------------------------------------------------
1386 // Function: ViolatesMinimumGap
1389 // Check minimum gap requirements relative to instructions scheduled in
1391 // Note that we do not need to consider `nextEarliestIssueTime' here because
1392 // that is also captured in the earliest start times for each opcode.
1393 //---------------------------------------------------------------------------
1396 ViolatesMinimumGap(const SchedulingManager& S,
1397 MachineOpCode opCode,
1398 const cycles_t inCycle)
1400 return (inCycle < S.getEarliestStartTimeForOp(opCode));
1404 //---------------------------------------------------------------------------
1405 // Function: instrIsFeasible
1408 // Check if any issue restrictions would prevent the instruction from
1409 // being issued in the current cycle
1410 //---------------------------------------------------------------------------
1413 instrIsFeasible(const SchedulingManager& S,
1414 MachineOpCode opCode)
1416 // skip the instruction if it cannot be issued due to issue restrictions
1417 // caused by previously issued instructions
1418 if (ViolatesMinimumGap(S, opCode, S.getTime()))
1421 // skip the instruction if it cannot be issued due to issue restrictions
1422 // caused by previously chosen instructions for the current cycle
1423 if (ConflictsWithChoices(S, opCode))
1429 //---------------------------------------------------------------------------
1430 // Function: ScheduleInstructionsWithSSA
1433 // Entry point for instruction scheduling on SSA form.
1434 // Schedules the machine instructions generated by instruction selection.
1435 // Assumes that register allocation has not been done, i.e., operands
1436 // are still in SSA form.
1437 //---------------------------------------------------------------------------
1440 class InstructionSchedulingWithSSA : public FunctionPass {
1441 const TargetMachine ⌖
1443 inline InstructionSchedulingWithSSA(const TargetMachine &T) : target(T) {}
1445 const char *getPassName() const { return "Instruction Scheduling"; }
1447 // getAnalysisUsage - We use LiveVarInfo...
1448 virtual void getAnalysisUsage(AnalysisUsage &AU) const {
1449 AU.addRequired<FunctionLiveVarInfo>();
1450 AU.setPreservesCFG();
1453 bool runOnFunction(Function &F);
1455 } // end anonymous namespace
1458 bool InstructionSchedulingWithSSA::runOnFunction(Function &F)
1460 SchedGraphSet graphSet(&F, target);
1462 if (SchedDebugLevel >= Sched_PrintSchedGraphs) {
1463 std::cerr << "\n*** SCHEDULING GRAPHS FOR INSTRUCTION SCHEDULING\n";
1467 for (SchedGraphSet::const_iterator GI=graphSet.begin(), GE=graphSet.end();
1470 SchedGraph* graph = (*GI);
1471 MachineBasicBlock &MBB = graph->getBasicBlock();
1473 if (SchedDebugLevel >= Sched_PrintSchedTrace)
1474 std::cerr << "\n*** TRACE OF INSTRUCTION SCHEDULING OPERATIONS\n\n";
1477 SchedPriorities schedPrio(&F, graph, getAnalysis<FunctionLiveVarInfo>());
1478 SchedulingManager S(target, graph, schedPrio);
1480 ChooseInstructionsForDelaySlots(S, MBB, graph); // modifies graph
1481 ForwardListSchedule(S); // computes schedule in S
1482 RecordSchedule(MBB, S); // records schedule in BB
1485 if (SchedDebugLevel >= Sched_PrintMachineCode) {
1486 std::cerr << "\n*** Machine instructions after INSTRUCTION SCHEDULING\n";
1487 MachineFunction::get(&F).dump();
1494 FunctionPass *createInstructionSchedulingWithSSAPass(const TargetMachine &tgt) {
1495 return new InstructionSchedulingWithSSA(tgt);
1498 } // End llvm namespace