1 //===- SparcV8Instrs.td - Target Description for SparcV8 Target -----------===//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by the LLVM research group and is distributed under
6 // the University of Illinois Open Source License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the SparcV8 instructions in TableGen format.
12 //===----------------------------------------------------------------------===//
14 //===----------------------------------------------------------------------===//
15 // Instruction format superclass
16 //===----------------------------------------------------------------------===//
18 class InstV8 : Instruction { // SparcV8 instruction baseline
24 let Inst{31-30} = op; // Top two bits are the 'op' field
26 // Bit attributes specific to SparcV8 instructions
27 bit isPasi = 0; // Does this instruction affect an alternate addr space?
28 bit isPrivileged = 0; // Is this a privileged instruction?
31 include "SparcV8InstrInfo_F2.td"
32 include "SparcV8InstrInfo_F3.td"
34 //===----------------------------------------------------------------------===//
36 //===----------------------------------------------------------------------===//
38 // Pseudo instructions.
42 def ADJCALLSTACKDOWN : InstV8 {
43 let Name = "ADJCALLSTACKDOWN";
45 def ADJCALLSTACKUP : InstV8 {
46 let Name = "ADJCALLSTACKUP";
49 // Section B.20: SAVE and RESTORE - p117
50 def SAVEr : F3_1<2, 0b111100, "save">; // save r, r, r
51 def SAVEi : F3_2<2, 0b111100, "save">; // save r, i, r
52 def RESTOREr : F3_1<2, 0b111101, "restore">; // restore r, r, r
53 def RESTOREi : F3_2<2, 0b111101, "restore">; // restore r, i, r
55 // Section B.24: Call and Link - p125
56 // This is the only Format 1 instruction
61 let Inst{29-0} = disp;
65 // Section B.25: Jump and Link - p126
66 def JMPLr : F3_1<2, 0b111000, "jmpl">; // jmpl [rs1+rs2], rd
67 def JMPLi : F3_2<2, 0b111000, "jmpl">; // jmpl [rs1+imm], rd