1 //===- SparcV8Instrs.td - Target Description for SparcV8 Target -----------===//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by the LLVM research group and is distributed under
6 // the University of Illinois Open Source License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the SparcV8 instructions in TableGen format.
12 //===----------------------------------------------------------------------===//
14 //===----------------------------------------------------------------------===//
15 // Instruction format superclass
16 //===----------------------------------------------------------------------===//
18 include "SparcV8InstrFormats.td"
20 //===----------------------------------------------------------------------===//
21 // Feature predicates.
22 //===----------------------------------------------------------------------===//
24 // HasV9 - This predicate is true when the target processor supports V9
25 // instructions. Note that the machine may be running in 32-bit mode.
26 def HasV9 : Predicate<"Subtarget.isV9()">;
28 // HasNoV9 - This predicate is true when the target doesn't have V9
29 // instructions. Use of this is just a hack for the isel not having proper
30 // costs for V8 instructions that are more expensive than their V9 ones.
31 def HasNoV9 : Predicate<"!Subtarget.isV9()">;
33 // HasVIS - This is true when the target processor has VIS extensions.
34 def HasVIS : Predicate<"Subtarget.isVIS()">;
36 // UseDeprecatedInsts - This predicate is true when the target processor is a
37 // V8, or when it is V9 but the V8 deprecated instructions are efficient enough
38 // to use when appropriate. In either of these cases, the instruction selector
39 // will pick deprecated instructions.
40 def UseDeprecatedInsts : Predicate<"Subtarget.useDeprecatedV8Instructions()">;
42 //===----------------------------------------------------------------------===//
43 // Instruction Pattern Stuff
44 //===----------------------------------------------------------------------===//
46 def simm11 : PatLeaf<(imm), [{
47 // simm11 predicate - True if the imm fits in a 11-bit sign extended field.
48 return (((int)N->getValue() << (32-11)) >> (32-11)) == (int)N->getValue();
51 def simm13 : PatLeaf<(imm), [{
52 // simm13 predicate - True if the imm fits in a 13-bit sign extended field.
53 return (((int)N->getValue() << (32-13)) >> (32-13)) == (int)N->getValue();
56 def LO10 : SDNodeXForm<imm, [{
57 return CurDAG->getTargetConstant((unsigned)N->getValue() & 1023, MVT::i32);
60 def HI22 : SDNodeXForm<imm, [{
61 // Transformation function: shift the immediate value down into the low bits.
62 return CurDAG->getTargetConstant((unsigned)N->getValue() >> 10, MVT::i32);
65 def SETHIimm : PatLeaf<(imm), [{
66 return (((unsigned)N->getValue() >> 10) << 10) == (unsigned)N->getValue();
70 def ADDRrr : ComplexPattern<i32, 2, "SelectADDRrr", []>;
71 def ADDRri : ComplexPattern<i32, 2, "SelectADDRri", []>;
74 def MEMrr : Operand<i32> {
75 let PrintMethod = "printMemOperand";
76 let NumMIOperands = 2;
77 let MIOperandInfo = (ops IntRegs, IntRegs);
79 def MEMri : Operand<i32> {
80 let PrintMethod = "printMemOperand";
81 let NumMIOperands = 2;
82 let MIOperandInfo = (ops IntRegs, i32imm);
85 // Branch targets have OtherVT type.
86 def brtarget : Operand<OtherVT>;
87 def calltarget : Operand<i32>;
89 // Operand for printing out a condition code.
90 let PrintMethod = "printV8CCOperand" in
91 def V8CC : Operand<i32>;
94 SDTypeProfile<1, 2, [SDTCisVT<0, FlagVT>, SDTCisFP<1>, SDTCisSameAs<1, 2>]>;
96 SDTypeProfile<0, 3, [SDTCisVT<0, OtherVT>, SDTCisVT<1, i32>,
97 SDTCisVT<2, FlagVT>]>;
99 SDTypeProfile<1, 4, [SDTCisSameAs<0, 1>, SDTCisSameAs<1, 2>,
100 SDTCisVT<3, i32>, SDTCisVT<4, FlagVT>]>;
102 SDTypeProfile<1, 1, [SDTCisVT<0, f32>, SDTCisFP<1>]>;
104 SDTypeProfile<1, 1, [SDTCisFP<0>, SDTCisVT<1, f32>]>;
106 def V8cmpicc : SDNode<"V8ISD::CMPICC", SDTIntBinOp, [SDNPOutFlag]>;
107 def V8cmpfcc : SDNode<"V8ISD::CMPFCC", SDTV8cmpfcc, [SDNPOutFlag]>;
108 def V8bricc : SDNode<"V8ISD::BRICC", SDTV8brcc, [SDNPHasChain]>;
109 def V8brfcc : SDNode<"V8ISD::BRFCC", SDTV8brcc, [SDNPHasChain]>;
111 def V8hi : SDNode<"V8ISD::Hi", SDTIntUnaryOp>;
112 def V8lo : SDNode<"V8ISD::Lo", SDTIntUnaryOp>;
114 def V8ftoi : SDNode<"V8ISD::FTOI", SDTV8FTOI>;
115 def V8itof : SDNode<"V8ISD::ITOF", SDTV8ITOF>;
117 def V8selecticc : SDNode<"V8ISD::SELECT_ICC", SDTV8selectcc>;
118 def V8selectfcc : SDNode<"V8ISD::SELECT_FCC", SDTV8selectcc>;
120 // These are target-independent nodes, but have target-specific formats.
121 def SDT_V8CallSeq : SDTypeProfile<0, 1, [ SDTCisVT<0, i32> ]>;
122 def callseq_start : SDNode<"ISD::CALLSEQ_START", SDT_V8CallSeq, [SDNPHasChain]>;
123 def callseq_end : SDNode<"ISD::CALLSEQ_END", SDT_V8CallSeq, [SDNPHasChain]>;
125 def SDT_V8Call : SDTypeProfile<0, 1, [SDTCisVT<0, i32>]>;
126 def call : SDNode<"V8ISD::CALL", SDT_V8Call,
127 [SDNPHasChain, SDNPOptInFlag, SDNPOutFlag]>;
129 def SDT_V8RetFlag : SDTypeProfile<0, 0, []>;
130 def retflag : SDNode<"V8ISD::RET_FLAG", SDT_V8RetFlag,
131 [SDNPHasChain, SDNPOptInFlag]>;
133 //===----------------------------------------------------------------------===//
134 // SPARC Flag Conditions
135 //===----------------------------------------------------------------------===//
137 // Note that these values must be kept in sync with the V8CC::CondCode enum
139 class ICC_VAL<int N> : PatLeaf<(i32 N)>;
140 def ICC_NE : ICC_VAL< 9>; // Not Equal
141 def ICC_E : ICC_VAL< 1>; // Equal
142 def ICC_G : ICC_VAL<10>; // Greater
143 def ICC_LE : ICC_VAL< 2>; // Less or Equal
144 def ICC_GE : ICC_VAL<11>; // Greater or Equal
145 def ICC_L : ICC_VAL< 3>; // Less
146 def ICC_GU : ICC_VAL<12>; // Greater Unsigned
147 def ICC_LEU : ICC_VAL< 4>; // Less or Equal Unsigned
148 def ICC_CC : ICC_VAL<13>; // Carry Clear/Great or Equal Unsigned
149 def ICC_CS : ICC_VAL< 5>; // Carry Set/Less Unsigned
150 def ICC_POS : ICC_VAL<14>; // Positive
151 def ICC_NEG : ICC_VAL< 6>; // Negative
152 def ICC_VC : ICC_VAL<15>; // Overflow Clear
153 def ICC_VS : ICC_VAL< 7>; // Overflow Set
155 class FCC_VAL<int N> : PatLeaf<(i32 N)>;
156 def FCC_U : FCC_VAL<23>; // Unordered
157 def FCC_G : FCC_VAL<22>; // Greater
158 def FCC_UG : FCC_VAL<21>; // Unordered or Greater
159 def FCC_L : FCC_VAL<20>; // Less
160 def FCC_UL : FCC_VAL<19>; // Unordered or Less
161 def FCC_LG : FCC_VAL<18>; // Less or Greater
162 def FCC_NE : FCC_VAL<17>; // Not Equal
163 def FCC_E : FCC_VAL<25>; // Equal
164 def FCC_UE : FCC_VAL<24>; // Unordered or Equal
165 def FCC_GE : FCC_VAL<25>; // Greater or Equal
166 def FCC_UGE : FCC_VAL<26>; // Unordered or Greater or Equal
167 def FCC_LE : FCC_VAL<27>; // Less or Equal
168 def FCC_ULE : FCC_VAL<28>; // Unordered or Less or Equal
169 def FCC_O : FCC_VAL<29>; // Ordered
172 //===----------------------------------------------------------------------===//
174 //===----------------------------------------------------------------------===//
176 // Pseudo instructions.
177 class Pseudo<dag ops, string asmstr, list<dag> pattern>
178 : InstV8<ops, asmstr, pattern>;
180 def ADJCALLSTACKDOWN : Pseudo<(ops i32imm:$amt),
181 "!ADJCALLSTACKDOWN $amt",
182 [(callseq_start imm:$amt)]>;
183 def ADJCALLSTACKUP : Pseudo<(ops i32imm:$amt),
184 "!ADJCALLSTACKUP $amt",
185 [(callseq_end imm:$amt)]>;
186 def IMPLICIT_DEF_Int : Pseudo<(ops IntRegs:$dst),
187 "!IMPLICIT_DEF $dst",
188 [(set IntRegs:$dst, (undef))]>;
189 def IMPLICIT_DEF_FP : Pseudo<(ops FPRegs:$dst), "!IMPLICIT_DEF $dst",
190 [(set FPRegs:$dst, (undef))]>;
191 def IMPLICIT_DEF_DFP : Pseudo<(ops DFPRegs:$dst), "!IMPLICIT_DEF $dst",
192 [(set DFPRegs:$dst, (undef))]>;
194 // FpMOVD/FpNEGD/FpABSD - These are lowered to single-precision ops by the
196 let Predicates = [HasNoV9] in { // Only emit these in V8 mode.
197 def FpMOVD : Pseudo<(ops DFPRegs:$dst, DFPRegs:$src),
198 "!FpMOVD $src, $dst", []>;
199 def FpNEGD : Pseudo<(ops DFPRegs:$dst, DFPRegs:$src),
200 "!FpNEGD $src, $dst",
201 [(set DFPRegs:$dst, (fneg DFPRegs:$src))]>;
202 def FpABSD : Pseudo<(ops DFPRegs:$dst, DFPRegs:$src),
203 "!FpABSD $src, $dst",
204 [(set DFPRegs:$dst, (fabs DFPRegs:$src))]>;
207 // SELECT_CC_* - Used to implement the SELECT_CC DAG operation. Expanded by the
208 // scheduler into a branch sequence. This has to handle all permutations of
209 // selection between i32/f32/f64 on ICC and FCC.
210 let usesCustomDAGSchedInserter = 1, // Expanded by the scheduler.
211 Predicates = [HasNoV9] in { // V9 has conditional moves
212 def SELECT_CC_Int_ICC
213 : Pseudo<(ops IntRegs:$dst, IntRegs:$T, IntRegs:$F, i32imm:$Cond),
214 "; SELECT_CC_Int_ICC PSEUDO!",
215 [(set IntRegs:$dst, (V8selecticc IntRegs:$T, IntRegs:$F,
217 def SELECT_CC_Int_FCC
218 : Pseudo<(ops IntRegs:$dst, IntRegs:$T, IntRegs:$F, i32imm:$Cond),
219 "; SELECT_CC_Int_FCC PSEUDO!",
220 [(set IntRegs:$dst, (V8selectfcc IntRegs:$T, IntRegs:$F,
223 : Pseudo<(ops FPRegs:$dst, FPRegs:$T, FPRegs:$F, i32imm:$Cond),
224 "; SELECT_CC_FP_ICC PSEUDO!",
225 [(set FPRegs:$dst, (V8selecticc FPRegs:$T, FPRegs:$F,
228 : Pseudo<(ops FPRegs:$dst, FPRegs:$T, FPRegs:$F, i32imm:$Cond),
229 "; SELECT_CC_FP_FCC PSEUDO!",
230 [(set FPRegs:$dst, (V8selectfcc FPRegs:$T, FPRegs:$F,
232 def SELECT_CC_DFP_ICC
233 : Pseudo<(ops DFPRegs:$dst, DFPRegs:$T, DFPRegs:$F, i32imm:$Cond),
234 "; SELECT_CC_DFP_ICC PSEUDO!",
235 [(set DFPRegs:$dst, (V8selecticc DFPRegs:$T, DFPRegs:$F,
237 def SELECT_CC_DFP_FCC
238 : Pseudo<(ops DFPRegs:$dst, DFPRegs:$T, DFPRegs:$F, i32imm:$Cond),
239 "; SELECT_CC_DFP_FCC PSEUDO!",
240 [(set DFPRegs:$dst, (V8selectfcc DFPRegs:$T, DFPRegs:$F,
245 // Section A.3 - Synthetic Instructions, p. 85
246 // special cases of JMPL:
247 let isReturn = 1, isTerminator = 1, hasDelaySlot = 1, noResults = 1 in {
248 let rd = O7.Num, rs1 = G0.Num, simm13 = 8 in
249 def RETL: F3_2<2, 0b111000, (ops), "retl", [(retflag)]>;
252 // Section B.1 - Load Integer Instructions, p. 90
253 def LDSBrr : F3_1<3, 0b001001,
254 (ops IntRegs:$dst, MEMrr:$addr),
255 "ldsb [$addr], $dst",
256 [(set IntRegs:$dst, (sextload ADDRrr:$addr, i8))]>;
257 def LDSBri : F3_2<3, 0b001001,
258 (ops IntRegs:$dst, MEMri:$addr),
259 "ldsb [$addr], $dst",
260 [(set IntRegs:$dst, (sextload ADDRri:$addr, i8))]>;
261 def LDSHrr : F3_1<3, 0b001010,
262 (ops IntRegs:$dst, MEMrr:$addr),
263 "ldsh [$addr], $dst",
264 [(set IntRegs:$dst, (sextload ADDRrr:$addr, i16))]>;
265 def LDSHri : F3_2<3, 0b001010,
266 (ops IntRegs:$dst, MEMri:$addr),
267 "ldsh [$addr], $dst",
268 [(set IntRegs:$dst, (sextload ADDRri:$addr, i16))]>;
269 def LDUBrr : F3_1<3, 0b000001,
270 (ops IntRegs:$dst, MEMrr:$addr),
271 "ldub [$addr], $dst",
272 [(set IntRegs:$dst, (zextload ADDRrr:$addr, i8))]>;
273 def LDUBri : F3_2<3, 0b000001,
274 (ops IntRegs:$dst, MEMri:$addr),
275 "ldub [$addr], $dst",
276 [(set IntRegs:$dst, (zextload ADDRri:$addr, i8))]>;
277 def LDUHrr : F3_1<3, 0b000010,
278 (ops IntRegs:$dst, MEMrr:$addr),
279 "lduh [$addr], $dst",
280 [(set IntRegs:$dst, (zextload ADDRrr:$addr, i16))]>;
281 def LDUHri : F3_2<3, 0b000010,
282 (ops IntRegs:$dst, MEMri:$addr),
283 "lduh [$addr], $dst",
284 [(set IntRegs:$dst, (zextload ADDRri:$addr, i16))]>;
285 def LDrr : F3_1<3, 0b000000,
286 (ops IntRegs:$dst, MEMrr:$addr),
288 [(set IntRegs:$dst, (load ADDRrr:$addr))]>;
289 def LDri : F3_2<3, 0b000000,
290 (ops IntRegs:$dst, MEMri:$addr),
292 [(set IntRegs:$dst, (load ADDRri:$addr))]>;
294 // Section B.2 - Load Floating-point Instructions, p. 92
295 def LDFrr : F3_1<3, 0b100000,
296 (ops FPRegs:$dst, MEMrr:$addr),
298 [(set FPRegs:$dst, (load ADDRrr:$addr))]>;
299 def LDFri : F3_2<3, 0b100000,
300 (ops FPRegs:$dst, MEMri:$addr),
302 [(set FPRegs:$dst, (load ADDRri:$addr))]>;
303 def LDDFrr : F3_1<3, 0b100011,
304 (ops DFPRegs:$dst, MEMrr:$addr),
306 [(set DFPRegs:$dst, (load ADDRrr:$addr))]>;
307 def LDDFri : F3_2<3, 0b100011,
308 (ops DFPRegs:$dst, MEMri:$addr),
310 [(set DFPRegs:$dst, (load ADDRri:$addr))]>;
312 // Section B.4 - Store Integer Instructions, p. 95
313 def STBrr : F3_1<3, 0b000101,
314 (ops MEMrr:$addr, IntRegs:$src),
316 [(truncstore IntRegs:$src, ADDRrr:$addr, i8)]>;
317 def STBri : F3_2<3, 0b000101,
318 (ops MEMri:$addr, IntRegs:$src),
320 [(truncstore IntRegs:$src, ADDRri:$addr, i8)]>;
321 def STHrr : F3_1<3, 0b000110,
322 (ops MEMrr:$addr, IntRegs:$src),
324 [(truncstore IntRegs:$src, ADDRrr:$addr, i16)]>;
325 def STHri : F3_2<3, 0b000110,
326 (ops MEMri:$addr, IntRegs:$src),
328 [(truncstore IntRegs:$src, ADDRri:$addr, i16)]>;
329 def STrr : F3_1<3, 0b000100,
330 (ops MEMrr:$addr, IntRegs:$src),
332 [(store IntRegs:$src, ADDRrr:$addr)]>;
333 def STri : F3_2<3, 0b000100,
334 (ops MEMri:$addr, IntRegs:$src),
336 [(store IntRegs:$src, ADDRri:$addr)]>;
338 // Section B.5 - Store Floating-point Instructions, p. 97
339 def STFrr : F3_1<3, 0b100100,
340 (ops MEMrr:$addr, FPRegs:$src),
342 [(store FPRegs:$src, ADDRrr:$addr)]>;
343 def STFri : F3_2<3, 0b100100,
344 (ops MEMri:$addr, FPRegs:$src),
346 [(store FPRegs:$src, ADDRri:$addr)]>;
347 def STDFrr : F3_1<3, 0b100111,
348 (ops MEMrr:$addr, DFPRegs:$src),
350 [(store DFPRegs:$src, ADDRrr:$addr)]>;
351 def STDFri : F3_2<3, 0b100111,
352 (ops MEMri:$addr, DFPRegs:$src),
354 [(store DFPRegs:$src, ADDRri:$addr)]>;
356 // Section B.9 - SETHI Instruction, p. 104
357 def SETHIi: F2_1<0b100,
358 (ops IntRegs:$dst, i32imm:$src),
360 [(set IntRegs:$dst, SETHIimm:$src)]>;
362 // Section B.10 - NOP Instruction, p. 105
363 // (It's a special case of SETHI)
364 let rd = 0, imm22 = 0 in
365 def NOP : F2_1<0b100, (ops), "nop", []>;
367 // Section B.11 - Logical Instructions, p. 106
368 def ANDrr : F3_1<2, 0b000001,
369 (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c),
371 [(set IntRegs:$dst, (and IntRegs:$b, IntRegs:$c))]>;
372 def ANDri : F3_2<2, 0b000001,
373 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c),
375 [(set IntRegs:$dst, (and IntRegs:$b, simm13:$c))]>;
376 def ANDNrr : F3_1<2, 0b000101,
377 (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c),
379 [(set IntRegs:$dst, (and IntRegs:$b, (not IntRegs:$c)))]>;
380 def ANDNri : F3_2<2, 0b000101,
381 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c),
382 "andn $b, $c, $dst", []>;
383 def ORrr : F3_1<2, 0b000010,
384 (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c),
386 [(set IntRegs:$dst, (or IntRegs:$b, IntRegs:$c))]>;
387 def ORri : F3_2<2, 0b000010,
388 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c),
390 [(set IntRegs:$dst, (or IntRegs:$b, simm13:$c))]>;
391 def ORNrr : F3_1<2, 0b000110,
392 (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c),
394 [(set IntRegs:$dst, (or IntRegs:$b, (not IntRegs:$c)))]>;
395 def ORNri : F3_2<2, 0b000110,
396 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c),
397 "orn $b, $c, $dst", []>;
398 def XORrr : F3_1<2, 0b000011,
399 (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c),
401 [(set IntRegs:$dst, (xor IntRegs:$b, IntRegs:$c))]>;
402 def XORri : F3_2<2, 0b000011,
403 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c),
405 [(set IntRegs:$dst, (xor IntRegs:$b, simm13:$c))]>;
406 def XNORrr : F3_1<2, 0b000111,
407 (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c),
409 [(set IntRegs:$dst, (not (xor IntRegs:$b, IntRegs:$c)))]>;
410 def XNORri : F3_2<2, 0b000111,
411 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c),
412 "xnor $b, $c, $dst", []>;
414 // Section B.12 - Shift Instructions, p. 107
415 def SLLrr : F3_1<2, 0b100101,
416 (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c),
418 [(set IntRegs:$dst, (shl IntRegs:$b, IntRegs:$c))]>;
419 def SLLri : F3_2<2, 0b100101,
420 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c),
422 [(set IntRegs:$dst, (shl IntRegs:$b, simm13:$c))]>;
423 def SRLrr : F3_1<2, 0b100110,
424 (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c),
426 [(set IntRegs:$dst, (srl IntRegs:$b, IntRegs:$c))]>;
427 def SRLri : F3_2<2, 0b100110,
428 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c),
430 [(set IntRegs:$dst, (srl IntRegs:$b, simm13:$c))]>;
431 def SRArr : F3_1<2, 0b100111,
432 (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c),
434 [(set IntRegs:$dst, (sra IntRegs:$b, IntRegs:$c))]>;
435 def SRAri : F3_2<2, 0b100111,
436 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c),
438 [(set IntRegs:$dst, (sra IntRegs:$b, simm13:$c))]>;
440 // Section B.13 - Add Instructions, p. 108
441 def ADDrr : F3_1<2, 0b000000,
442 (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c),
444 [(set IntRegs:$dst, (add IntRegs:$b, IntRegs:$c))]>;
445 def ADDri : F3_2<2, 0b000000,
446 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c),
448 [(set IntRegs:$dst, (add IntRegs:$b, simm13:$c))]>;
449 def ADDCCrr : F3_1<2, 0b010000,
450 (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c),
451 "addcc $b, $c, $dst", []>;
452 def ADDCCri : F3_2<2, 0b010000,
453 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c),
454 "addcc $b, $c, $dst", []>;
455 def ADDXrr : F3_1<2, 0b001000,
456 (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c),
457 "addx $b, $c, $dst", []>;
458 def ADDXri : F3_2<2, 0b001000,
459 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c),
460 "addx $b, $c, $dst", []>;
462 // Section B.15 - Subtract Instructions, p. 110
463 def SUBrr : F3_1<2, 0b000100,
464 (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c),
466 [(set IntRegs:$dst, (sub IntRegs:$b, IntRegs:$c))]>;
467 def SUBri : F3_2<2, 0b000100,
468 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c),
470 [(set IntRegs:$dst, (sub IntRegs:$b, simm13:$c))]>;
471 def SUBXrr : F3_1<2, 0b001100,
472 (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c),
473 "subx $b, $c, $dst", []>;
474 def SUBXri : F3_2<2, 0b001100,
475 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c),
476 "subx $b, $c, $dst", []>;
477 def SUBCCrr : F3_1<2, 0b010100,
478 (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c),
479 "subcc $b, $c, $dst",
480 [(set IntRegs:$dst, (V8cmpicc IntRegs:$b, IntRegs:$c))]>;
481 def SUBCCri : F3_2<2, 0b010100,
482 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c),
483 "subcc $b, $c, $dst",
484 [(set IntRegs:$dst, (V8cmpicc IntRegs:$b, simm13:$c))]>;
485 def SUBXCCrr: F3_1<2, 0b011100,
486 (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c),
487 "subxcc $b, $c, $dst", []>;
489 // Section B.18 - Multiply Instructions, p. 113
490 def UMULrr : F3_1<2, 0b001010,
491 (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c),
492 "umul $b, $c, $dst", []>;
493 def UMULri : F3_2<2, 0b001010,
494 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c),
495 "umul $b, $c, $dst", []>;
496 def SMULrr : F3_1<2, 0b001011,
497 (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c),
499 [(set IntRegs:$dst, (mul IntRegs:$b, IntRegs:$c))]>;
500 def SMULri : F3_2<2, 0b001011,
501 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c),
503 [(set IntRegs:$dst, (mul IntRegs:$b, simm13:$c))]>;
505 // Section B.19 - Divide Instructions, p. 115
506 def UDIVrr : F3_1<2, 0b001110,
507 (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c),
508 "udiv $b, $c, $dst", []>;
509 def UDIVri : F3_2<2, 0b001110,
510 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c),
511 "udiv $b, $c, $dst", []>;
512 def SDIVrr : F3_1<2, 0b001111,
513 (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c),
514 "sdiv $b, $c, $dst", []>;
515 def SDIVri : F3_2<2, 0b001111,
516 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c),
517 "sdiv $b, $c, $dst", []>;
519 // Section B.20 - SAVE and RESTORE, p. 117
520 def SAVErr : F3_1<2, 0b111100,
521 (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c),
522 "save $b, $c, $dst", []>;
523 def SAVEri : F3_2<2, 0b111100,
524 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c),
525 "save $b, $c, $dst", []>;
526 def RESTORErr : F3_1<2, 0b111101,
527 (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c),
528 "restore $b, $c, $dst", []>;
529 def RESTOREri : F3_2<2, 0b111101,
530 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c),
531 "restore $b, $c, $dst", []>;
533 // Section B.21 - Branch on Integer Condition Codes Instructions, p. 119
535 // conditional branch class:
536 class BranchV8<bits<4> cc, dag ops, string asmstr, list<dag> pattern>
537 : F2_2<cc, 0b010, ops, asmstr, pattern> {
539 let isTerminator = 1;
540 let hasDelaySlot = 1;
545 def BA : BranchV8<0b1000, (ops brtarget:$dst),
549 // FIXME: the encoding for the JIT should look at the condition field.
550 def BCOND : BranchV8<0, (ops brtarget:$dst, V8CC:$cc),
552 [(V8bricc bb:$dst, imm:$cc, ICC)]>;
555 // Section B.22 - Branch on Floating-point Condition Codes Instructions, p. 121
557 // floating-point conditional branch class:
558 class FPBranchV8<bits<4> cc, dag ops, string asmstr, list<dag> pattern>
559 : F2_2<cc, 0b110, ops, asmstr, pattern> {
561 let isTerminator = 1;
562 let hasDelaySlot = 1;
566 // FIXME: the encoding for the JIT should look at the condition field.
567 def FBCOND : FPBranchV8<0, (ops brtarget:$dst, V8CC:$cc),
569 [(V8brfcc bb:$dst, imm:$cc, FCC)]>;
572 // Section B.24 - Call and Link Instruction, p. 125
573 // This is the only Format 1 instruction
574 let Uses = [O0, O1, O2, O3, O4, O5],
575 hasDelaySlot = 1, isCall = 1, noResults = 1,
576 Defs = [O0, O1, O2, O3, O4, O5, O7, G1, G2, G3, G4, G5, G6, G7,
577 D0, D1, D2, D3, D4, D5, D6, D7, D8, D9, D10, D11, D12, D13, D14, D15] in {
578 def CALL : InstV8<(ops calltarget:$dst),
582 let Inst{29-0} = disp;
586 def JMPLrr : F3_1<2, 0b111000,
589 [(call ADDRrr:$ptr)]>;
590 def JMPLri : F3_2<2, 0b111000,
593 [(call ADDRri:$ptr)]>;
596 // Section B.28 - Read State Register Instructions
597 def RDY : F3_1<2, 0b101000,
601 // Section B.29 - Write State Register Instructions
602 def WRYrr : F3_1<2, 0b110000,
603 (ops IntRegs:$b, IntRegs:$c),
604 "wr $b, $c, %y", []>;
605 def WRYri : F3_2<2, 0b110000,
606 (ops IntRegs:$b, i32imm:$c),
607 "wr $b, $c, %y", []>;
609 // Convert Integer to Floating-point Instructions, p. 141
610 def FITOS : F3_3<2, 0b110100, 0b011000100,
611 (ops FPRegs:$dst, FPRegs:$src),
613 [(set FPRegs:$dst, (V8itof FPRegs:$src))]>;
614 def FITOD : F3_3<2, 0b110100, 0b011001000,
615 (ops DFPRegs:$dst, FPRegs:$src),
617 [(set DFPRegs:$dst, (V8itof FPRegs:$src))]>;
619 // Convert Floating-point to Integer Instructions, p. 142
620 def FSTOI : F3_3<2, 0b110100, 0b011010001,
621 (ops FPRegs:$dst, FPRegs:$src),
623 [(set FPRegs:$dst, (V8ftoi FPRegs:$src))]>;
624 def FDTOI : F3_3<2, 0b110100, 0b011010010,
625 (ops FPRegs:$dst, DFPRegs:$src),
627 [(set FPRegs:$dst, (V8ftoi DFPRegs:$src))]>;
629 // Convert between Floating-point Formats Instructions, p. 143
630 def FSTOD : F3_3<2, 0b110100, 0b011001001,
631 (ops DFPRegs:$dst, FPRegs:$src),
633 [(set DFPRegs:$dst, (fextend FPRegs:$src))]>;
634 def FDTOS : F3_3<2, 0b110100, 0b011000110,
635 (ops FPRegs:$dst, DFPRegs:$src),
637 [(set FPRegs:$dst, (fround DFPRegs:$src))]>;
639 // Floating-point Move Instructions, p. 144
640 def FMOVS : F3_3<2, 0b110100, 0b000000001,
641 (ops FPRegs:$dst, FPRegs:$src),
642 "fmovs $src, $dst", []>;
643 def FNEGS : F3_3<2, 0b110100, 0b000000101,
644 (ops FPRegs:$dst, FPRegs:$src),
646 [(set FPRegs:$dst, (fneg FPRegs:$src))]>;
647 def FABSS : F3_3<2, 0b110100, 0b000001001,
648 (ops FPRegs:$dst, FPRegs:$src),
650 [(set FPRegs:$dst, (fabs FPRegs:$src))]>;
653 // Floating-point Square Root Instructions, p.145
654 def FSQRTS : F3_3<2, 0b110100, 0b000101001,
655 (ops FPRegs:$dst, FPRegs:$src),
657 [(set FPRegs:$dst, (fsqrt FPRegs:$src))]>;
658 def FSQRTD : F3_3<2, 0b110100, 0b000101010,
659 (ops DFPRegs:$dst, DFPRegs:$src),
661 [(set DFPRegs:$dst, (fsqrt DFPRegs:$src))]>;
665 // Floating-point Add and Subtract Instructions, p. 146
666 def FADDS : F3_3<2, 0b110100, 0b001000001,
667 (ops FPRegs:$dst, FPRegs:$src1, FPRegs:$src2),
668 "fadds $src1, $src2, $dst",
669 [(set FPRegs:$dst, (fadd FPRegs:$src1, FPRegs:$src2))]>;
670 def FADDD : F3_3<2, 0b110100, 0b001000010,
671 (ops DFPRegs:$dst, DFPRegs:$src1, DFPRegs:$src2),
672 "faddd $src1, $src2, $dst",
673 [(set DFPRegs:$dst, (fadd DFPRegs:$src1, DFPRegs:$src2))]>;
674 def FSUBS : F3_3<2, 0b110100, 0b001000101,
675 (ops FPRegs:$dst, FPRegs:$src1, FPRegs:$src2),
676 "fsubs $src1, $src2, $dst",
677 [(set FPRegs:$dst, (fsub FPRegs:$src1, FPRegs:$src2))]>;
678 def FSUBD : F3_3<2, 0b110100, 0b001000110,
679 (ops DFPRegs:$dst, DFPRegs:$src1, DFPRegs:$src2),
680 "fsubd $src1, $src2, $dst",
681 [(set DFPRegs:$dst, (fsub DFPRegs:$src1, DFPRegs:$src2))]>;
683 // Floating-point Multiply and Divide Instructions, p. 147
684 def FMULS : F3_3<2, 0b110100, 0b001001001,
685 (ops FPRegs:$dst, FPRegs:$src1, FPRegs:$src2),
686 "fmuls $src1, $src2, $dst",
687 [(set FPRegs:$dst, (fmul FPRegs:$src1, FPRegs:$src2))]>;
688 def FMULD : F3_3<2, 0b110100, 0b001001010,
689 (ops DFPRegs:$dst, DFPRegs:$src1, DFPRegs:$src2),
690 "fmuld $src1, $src2, $dst",
691 [(set DFPRegs:$dst, (fmul DFPRegs:$src1, DFPRegs:$src2))]>;
692 def FSMULD : F3_3<2, 0b110100, 0b001101001,
693 (ops DFPRegs:$dst, FPRegs:$src1, FPRegs:$src2),
694 "fsmuld $src1, $src2, $dst",
695 [(set DFPRegs:$dst, (fmul (fextend FPRegs:$src1),
696 (fextend FPRegs:$src2)))]>;
697 def FDIVS : F3_3<2, 0b110100, 0b001001101,
698 (ops FPRegs:$dst, FPRegs:$src1, FPRegs:$src2),
699 "fdivs $src1, $src2, $dst",
700 [(set FPRegs:$dst, (fdiv FPRegs:$src1, FPRegs:$src2))]>;
701 def FDIVD : F3_3<2, 0b110100, 0b001001110,
702 (ops DFPRegs:$dst, DFPRegs:$src1, DFPRegs:$src2),
703 "fdivd $src1, $src2, $dst",
704 [(set DFPRegs:$dst, (fdiv DFPRegs:$src1, DFPRegs:$src2))]>;
706 // Floating-point Compare Instructions, p. 148
707 // Note: the 2nd template arg is different for these guys.
708 // Note 2: the result of a FCMP is not available until the 2nd cycle
709 // after the instr is retired, but there is no interlock. This behavior
710 // is modelled with a forced noop after the instruction.
711 def FCMPS : F3_3<2, 0b110101, 0b001010001,
712 (ops FPRegs:$src1, FPRegs:$src2),
713 "fcmps $src1, $src2\n\tnop",
714 [(set FCC, (V8cmpfcc FPRegs:$src1, FPRegs:$src2))]>;
715 def FCMPD : F3_3<2, 0b110101, 0b001010010,
716 (ops DFPRegs:$src1, DFPRegs:$src2),
717 "fcmpd $src1, $src2\n\tnop",
718 [(set FCC, (V8cmpfcc DFPRegs:$src1, DFPRegs:$src2))]>;
721 //===----------------------------------------------------------------------===//
723 //===----------------------------------------------------------------------===//
725 // V9 Conditional Moves.
726 let Predicates = [HasV9], isTwoAddress = 1 in {
727 // Move Integer Register on Condition (MOVcc) p. 194 of the V9 manual.
728 // FIXME: Add instruction encodings for the JIT some day.
730 : Pseudo<(ops IntRegs:$dst, IntRegs:$T, IntRegs:$F, V8CC:$cc),
731 "mov$cc %icc, $F, $dst",
733 (V8selecticc IntRegs:$F, IntRegs:$T, imm:$cc, ICC))]>;
735 : Pseudo<(ops IntRegs:$dst, IntRegs:$T, i32imm:$F, V8CC:$cc),
736 "mov$cc %icc, $F, $dst",
738 (V8selecticc simm11:$F, IntRegs:$T, imm:$cc, ICC))]>;
741 : Pseudo<(ops IntRegs:$dst, IntRegs:$T, IntRegs:$F, V8CC:$cc),
742 "mov$cc %fcc0, $F, $dst",
744 (V8selectfcc IntRegs:$F, IntRegs:$T, imm:$cc, FCC))]>;
746 : Pseudo<(ops IntRegs:$dst, IntRegs:$T, i32imm:$F, V8CC:$cc),
747 "mov$cc %fcc0, $F, $dst",
749 (V8selectfcc simm11:$F, IntRegs:$T, imm:$cc, FCC))]>;
752 : Pseudo<(ops FPRegs:$dst, FPRegs:$T, FPRegs:$F, V8CC:$cc),
753 "fmovs$cc %icc, $F, $dst",
755 (V8selecticc FPRegs:$F, FPRegs:$T, imm:$cc, ICC))]>;
757 : Pseudo<(ops DFPRegs:$dst, DFPRegs:$T, DFPRegs:$F, V8CC:$cc),
758 "fmovd$cc %icc, $F, $dst",
760 (V8selecticc DFPRegs:$F, DFPRegs:$T, imm:$cc, ICC))]>;
762 : Pseudo<(ops FPRegs:$dst, FPRegs:$T, FPRegs:$F, V8CC:$cc),
763 "fmovs$cc %fcc0, $F, $dst",
765 (V8selectfcc FPRegs:$F, FPRegs:$T, imm:$cc, FCC))]>;
767 : Pseudo<(ops DFPRegs:$dst, DFPRegs:$T, DFPRegs:$F, V8CC:$cc),
768 "fmovd$cc %fcc0, $F, $dst",
770 (V8selectfcc DFPRegs:$F, DFPRegs:$T, imm:$cc, FCC))]>;
774 // Floating-Point Move Instructions, p. 164 of the V9 manual.
775 let Predicates = [HasV9] in {
776 def FMOVD : F3_3<2, 0b110100, 0b000000010,
777 (ops DFPRegs:$dst, DFPRegs:$src),
778 "fmovd $src, $dst", []>;
779 def FNEGD : F3_3<2, 0b110100, 0b000000110,
780 (ops DFPRegs:$dst, DFPRegs:$src),
782 [(set DFPRegs:$dst, (fneg DFPRegs:$src))]>;
783 def FABSD : F3_3<2, 0b110100, 0b000001010,
784 (ops DFPRegs:$dst, DFPRegs:$src),
786 [(set DFPRegs:$dst, (fabs DFPRegs:$src))]>;
789 // POPCrr - This does a ctpop of a 64-bit register. As such, we have to clear
790 // the top 32-bits before using it. To do this clearing, we use a SLLri X,0.
791 def POPCrr : F3_1<2, 0b101110,
792 (ops IntRegs:$dst, IntRegs:$src),
793 "popc $src, $dst", []>, Requires<[HasV9]>;
794 def : Pat<(ctpop IntRegs:$src),
795 (POPCrr (SLLri IntRegs:$src, 0))>;
797 //===----------------------------------------------------------------------===//
798 // Non-Instruction Patterns
799 //===----------------------------------------------------------------------===//
802 def : Pat<(i32 simm13:$val),
803 (ORri G0, imm:$val)>;
804 // Arbitrary immediates.
805 def : Pat<(i32 imm:$val),
806 (ORri (SETHIi (HI22 imm:$val)), (LO10 imm:$val))>;
808 // Global addresses, constant pool entries
809 def : Pat<(V8hi tglobaladdr:$in), (SETHIi tglobaladdr:$in)>;
810 def : Pat<(V8lo tglobaladdr:$in), (ORri G0, tglobaladdr:$in)>;
811 def : Pat<(V8hi tconstpool:$in), (SETHIi tconstpool:$in)>;
812 def : Pat<(V8lo tconstpool:$in), (ORri G0, tconstpool:$in)>;
814 // Add reg, lo. This is used when taking the addr of a global/constpool entry.
815 def : Pat<(add IntRegs:$r, (V8lo tglobaladdr:$in)),
816 (ADDri IntRegs:$r, tglobaladdr:$in)>;
817 def : Pat<(add IntRegs:$r, (V8lo tconstpool:$in)),
818 (ADDri IntRegs:$r, tconstpool:$in)>;
822 def : Pat<(call tglobaladdr:$dst),
823 (CALL tglobaladdr:$dst)>;
824 def : Pat<(call externalsym:$dst),
825 (CALL externalsym:$dst)>;
827 def : Pat<(ret), (RETL)>;
829 // Map integer extload's to zextloads.
830 def : Pat<(i32 (extload ADDRrr:$src, i1)), (LDUBrr ADDRrr:$src)>;
831 def : Pat<(i32 (extload ADDRri:$src, i1)), (LDUBri ADDRri:$src)>;
832 def : Pat<(i32 (extload ADDRrr:$src, i8)), (LDUBrr ADDRrr:$src)>;
833 def : Pat<(i32 (extload ADDRri:$src, i8)), (LDUBri ADDRri:$src)>;
834 def : Pat<(i32 (extload ADDRrr:$src, i16)), (LDUHrr ADDRrr:$src)>;
835 def : Pat<(i32 (extload ADDRri:$src, i16)), (LDUHri ADDRri:$src)>;
837 // zextload bool -> zextload byte
838 def : Pat<(i32 (zextload ADDRrr:$src, i1)), (LDUBrr ADDRrr:$src)>;
839 def : Pat<(i32 (zextload ADDRri:$src, i1)), (LDUBri ADDRri:$src)>;
841 // truncstore bool -> truncstore byte.
842 def : Pat<(truncstore IntRegs:$src, ADDRrr:$addr, i1),
843 (STBrr ADDRrr:$addr, IntRegs:$src)>;
844 def : Pat<(truncstore IntRegs:$src, ADDRri:$addr, i1),
845 (STBri ADDRri:$addr, IntRegs:$src)>;