1 //===-- InstSelectSimple.cpp - A simple instruction selector for SparcV8 --===//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by the LLVM research group and is distributed under
6 // the University of Illinois Open Source License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file defines a simple peephole instruction selector for the V8 target
12 //===----------------------------------------------------------------------===//
15 #include "SparcV8InstrInfo.h"
16 #include "Support/Debug.h"
17 #include "llvm/Instructions.h"
18 #include "llvm/Pass.h"
19 #include "llvm/Constants.h"
20 #include "llvm/CodeGen/IntrinsicLowering.h"
21 #include "llvm/CodeGen/MachineInstrBuilder.h"
22 #include "llvm/CodeGen/MachineFrameInfo.h"
23 #include "llvm/CodeGen/MachineConstantPool.h"
24 #include "llvm/CodeGen/MachineFunction.h"
25 #include "llvm/CodeGen/SSARegMap.h"
26 #include "llvm/Target/TargetMachine.h"
27 #include "llvm/Support/GetElementPtrTypeIterator.h"
28 #include "llvm/Support/InstVisitor.h"
29 #include "llvm/Support/CFG.h"
34 struct V8ISel : public FunctionPass, public InstVisitor<V8ISel> {
36 MachineFunction *F; // The function we are compiling into
37 MachineBasicBlock *BB; // The current MBB we are compiling
39 std::map<Value*, unsigned> RegMap; // Mapping between Val's and SSA Regs
41 // MBBMap - Mapping between LLVM BB -> Machine BB
42 std::map<const BasicBlock*, MachineBasicBlock*> MBBMap;
44 V8ISel(TargetMachine &tm) : TM(tm), F(0), BB(0) {}
46 /// runOnFunction - Top level implementation of instruction selection for
47 /// the entire function.
49 bool runOnFunction(Function &Fn);
51 virtual const char *getPassName() const {
52 return "SparcV8 Simple Instruction Selection";
55 /// emitGEPOperation - Common code shared between visitGetElementPtrInst and
56 /// constant expression GEP support.
58 void emitGEPOperation(MachineBasicBlock *BB, MachineBasicBlock::iterator IP,
59 Value *Src, User::op_iterator IdxBegin,
60 User::op_iterator IdxEnd, unsigned TargetReg);
62 /// emitCastOperation - Common code shared between visitCastInst and
63 /// constant expression cast support.
65 void emitCastOperation(MachineBasicBlock *BB,MachineBasicBlock::iterator IP,
66 Value *Src, const Type *DestTy, unsigned TargetReg);
68 /// visitBasicBlock - This method is called when we are visiting a new basic
69 /// block. This simply creates a new MachineBasicBlock to emit code into
70 /// and adds it to the current MachineFunction. Subsequent visit* for
71 /// instructions will be invoked for all instructions in the basic block.
73 void visitBasicBlock(BasicBlock &LLVM_BB) {
74 BB = MBBMap[&LLVM_BB];
77 void visitBinaryOperator(Instruction &I);
78 void visitShiftInst (ShiftInst &SI) { visitBinaryOperator (SI); }
79 void visitSetCondInst(SetCondInst &I);
80 void visitCallInst(CallInst &I);
81 void visitReturnInst(ReturnInst &I);
82 void visitBranchInst(BranchInst &I);
83 void visitCastInst(CastInst &I);
84 void visitLoadInst(LoadInst &I);
85 void visitStoreInst(StoreInst &I);
86 void visitPHINode(PHINode &I) {} // PHI nodes handled by second pass
87 void visitGetElementPtrInst(GetElementPtrInst &I);
88 void visitAllocaInst(AllocaInst &I);
90 void visitInstruction(Instruction &I) {
91 std::cerr << "Unhandled instruction: " << I;
95 /// LowerUnknownIntrinsicFunctionCalls - This performs a prepass over the
96 /// function, lowering any calls to unknown intrinsic functions into the
97 /// equivalent LLVM code.
98 void LowerUnknownIntrinsicFunctionCalls(Function &F);
99 void visitIntrinsicCall(Intrinsic::ID ID, CallInst &CI);
101 void LoadArgumentsToVirtualRegs(Function *F);
103 /// SelectPHINodes - Insert machine code to generate phis. This is tricky
104 /// because we have to generate our sources into the source basic blocks,
105 /// not the current one.
107 void SelectPHINodes();
109 /// copyConstantToRegister - Output the instructions required to put the
110 /// specified constant into the specified register.
112 void copyConstantToRegister(MachineBasicBlock *MBB,
113 MachineBasicBlock::iterator IP,
114 Constant *C, unsigned R);
116 /// makeAnotherReg - This method returns the next register number we haven't
119 /// Long values are handled somewhat specially. They are always allocated
120 /// as pairs of 32 bit integer values. The register number returned is the
121 /// lower 32 bits of the long value, and the regNum+1 is the upper 32 bits
122 /// of the long value.
124 unsigned makeAnotherReg(const Type *Ty) {
125 assert(dynamic_cast<const SparcV8RegisterInfo*>(TM.getRegisterInfo()) &&
126 "Current target doesn't have SparcV8 reg info??");
127 const SparcV8RegisterInfo *MRI =
128 static_cast<const SparcV8RegisterInfo*>(TM.getRegisterInfo());
129 if (Ty == Type::LongTy || Ty == Type::ULongTy) {
130 const TargetRegisterClass *RC = MRI->getRegClassForType(Type::IntTy);
131 // Create the lower part
132 F->getSSARegMap()->createVirtualRegister(RC);
133 // Create the upper part.
134 return F->getSSARegMap()->createVirtualRegister(RC)-1;
137 // Add the mapping of regnumber => reg class to MachineFunction
138 const TargetRegisterClass *RC = MRI->getRegClassForType(Ty);
139 return F->getSSARegMap()->createVirtualRegister(RC);
142 unsigned getReg(Value &V) { return getReg (&V); } // allow refs.
143 unsigned getReg(Value *V) {
144 // Just append to the end of the current bb.
145 MachineBasicBlock::iterator It = BB->end();
146 return getReg(V, BB, It);
148 unsigned getReg(Value *V, MachineBasicBlock *MBB,
149 MachineBasicBlock::iterator IPt) {
150 unsigned &Reg = RegMap[V];
152 Reg = makeAnotherReg(V->getType());
155 // If this operand is a constant, emit the code to copy the constant into
156 // the register here...
158 if (Constant *C = dyn_cast<Constant>(V)) {
159 copyConstantToRegister(MBB, IPt, C, Reg);
160 RegMap.erase(V); // Assign a new name to this constant if ref'd again
161 } else if (GlobalValue *GV = dyn_cast<GlobalValue>(V)) {
162 // Move the address of the global into the register
163 unsigned TmpReg = makeAnotherReg(V->getType());
164 BuildMI (*MBB, IPt, V8::SETHIi, 1, TmpReg).addGlobalAddress (GV);
165 BuildMI (*MBB, IPt, V8::ORri, 2, Reg).addReg (TmpReg)
166 .addGlobalAddress (GV);
167 RegMap.erase(V); // Assign a new name to this address if ref'd again
176 FunctionPass *llvm::createSparcV8SimpleInstructionSelector(TargetMachine &TM) {
177 return new V8ISel(TM);
181 cByte, cShort, cInt, cLong, cFloat, cDouble
184 static TypeClass getClass (const Type *T) {
185 switch (T->getTypeID()) {
186 case Type::UByteTyID: case Type::SByteTyID: return cByte;
187 case Type::UShortTyID: case Type::ShortTyID: return cShort;
188 case Type::PointerTyID:
189 case Type::UIntTyID: case Type::IntTyID: return cInt;
190 case Type::ULongTyID: case Type::LongTyID: return cLong;
191 case Type::FloatTyID: return cFloat;
192 case Type::DoubleTyID: return cDouble;
194 assert (0 && "Type of unknown class passed to getClass?");
198 static TypeClass getClassB(const Type *T) {
199 if (T == Type::BoolTy) return cByte;
205 /// copyConstantToRegister - Output the instructions required to put the
206 /// specified constant into the specified register.
208 void V8ISel::copyConstantToRegister(MachineBasicBlock *MBB,
209 MachineBasicBlock::iterator IP,
210 Constant *C, unsigned R) {
211 if (ConstantExpr *CE = dyn_cast<ConstantExpr>(C)) {
212 switch (CE->getOpcode()) {
213 case Instruction::GetElementPtr:
214 emitGEPOperation(MBB, IP, CE->getOperand(0),
215 CE->op_begin()+1, CE->op_end(), R);
217 case Instruction::Cast:
218 emitCastOperation(MBB, IP, CE->getOperand(0), CE->getType(), R);
221 std::cerr << "Copying this constant expr not yet handled: " << *CE;
226 if (C->getType()->isIntegral ()) {
228 unsigned Class = getClassB (C->getType ());
229 if (Class == cLong) {
230 unsigned TmpReg = makeAnotherReg (Type::IntTy);
231 unsigned TmpReg2 = makeAnotherReg (Type::IntTy);
232 // Copy the value into the register pair.
233 // R = top(more-significant) half, R+1 = bottom(less-significant) half
234 uint64_t Val = cast<ConstantInt>(C)->getRawValue();
235 unsigned bottomHalf = Val & 0xffffffffU;
236 unsigned topHalf = Val >> 32;
237 unsigned HH = topHalf >> 10;
238 unsigned HM = topHalf & 0x03ff;
239 unsigned LM = bottomHalf >> 10;
240 unsigned LO = bottomHalf & 0x03ff;
241 BuildMI (*MBB, IP, V8::SETHIi, 1, TmpReg).addZImm(HH);
242 BuildMI (*MBB, IP, V8::ORri, 2, R).addReg (TmpReg)
244 BuildMI (*MBB, IP, V8::SETHIi, 1, TmpReg2).addZImm(LM);
245 BuildMI (*MBB, IP, V8::ORri, 2, R+1).addReg (TmpReg2)
250 assert(Class <= cInt && "Type not handled yet!");
252 if (C->getType() == Type::BoolTy) {
253 Val = (C == ConstantBool::True);
255 ConstantInt *CI = cast<ConstantInt> (C);
256 Val = CI->getRawValue ();
259 case cByte: Val = (int8_t) Val; break;
260 case cShort: Val = (int16_t) Val; break;
261 case cInt: Val = (int32_t) Val; break;
263 std::cerr << "Offending constant: " << *C << "\n";
264 assert (0 && "Can't copy this kind of constant into register yet");
268 BuildMI (*MBB, IP, V8::ORrr, 2, R).addReg (V8::G0).addReg(V8::G0);
269 } else if (((int64_t)Val >= -4096) && ((int64_t)Val <= 4095)) {
270 BuildMI (*MBB, IP, V8::ORri, 2, R).addReg (V8::G0).addSImm(Val);
272 unsigned TmpReg = makeAnotherReg (C->getType ());
273 BuildMI (*MBB, IP, V8::SETHIi, 1, TmpReg)
274 .addSImm (((uint32_t) Val) >> 10);
275 BuildMI (*MBB, IP, V8::ORri, 2, R).addReg (TmpReg)
276 .addSImm (((uint32_t) Val) & 0x03ff);
279 } else if (ConstantFP *CFP = dyn_cast<ConstantFP>(C)) {
280 // We need to spill the constant to memory...
281 MachineConstantPool *CP = F->getConstantPool();
282 unsigned CPI = CP->getConstantPoolIndex(CFP);
283 const Type *Ty = CFP->getType();
285 assert(Ty == Type::FloatTy || Ty == Type::DoubleTy && "Unknown FP type!");
286 unsigned LoadOpcode = Ty == Type::FloatTy ? V8::LDFri : V8::LDDFri;
287 BuildMI (*MBB, IP, LoadOpcode, 2, R).addConstantPoolIndex (CPI).addSImm (0);
288 } else if (isa<ConstantPointerNull>(C)) {
289 // Copy zero (null pointer) to the register.
290 BuildMI (*MBB, IP, V8::ORri, 2, R).addReg (V8::G0).addSImm (0);
291 } else if (ConstantPointerRef *CPR = dyn_cast<ConstantPointerRef>(C)) {
292 // Copy it with a SETHI/OR pair; the JIT + asmwriter should recognize
293 // that SETHI %reg,global == SETHI %reg,%hi(global) and
294 // OR %reg,global,%reg == OR %reg,%lo(global),%reg.
295 unsigned TmpReg = makeAnotherReg (C->getType ());
296 BuildMI (*MBB, IP, V8::SETHIi, 1, TmpReg).addGlobalAddress (CPR->getValue());
297 BuildMI (*MBB, IP, V8::ORri, 2, R).addReg (TmpReg)
298 .addGlobalAddress (CPR->getValue ());
300 std::cerr << "Offending constant: " << *C << "\n";
301 assert (0 && "Can't copy this kind of constant into register yet");
305 void V8ISel::LoadArgumentsToVirtualRegs (Function *LF) {
307 static const unsigned IncomingArgRegs[] = { V8::I0, V8::I1, V8::I2,
308 V8::I3, V8::I4, V8::I5 };
309 assert (LF->asize () < 7
310 && "Can't handle loading excess call args off the stack yet");
312 // Add IMPLICIT_DEFs of input regs.
314 for (Function::aiterator I = LF->abegin(), E = LF->aend(); I != E; ++I) {
315 unsigned Reg = getReg(*I);
316 switch (getClassB(I->getType())) {
321 BuildMI(BB, V8::IMPLICIT_DEF, 0, IncomingArgRegs[ArgOffset]);
324 // FIXME: handle cDouble, cLong
325 assert (0 && "64-bit (double, long, etc.) function args not handled");
332 for (Function::aiterator I = LF->abegin(), E = LF->aend(); I != E; ++I) {
333 unsigned Reg = getReg(*I);
334 switch (getClassB(I->getType())) {
338 BuildMI(BB, V8::ORrr, 2, Reg).addReg (V8::G0)
339 .addReg (IncomingArgRegs[ArgOffset]);
342 // Single-fp args are passed in integer registers; go through
343 // memory to get them into FP registers. (Bleh!)
344 unsigned FltAlign = TM.getTargetData().getFloatAlignment();
345 int FI = F->getFrameInfo()->CreateStackObject(4, FltAlign);
346 BuildMI (BB, V8::ST, 3).addFrameIndex (FI).addSImm (0)
347 .addReg (IncomingArgRegs[ArgOffset]);
348 BuildMI (BB, V8::LDFri, 2, Reg).addFrameIndex (FI).addSImm (0);
352 // FIXME: handle cDouble, cLong
353 assert (0 && "64-bit (double, long, etc.) function args not handled");
361 void V8ISel::SelectPHINodes() {
362 const TargetInstrInfo &TII = *TM.getInstrInfo();
363 const Function &LF = *F->getFunction(); // The LLVM function...
364 for (Function::const_iterator I = LF.begin(), E = LF.end(); I != E; ++I) {
365 const BasicBlock *BB = I;
366 MachineBasicBlock &MBB = *MBBMap[I];
368 // Loop over all of the PHI nodes in the LLVM basic block...
369 MachineBasicBlock::iterator PHIInsertPoint = MBB.begin();
370 for (BasicBlock::const_iterator I = BB->begin();
371 PHINode *PN = const_cast<PHINode*>(dyn_cast<PHINode>(I)); ++I) {
373 // Create a new machine instr PHI node, and insert it.
374 unsigned PHIReg = getReg(*PN);
375 MachineInstr *PhiMI = BuildMI(MBB, PHIInsertPoint,
376 V8::PHI, PN->getNumOperands(), PHIReg);
378 MachineInstr *LongPhiMI = 0;
379 if (PN->getType() == Type::LongTy || PN->getType() == Type::ULongTy)
380 LongPhiMI = BuildMI(MBB, PHIInsertPoint,
381 V8::PHI, PN->getNumOperands(), PHIReg+1);
383 // PHIValues - Map of blocks to incoming virtual registers. We use this
384 // so that we only initialize one incoming value for a particular block,
385 // even if the block has multiple entries in the PHI node.
387 std::map<MachineBasicBlock*, unsigned> PHIValues;
389 for (unsigned i = 0, e = PN->getNumIncomingValues(); i != e; ++i) {
390 MachineBasicBlock *PredMBB = 0;
391 for (MachineBasicBlock::pred_iterator PI = MBB.pred_begin (),
392 PE = MBB.pred_end (); PI != PE; ++PI)
393 if (PN->getIncomingBlock(i) == (*PI)->getBasicBlock()) {
397 assert (PredMBB && "Couldn't find incoming machine-cfg edge for phi");
400 std::map<MachineBasicBlock*, unsigned>::iterator EntryIt =
401 PHIValues.lower_bound(PredMBB);
403 if (EntryIt != PHIValues.end() && EntryIt->first == PredMBB) {
404 // We already inserted an initialization of the register for this
405 // predecessor. Recycle it.
406 ValReg = EntryIt->second;
409 // Get the incoming value into a virtual register.
411 Value *Val = PN->getIncomingValue(i);
413 // If this is a constant or GlobalValue, we may have to insert code
414 // into the basic block to compute it into a virtual register.
415 if ((isa<Constant>(Val) && !isa<ConstantExpr>(Val)) ||
416 isa<GlobalValue>(Val)) {
417 // Simple constants get emitted at the end of the basic block,
418 // before any terminator instructions. We "know" that the code to
419 // move a constant into a register will never clobber any flags.
420 ValReg = getReg(Val, PredMBB, PredMBB->getFirstTerminator());
422 // Because we don't want to clobber any values which might be in
423 // physical registers with the computation of this constant (which
424 // might be arbitrarily complex if it is a constant expression),
425 // just insert the computation at the top of the basic block.
426 MachineBasicBlock::iterator PI = PredMBB->begin();
428 // Skip over any PHI nodes though!
429 while (PI != PredMBB->end() && PI->getOpcode() == V8::PHI)
432 ValReg = getReg(Val, PredMBB, PI);
435 // Remember that we inserted a value for this PHI for this predecessor
436 PHIValues.insert(EntryIt, std::make_pair(PredMBB, ValReg));
439 PhiMI->addRegOperand(ValReg);
440 PhiMI->addMachineBasicBlockOperand(PredMBB);
442 LongPhiMI->addRegOperand(ValReg+1);
443 LongPhiMI->addMachineBasicBlockOperand(PredMBB);
447 // Now that we emitted all of the incoming values for the PHI node, make
448 // sure to reposition the InsertPoint after the PHI that we just added.
449 // This is needed because we might have inserted a constant into this
450 // block, right after the PHI's which is before the old insert point!
451 PHIInsertPoint = LongPhiMI ? LongPhiMI : PhiMI;
457 bool V8ISel::runOnFunction(Function &Fn) {
458 // First pass over the function, lower any unknown intrinsic functions
459 // with the IntrinsicLowering class.
460 LowerUnknownIntrinsicFunctionCalls(Fn);
462 F = &MachineFunction::construct(&Fn, TM);
464 // Create all of the machine basic blocks for the function...
465 for (Function::iterator I = Fn.begin(), E = Fn.end(); I != E; ++I)
466 F->getBasicBlockList().push_back(MBBMap[I] = new MachineBasicBlock(I));
470 // Set up a frame object for the return address. This is used by the
471 // llvm.returnaddress & llvm.frameaddress intrinisics.
472 //ReturnAddressIndex = F->getFrameInfo()->CreateFixedObject(4, -4);
474 // Copy incoming arguments off of the stack and out of fixed registers.
475 LoadArgumentsToVirtualRegs(&Fn);
477 // Instruction select everything except PHI nodes
480 // Select the PHI nodes
486 // We always build a machine code representation for the function
490 void V8ISel::visitCastInst(CastInst &I) {
491 Value *Op = I.getOperand(0);
492 unsigned DestReg = getReg(I);
493 MachineBasicBlock::iterator MI = BB->end();
494 emitCastOperation(BB, MI, Op, I.getType(), DestReg);
497 /// emitCastOperation - Common code shared between visitCastInst and constant
498 /// expression cast support.
500 void V8ISel::emitCastOperation(MachineBasicBlock *BB,
501 MachineBasicBlock::iterator IP,
502 Value *Src, const Type *DestTy,
504 const Type *SrcTy = Src->getType();
505 unsigned SrcClass = getClassB(SrcTy);
506 unsigned DestClass = getClassB(DestTy);
507 unsigned SrcReg = getReg(Src, BB, IP);
509 const Type *oldTy = SrcTy;
510 const Type *newTy = DestTy;
511 unsigned oldTyClass = SrcClass;
512 unsigned newTyClass = DestClass;
514 if (oldTyClass < cLong && newTyClass < cLong) {
515 if (oldTyClass >= newTyClass) {
516 // Emit a reg->reg copy to do a equal-size or narrowing cast,
517 // and do sign/zero extension (necessary if we change signedness).
518 unsigned TmpReg1 = makeAnotherReg (newTy);
519 unsigned TmpReg2 = makeAnotherReg (newTy);
520 BuildMI (*BB, IP, V8::ORrr, 2, TmpReg1).addReg (V8::G0).addReg (SrcReg);
521 unsigned shiftWidth = 32 - (8 * TM.getTargetData ().getTypeSize (newTy));
522 BuildMI (*BB, IP, V8::SLLri, 2, TmpReg2).addZImm (shiftWidth).addReg(TmpReg1);
523 if (newTy->isSigned ()) { // sign-extend with SRA
524 BuildMI(*BB, IP, V8::SRAri, 2, DestReg).addZImm (shiftWidth).addReg(TmpReg2);
525 } else { // zero-extend with SRL
526 BuildMI(*BB, IP, V8::SRLri, 2, DestReg).addZImm (shiftWidth).addReg(TmpReg2);
529 unsigned TmpReg1 = makeAnotherReg (oldTy);
530 unsigned TmpReg2 = makeAnotherReg (newTy);
531 unsigned TmpReg3 = makeAnotherReg (newTy);
532 // Widening integer cast. Make sure it's fully sign/zero-extended
533 // wrt the input type, then make sure it's fully sign/zero-extended wrt
534 // the output type. Kind of stupid, but simple...
535 unsigned shiftWidth = 32 - (8 * TM.getTargetData ().getTypeSize (oldTy));
536 BuildMI (*BB, IP, V8::SLLri, 2, TmpReg1).addZImm (shiftWidth).addReg(SrcReg);
537 if (oldTy->isSigned ()) { // sign-extend with SRA
538 BuildMI(*BB, IP, V8::SRAri, 2, TmpReg2).addZImm (shiftWidth).addReg(TmpReg1);
539 } else { // zero-extend with SRL
540 BuildMI(*BB, IP, V8::SRLri, 2, TmpReg2).addZImm (shiftWidth).addReg(TmpReg1);
542 shiftWidth = 32 - (8 * TM.getTargetData ().getTypeSize (newTy));
543 BuildMI (*BB, IP, V8::SLLri, 2, TmpReg3).addZImm (shiftWidth).addReg(TmpReg2);
544 if (newTy->isSigned ()) { // sign-extend with SRA
545 BuildMI(*BB, IP, V8::SRAri, 2, DestReg).addZImm (shiftWidth).addReg(TmpReg3);
546 } else { // zero-extend with SRL
547 BuildMI(*BB, IP, V8::SRLri, 2, DestReg).addZImm (shiftWidth).addReg(TmpReg3);
551 if (newTyClass == cFloat) {
552 assert (oldTyClass != cLong && "cast long to float not implemented yet");
553 switch (oldTyClass) {
555 BuildMI (*BB, IP, V8::FMOVS, 1, DestReg).addReg (SrcReg);
558 BuildMI (*BB, IP, V8::FDTOS, 1, DestReg).addReg (SrcReg);
561 unsigned FltAlign = TM.getTargetData().getFloatAlignment();
562 // cast int to float. Store it to a stack slot and then load
563 // it using ldf into a floating point register. then do fitos.
564 unsigned TmpReg = makeAnotherReg (newTy);
565 int FI = F->getFrameInfo()->CreateStackObject(4, FltAlign);
566 BuildMI (*BB, IP, V8::ST, 3).addFrameIndex (FI).addSImm (0)
568 BuildMI (*BB, IP, V8::LDFri, 2, TmpReg).addFrameIndex (FI).addSImm (0);
569 BuildMI (*BB, IP, V8::FITOS, 1, DestReg).addReg(TmpReg);
573 } else if (newTyClass == cDouble) {
574 assert (oldTyClass != cLong && "cast long to double not implemented yet");
575 switch (oldTyClass) {
577 BuildMI (*BB, IP, V8::FSTOD, 1, DestReg).addReg (SrcReg);
580 // go through memory, for now
581 unsigned DoubleAlignment = TM.getTargetData().getDoubleAlignment();
582 int FI = F->getFrameInfo()->CreateStackObject(8, DoubleAlignment);
583 BuildMI (*BB, IP, V8::STDFri, 3).addFrameIndex (FI).addSImm (0)
585 BuildMI (*BB, IP, V8::LDDFri, 2, DestReg).addFrameIndex (FI)
590 unsigned DoubleAlignment = TM.getTargetData().getDoubleAlignment();
591 unsigned TmpReg = makeAnotherReg (newTy);
592 int FI = F->getFrameInfo()->CreateStackObject(8, DoubleAlignment);
593 BuildMI (*BB, IP, V8::ST, 3).addFrameIndex (FI).addSImm (0)
595 BuildMI (*BB, IP, V8::LDDFri, 2, TmpReg).addFrameIndex (FI).addSImm (0);
596 BuildMI (*BB, IP, V8::FITOD, 1, DestReg).addReg(TmpReg);
600 } else if (newTyClass == cLong) {
601 if (oldTyClass == cLong) {
603 BuildMI (*BB, IP, V8::ORrr, 2, DestReg).addReg (V8::G0).addReg (SrcReg);
604 BuildMI (*BB, IP, V8::ORrr, 2, DestReg+1).addReg (V8::G0)
607 std::cerr << "Cast still unsupported: SrcTy = "
608 << *SrcTy << ", DestTy = " << *DestTy << "\n";
612 std::cerr << "Cast still unsupported: SrcTy = "
613 << *SrcTy << ", DestTy = " << *DestTy << "\n";
619 void V8ISel::visitLoadInst(LoadInst &I) {
620 unsigned DestReg = getReg (I);
621 unsigned PtrReg = getReg (I.getOperand (0));
622 switch (getClassB (I.getType ())) {
624 if (I.getType ()->isSigned ())
625 BuildMI (BB, V8::LDSB, 2, DestReg).addReg (PtrReg).addSImm(0);
627 BuildMI (BB, V8::LDUB, 2, DestReg).addReg (PtrReg).addSImm(0);
630 if (I.getType ()->isSigned ())
631 BuildMI (BB, V8::LDSH, 2, DestReg).addReg (PtrReg).addSImm(0);
633 BuildMI (BB, V8::LDUH, 2, DestReg).addReg (PtrReg).addSImm(0);
636 BuildMI (BB, V8::LD, 2, DestReg).addReg (PtrReg).addSImm(0);
639 BuildMI (BB, V8::LD, 2, DestReg).addReg (PtrReg).addSImm(0);
640 BuildMI (BB, V8::LD, 2, DestReg+1).addReg (PtrReg).addSImm(4);
643 BuildMI (BB, V8::LDFri, 2, DestReg).addReg (PtrReg).addSImm(0);
646 BuildMI (BB, V8::LDDFri, 2, DestReg).addReg (PtrReg).addSImm(0);
649 std::cerr << "Load instruction not handled: " << I;
655 void V8ISel::visitStoreInst(StoreInst &I) {
656 Value *SrcVal = I.getOperand (0);
657 unsigned SrcReg = getReg (SrcVal);
658 unsigned PtrReg = getReg (I.getOperand (1));
659 switch (getClassB (SrcVal->getType ())) {
661 BuildMI (BB, V8::STB, 3).addReg (PtrReg).addSImm (0).addReg (SrcReg);
664 BuildMI (BB, V8::STH, 3).addReg (PtrReg).addSImm (0).addReg (SrcReg);
667 BuildMI (BB, V8::ST, 3).addReg (PtrReg).addSImm (0).addReg (SrcReg);
670 BuildMI (BB, V8::ST, 3).addReg (PtrReg).addSImm (0).addReg (SrcReg);
671 BuildMI (BB, V8::ST, 3).addReg (PtrReg).addSImm (4).addReg (SrcReg+1);
674 BuildMI (BB, V8::STFri, 3).addReg (PtrReg).addSImm (0).addReg (SrcReg);
677 BuildMI (BB, V8::STDFri, 3).addReg (PtrReg).addSImm (0).addReg (SrcReg);
680 std::cerr << "Store instruction not handled: " << I;
686 void V8ISel::visitCallInst(CallInst &I) {
687 MachineInstr *TheCall;
688 // Is it an intrinsic function call?
689 if (Function *F = I.getCalledFunction()) {
690 if (Intrinsic::ID ID = (Intrinsic::ID)F->getIntrinsicID()) {
691 visitIntrinsicCall(ID, I); // Special intrinsics are not handled here
697 assert (I.getNumOperands () < 8
698 && "Can't handle pushing excess call args on the stack yet");
699 static const unsigned OutgoingArgRegs[] = { V8::O0, V8::O1, V8::O2, V8::O3,
701 for (unsigned i = 1; i < 7; ++i)
702 if (i < I.getNumOperands ()) {
703 unsigned ArgReg = getReg (I.getOperand (i));
704 if (getClassB (I.getOperand (i)->getType ()) < cLong) {
705 // Schlep it over into the incoming arg register
706 BuildMI (BB, V8::ORrr, 2, OutgoingArgRegs[i - 1]).addReg (V8::G0)
708 } else if (getClassB (I.getOperand (i)->getType ()) == cFloat) {
709 // Single-fp args are passed in integer registers; go through
710 // memory to get them out of FP registers. (Bleh!)
711 unsigned FltAlign = TM.getTargetData().getFloatAlignment();
712 int FI = F->getFrameInfo()->CreateStackObject(4, FltAlign);
713 BuildMI (BB, V8::STFri, 3).addFrameIndex (FI).addSImm (0)
715 BuildMI (BB, V8::LD, 2, OutgoingArgRegs[i - 1]).addFrameIndex (FI)
718 assert (0 && "64-bit (double, long, etc.) 'call' opnds not handled");
722 // Emit call instruction
723 if (Function *F = I.getCalledFunction ()) {
724 BuildMI (BB, V8::CALL, 1).addGlobalAddress (F, true);
725 } else { // Emit an indirect call...
726 unsigned Reg = getReg (I.getCalledValue ());
727 BuildMI (BB, V8::JMPLrr, 3, V8::O7).addReg (Reg).addReg (V8::G0);
730 // Deal w/ return value: schlep it over into the destination register
731 if (I.getType () == Type::VoidTy)
733 unsigned DestReg = getReg (I);
734 switch (getClass (I.getType ())) {
738 BuildMI (BB, V8::ORrr, 2, DestReg).addReg(V8::G0).addReg(V8::O0);
741 BuildMI (BB, V8::FMOVS, 2, DestReg).addReg(V8::F0);
744 std::cerr << "Return type of call instruction not handled: " << I;
749 void V8ISel::visitReturnInst(ReturnInst &I) {
750 if (I.getNumOperands () == 1) {
751 unsigned RetValReg = getReg (I.getOperand (0));
752 switch (getClass (I.getOperand (0)->getType ())) {
756 // Schlep it over into i0 (where it will become o0 after restore).
757 BuildMI (BB, V8::ORrr, 2, V8::I0).addReg(V8::G0).addReg(RetValReg);
760 BuildMI (BB, V8::FMOVS, 2, V8::F0).addReg(RetValReg);
763 unsigned DoubleAlignment = TM.getTargetData().getDoubleAlignment();
764 int FI = F->getFrameInfo()->CreateStackObject(8, DoubleAlignment);
765 BuildMI (BB, V8::STDFri, 3).addFrameIndex (FI).addSImm (0)
767 BuildMI (BB, V8::LDDFri, 2, V8::F0).addFrameIndex (FI).addSImm (0);
771 BuildMI (BB, V8::ORrr, 2, V8::I0).addReg(V8::G0).addReg(RetValReg);
772 BuildMI (BB, V8::ORrr, 2, V8::I1).addReg(V8::G0).addReg(RetValReg+1);
775 std::cerr << "Return instruction of this type not handled: " << I;
780 // Just emit a 'retl' instruction to return.
781 BuildMI(BB, V8::RETL, 0);
785 static inline BasicBlock *getBlockAfter(BasicBlock *BB) {
786 Function::iterator I = BB; ++I; // Get iterator to next block
787 return I != BB->getParent()->end() ? &*I : 0;
790 /// visitBranchInst - Handles conditional and unconditional branches.
792 void V8ISel::visitBranchInst(BranchInst &I) {
793 BasicBlock *takenSucc = I.getSuccessor (0);
794 MachineBasicBlock *takenSuccMBB = MBBMap[takenSucc];
795 BB->addSuccessor (takenSuccMBB);
796 if (I.isConditional()) { // conditional branch
797 BasicBlock *notTakenSucc = I.getSuccessor (1);
798 MachineBasicBlock *notTakenSuccMBB = MBBMap[notTakenSucc];
799 BB->addSuccessor (notTakenSuccMBB);
801 // CondReg=(<condition>);
802 // If (CondReg==0) goto notTakenSuccMBB;
803 unsigned CondReg = getReg (I.getCondition ());
804 BuildMI (BB, V8::CMPri, 2).addSImm (0).addReg (CondReg);
805 BuildMI (BB, V8::BE, 1).addMBB (notTakenSuccMBB);
807 // goto takenSuccMBB;
808 BuildMI (BB, V8::BA, 1).addMBB (takenSuccMBB);
811 /// emitGEPOperation - Common code shared between visitGetElementPtrInst and
812 /// constant expression GEP support.
814 void V8ISel::emitGEPOperation (MachineBasicBlock *MBB,
815 MachineBasicBlock::iterator IP,
816 Value *Src, User::op_iterator IdxBegin,
817 User::op_iterator IdxEnd, unsigned TargetReg) {
818 const TargetData &TD = TM.getTargetData ();
819 const Type *Ty = Src->getType ();
820 unsigned basePtrReg = getReg (Src, MBB, IP);
822 // GEPs have zero or more indices; we must perform a struct access
823 // or array access for each one.
824 for (GetElementPtrInst::op_iterator oi = IdxBegin, oe = IdxEnd; oi != oe;
827 unsigned nextBasePtrReg = makeAnotherReg (Type::UIntTy);
828 if (const StructType *StTy = dyn_cast<StructType> (Ty)) {
829 // It's a struct access. idx is the index into the structure,
830 // which names the field. Use the TargetData structure to
831 // pick out what the layout of the structure is in memory.
832 // Use the (constant) structure index's value to find the
833 // right byte offset from the StructLayout class's list of
834 // structure member offsets.
835 unsigned fieldIndex = cast<ConstantUInt> (idx)->getValue ();
836 unsigned memberOffset =
837 TD.getStructLayout (StTy)->MemberOffsets[fieldIndex];
838 // Emit an ADD to add memberOffset to the basePtr.
839 BuildMI (*MBB, IP, V8::ADDri, 2,
840 nextBasePtrReg).addReg (basePtrReg).addZImm (memberOffset);
841 // The next type is the member of the structure selected by the
843 Ty = StTy->getElementType (fieldIndex);
844 } else if (const SequentialType *SqTy = dyn_cast<SequentialType> (Ty)) {
845 // It's an array or pointer access: [ArraySize x ElementType].
846 // We want to add basePtrReg to (idxReg * sizeof ElementType). First, we
847 // must find the size of the pointed-to type (Not coincidentally, the next
848 // type is the type of the elements in the array).
849 Ty = SqTy->getElementType ();
850 unsigned elementSize = TD.getTypeSize (Ty);
851 unsigned idxReg = getReg (idx, MBB, IP);
852 unsigned OffsetReg = makeAnotherReg (Type::IntTy);
853 unsigned elementSizeReg = makeAnotherReg (Type::UIntTy);
854 copyConstantToRegister (MBB, IP,
855 ConstantUInt::get(Type::UIntTy, elementSize), elementSizeReg);
856 // Emit a SMUL to multiply the register holding the index by
857 // elementSize, putting the result in OffsetReg.
858 BuildMI (*MBB, IP, V8::SMULrr, 2,
859 OffsetReg).addReg (elementSizeReg).addReg (idxReg);
860 // Emit an ADD to add OffsetReg to the basePtr.
861 BuildMI (*MBB, IP, V8::ADDrr, 2,
862 nextBasePtrReg).addReg (basePtrReg).addReg (OffsetReg);
864 basePtrReg = nextBasePtrReg;
866 // After we have processed all the indices, the result is left in
867 // basePtrReg. Move it to the register where we were expected to
869 BuildMI (BB, V8::ORrr, 1, TargetReg).addReg (V8::G0).addReg (basePtrReg);
872 void V8ISel::visitGetElementPtrInst (GetElementPtrInst &I) {
873 unsigned outputReg = getReg (I);
874 emitGEPOperation (BB, BB->end (), I.getOperand (0),
875 I.op_begin ()+1, I.op_end (), outputReg);
879 void V8ISel::visitBinaryOperator (Instruction &I) {
880 unsigned DestReg = getReg (I);
881 unsigned Op0Reg = getReg (I.getOperand (0));
882 unsigned Op1Reg = getReg (I.getOperand (1));
884 unsigned Class = getClassB (I.getType());
885 unsigned OpCase = ~0;
888 switch (I.getOpcode ()) {
889 case Instruction::Add: OpCase = 0; break;
890 case Instruction::Sub: OpCase = 1; break;
891 case Instruction::Mul: OpCase = 2; break;
892 case Instruction::Div: OpCase = 3; break;
893 default: visitInstruction (I); return;
895 static unsigned Opcodes[] = { V8::FADDS, V8::FADDD,
896 V8::FSUBS, V8::FSUBD,
897 V8::FMULS, V8::FMULD,
898 V8::FDIVS, V8::FDIVD };
899 BuildMI (BB, Opcodes[2*OpCase + (Class - cFloat)], 2, DestReg)
900 .addReg (Op0Reg).addReg (Op1Reg);
904 unsigned ResultReg = DestReg;
906 ResultReg = makeAnotherReg (I.getType ());
908 // FIXME: support long, ulong, fp.
909 switch (I.getOpcode ()) {
910 case Instruction::Add: OpCase = 0; break;
911 case Instruction::Sub: OpCase = 1; break;
912 case Instruction::Mul: OpCase = 2; break;
913 case Instruction::And: OpCase = 3; break;
914 case Instruction::Or: OpCase = 4; break;
915 case Instruction::Xor: OpCase = 5; break;
916 case Instruction::Shl: OpCase = 6; break;
917 case Instruction::Shr: OpCase = 7+I.getType()->isSigned(); break;
919 case Instruction::Div:
920 case Instruction::Rem: {
921 unsigned Dest = ResultReg;
922 if (I.getOpcode() == Instruction::Rem)
923 Dest = makeAnotherReg(I.getType());
925 // FIXME: this is probably only right for 32 bit operands.
926 if (I.getType ()->isSigned()) {
927 unsigned Tmp = makeAnotherReg (I.getType ());
928 // Sign extend into the Y register
929 BuildMI (BB, V8::SRAri, 2, Tmp).addReg (Op0Reg).addZImm (31);
930 BuildMI (BB, V8::WRrr, 2, V8::Y).addReg (Tmp).addReg (V8::G0);
931 BuildMI (BB, V8::SDIVrr, 2, Dest).addReg (Op0Reg).addReg (Op1Reg);
933 // Zero extend into the Y register, ie, just set it to zero
934 BuildMI (BB, V8::WRrr, 2, V8::Y).addReg (V8::G0).addReg (V8::G0);
935 BuildMI (BB, V8::UDIVrr, 2, Dest).addReg (Op0Reg).addReg (Op1Reg);
938 if (I.getOpcode() == Instruction::Rem) {
939 unsigned Tmp = makeAnotherReg (I.getType ());
940 BuildMI (BB, V8::SMULrr, 2, Tmp).addReg(Dest).addReg(Op1Reg);
941 BuildMI (BB, V8::SUBrr, 2, ResultReg).addReg(Op0Reg).addReg(Tmp);
946 visitInstruction (I);
950 static const unsigned Opcodes[] = {
951 V8::ADDrr, V8::SUBrr, V8::SMULrr, V8::ANDrr, V8::ORrr, V8::XORrr,
952 V8::SLLrr, V8::SRLrr, V8::SRArr
955 BuildMI (BB, Opcodes[OpCase], 2, ResultReg).addReg (Op0Reg).addReg (Op1Reg);
958 switch (getClassB (I.getType ())) {
960 if (I.getType ()->isSigned ()) { // add byte
961 BuildMI (BB, V8::ANDri, 2, DestReg).addReg (ResultReg).addZImm (0xff);
962 } else { // add ubyte
963 unsigned TmpReg = makeAnotherReg (I.getType ());
964 BuildMI (BB, V8::SLLri, 2, TmpReg).addReg (ResultReg).addZImm (24);
965 BuildMI (BB, V8::SRAri, 2, DestReg).addReg (TmpReg).addZImm (24);
969 if (I.getType ()->isSigned ()) { // add short
970 unsigned TmpReg = makeAnotherReg (I.getType ());
971 BuildMI (BB, V8::SLLri, 2, TmpReg).addReg (ResultReg).addZImm (16);
972 BuildMI (BB, V8::SRAri, 2, DestReg).addReg (TmpReg).addZImm (16);
973 } else { // add ushort
974 unsigned TmpReg = makeAnotherReg (I.getType ());
975 BuildMI (BB, V8::SLLri, 2, TmpReg).addReg (ResultReg).addZImm (16);
976 BuildMI (BB, V8::SRLri, 2, DestReg).addReg (TmpReg).addZImm (16);
980 // Nothing to do here.
983 // Only support and, or, xor.
984 if (OpCase < 3 || OpCase > 5) {
985 visitInstruction (I);
988 // Do the other half of the value:
989 BuildMI (BB, Opcodes[OpCase], 2, ResultReg+1).addReg (Op0Reg+1)
993 visitInstruction (I);
997 void V8ISel::visitSetCondInst(SetCondInst &I) {
998 unsigned Op0Reg = getReg (I.getOperand (0));
999 unsigned Op1Reg = getReg (I.getOperand (1));
1000 unsigned DestReg = getReg (I);
1001 const Type *Ty = I.getOperand (0)->getType ();
1003 // Compare the two values.
1004 assert (getClass (Ty) != cLong && "can't setcc on longs yet");
1005 if (getClass (Ty) < cLong) {
1006 BuildMI(BB, V8::SUBCCrr, 2, V8::G0).addReg(Op0Reg).addReg(Op1Reg);
1007 } else if (getClass (Ty) == cFloat) {
1008 BuildMI(BB, V8::FCMPS, 2).addReg(Op0Reg).addReg(Op1Reg);
1009 } else if (getClass (Ty) == cDouble) {
1010 BuildMI(BB, V8::FCMPD, 2).addReg(Op0Reg).addReg(Op1Reg);
1014 switch (I.getOpcode()) {
1015 default: assert(0 && "Unknown setcc instruction!");
1016 case Instruction::SetEQ: BranchIdx = 0; break;
1017 case Instruction::SetNE: BranchIdx = 1; break;
1018 case Instruction::SetLT: BranchIdx = 2; break;
1019 case Instruction::SetGT: BranchIdx = 3; break;
1020 case Instruction::SetLE: BranchIdx = 4; break;
1021 case Instruction::SetGE: BranchIdx = 5; break;
1023 unsigned Column = 0;
1024 if (Ty->isSigned()) ++Column;
1025 if (Ty->isFloatingPoint()) ++Column;
1026 static unsigned OpcodeTab[3*6] = {
1028 // unsigned signed fp
1029 V8::BE, V8::BE, V8::FBE, // seteq = be be fbe
1030 V8::BNE, V8::BNE, V8::FBNE, // setne = bne bne fbne
1031 V8::BCS, V8::BL, V8::FBL, // setlt = bcs bl fbl
1032 V8::BGU, V8::BG, V8::FBG, // setgt = bgu bg fbg
1033 V8::BLEU, V8::BLE, V8::FBLE, // setle = bleu ble fble
1034 V8::BCC, V8::BGE, V8::FBGE // setge = bcc bge fbge
1036 unsigned Opcode = OpcodeTab[3*BranchIdx + Column];
1038 MachineBasicBlock *thisMBB = BB;
1039 const BasicBlock *LLVM_BB = BB->getBasicBlock ();
1042 // subcc %reg0, %reg1, %g0
1046 // FIXME: we wouldn't need copy0MBB (we could fold it into thisMBB)
1047 // if we could insert other, non-terminator instructions after the
1048 // bCC. But MBB->getFirstTerminator() can't understand this.
1049 MachineBasicBlock *copy1MBB = new MachineBasicBlock (LLVM_BB);
1050 F->getBasicBlockList ().push_back (copy1MBB);
1051 BuildMI (BB, Opcode, 1).addMBB (copy1MBB);
1052 MachineBasicBlock *copy0MBB = new MachineBasicBlock (LLVM_BB);
1053 F->getBasicBlockList ().push_back (copy0MBB);
1054 BuildMI (BB, V8::BA, 1).addMBB (copy0MBB);
1055 // Update machine-CFG edges
1056 BB->addSuccessor (copy1MBB);
1057 BB->addSuccessor (copy0MBB);
1060 // %FalseValue = or %G0, 0
1063 unsigned FalseValue = makeAnotherReg (I.getType ());
1064 BuildMI (BB, V8::ORri, 2, FalseValue).addReg (V8::G0).addZImm (0);
1065 MachineBasicBlock *sinkMBB = new MachineBasicBlock (LLVM_BB);
1066 F->getBasicBlockList ().push_back (sinkMBB);
1067 BuildMI (BB, V8::BA, 1).addMBB (sinkMBB);
1068 // Update machine-CFG edges
1069 BB->addSuccessor (sinkMBB);
1071 DEBUG (std::cerr << "thisMBB is at " << (void*)thisMBB << "\n");
1072 DEBUG (std::cerr << "copy1MBB is at " << (void*)copy1MBB << "\n");
1073 DEBUG (std::cerr << "copy0MBB is at " << (void*)copy0MBB << "\n");
1074 DEBUG (std::cerr << "sinkMBB is at " << (void*)sinkMBB << "\n");
1077 // %TrueValue = or %G0, 1
1080 unsigned TrueValue = makeAnotherReg (I.getType ());
1081 BuildMI (BB, V8::ORri, 2, TrueValue).addReg (V8::G0).addZImm (1);
1082 BuildMI (BB, V8::BA, 1).addMBB (sinkMBB);
1083 // Update machine-CFG edges
1084 BB->addSuccessor (sinkMBB);
1087 // %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, copy1MBB ]
1090 BuildMI (BB, V8::PHI, 4, DestReg).addReg (FalseValue)
1091 .addMBB (copy0MBB).addReg (TrueValue).addMBB (copy1MBB);
1094 void V8ISel::visitAllocaInst(AllocaInst &I) {
1095 // Find the data size of the alloca inst's getAllocatedType.
1096 const Type *Ty = I.getAllocatedType();
1097 unsigned TySize = TM.getTargetData().getTypeSize(Ty);
1099 unsigned ArraySizeReg = getReg (I.getArraySize ());
1100 unsigned TySizeReg = getReg (ConstantUInt::get (Type::UIntTy, TySize));
1101 unsigned TmpReg1 = makeAnotherReg (Type::UIntTy);
1102 unsigned TmpReg2 = makeAnotherReg (Type::UIntTy);
1103 unsigned StackAdjReg = makeAnotherReg (Type::UIntTy);
1105 // StackAdjReg = (ArraySize * TySize) rounded up to nearest doubleword boundary
1106 BuildMI (BB, V8::UMULrr, 2, TmpReg1).addReg (ArraySizeReg).addReg (TySizeReg);
1108 // Round up TmpReg1 to nearest doubleword boundary:
1109 BuildMI (BB, V8::ADDri, 2, TmpReg2).addReg (TmpReg1).addSImm (7);
1110 BuildMI (BB, V8::ANDri, 2, StackAdjReg).addReg (TmpReg2).addSImm (-8);
1112 // Subtract size from stack pointer, thereby allocating some space.
1113 BuildMI (BB, V8::SUBrr, 2, V8::SP).addReg (V8::SP).addReg (StackAdjReg);
1115 // Put a pointer to the space into the result register, by copying
1116 // the stack pointer.
1117 BuildMI (BB, V8::ADDri, 2, getReg(I)).addReg (V8::SP).addSImm (96);
1119 // Inform the Frame Information that we have just allocated a variable-sized
1121 F->getFrameInfo()->CreateVariableSizedObject();
1124 /// LowerUnknownIntrinsicFunctionCalls - This performs a prepass over the
1125 /// function, lowering any calls to unknown intrinsic functions into the
1126 /// equivalent LLVM code.
1127 void V8ISel::LowerUnknownIntrinsicFunctionCalls(Function &F) {
1128 for (Function::iterator BB = F.begin(), E = F.end(); BB != E; ++BB)
1129 for (BasicBlock::iterator I = BB->begin(), E = BB->end(); I != E; )
1130 if (CallInst *CI = dyn_cast<CallInst>(I++))
1131 if (Function *F = CI->getCalledFunction())
1132 switch (F->getIntrinsicID()) {
1133 case Intrinsic::not_intrinsic: break;
1135 // All other intrinsic calls we must lower.
1136 Instruction *Before = CI->getPrev();
1137 TM.getIntrinsicLowering().LowerIntrinsicCall(CI);
1138 if (Before) { // Move iterator to instruction after call
1147 void V8ISel::visitIntrinsicCall(Intrinsic::ID ID, CallInst &CI) {
1148 unsigned TmpReg1, TmpReg2;
1150 default: assert(0 && "Intrinsic not supported!");