1 //===-- SparcTargetMachine.cpp - Define TargetMachine for Sparc -----------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
11 //===----------------------------------------------------------------------===//
13 #include "SparcTargetMachine.h"
15 #include "llvm/CodeGen/Passes.h"
16 #include "llvm/PassManager.h"
17 #include "llvm/Support/TargetRegistry.h"
20 extern "C" void LLVMInitializeSparcTarget() {
21 // Register the target.
22 RegisterTargetMachine<SparcV8TargetMachine> X(TheSparcTarget);
23 RegisterTargetMachine<SparcV9TargetMachine> Y(TheSparcV9Target);
26 static std::string computeDataLayout(const SparcSubtarget &ST) {
27 // Sparc is big endian.
28 std::string Ret = "E";
30 // Some ABIs have 32bit pointers.
34 // Alignments for 64 bit integers.
37 // On SparcV9 128 floats are aligned to 128 bits, on others only to 64.
38 // On SparcV9 registers can hold 64 or 32 bits, on others only 32.
42 Ret += "-f128:64:64-n32";
47 /// SparcTargetMachine ctor - Create an ILP32 architecture model
49 SparcTargetMachine::SparcTargetMachine(const Target &T, StringRef TT,
50 StringRef CPU, StringRef FS,
51 const TargetOptions &Options,
52 Reloc::Model RM, CodeModel::Model CM,
55 : LLVMTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL),
56 Subtarget(TT, CPU, FS, is64bit),
57 DL(computeDataLayout(Subtarget)),
59 TLInfo(*this), TSInfo(*this),
60 FrameLowering(Subtarget) {
65 /// Sparc Code Generator Pass Configuration Options.
66 class SparcPassConfig : public TargetPassConfig {
68 SparcPassConfig(SparcTargetMachine *TM, PassManagerBase &PM)
69 : TargetPassConfig(TM, PM) {}
71 SparcTargetMachine &getSparcTargetMachine() const {
72 return getTM<SparcTargetMachine>();
75 virtual bool addInstSelector();
76 virtual bool addPreEmitPass();
80 TargetPassConfig *SparcTargetMachine::createPassConfig(PassManagerBase &PM) {
81 return new SparcPassConfig(this, PM);
84 bool SparcPassConfig::addInstSelector() {
85 addPass(createSparcISelDag(getSparcTargetMachine()));
89 bool SparcTargetMachine::addCodeEmitter(PassManagerBase &PM,
90 JITCodeEmitter &JCE) {
91 // Machine code emitter pass for Sparc.
92 PM.add(createSparcJITCodeEmitterPass(*this, JCE));
96 /// addPreEmitPass - This pass may be implemented by targets that want to run
97 /// passes immediately before machine code is emitted. This should return
98 /// true if -print-machineinstrs should print out the code after the passes.
99 bool SparcPassConfig::addPreEmitPass(){
100 addPass(createSparcDelaySlotFillerPass(getSparcTargetMachine()));
104 void SparcV8TargetMachine::anchor() { }
106 SparcV8TargetMachine::SparcV8TargetMachine(const Target &T,
107 StringRef TT, StringRef CPU,
109 const TargetOptions &Options,
112 CodeGenOpt::Level OL)
113 : SparcTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, false) {
116 void SparcV9TargetMachine::anchor() { }
118 SparcV9TargetMachine::SparcV9TargetMachine(const Target &T,
119 StringRef TT, StringRef CPU,
121 const TargetOptions &Options,
124 CodeGenOpt::Level OL)
125 : SparcTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, true) {