1 //===-- SparcTargetMachine.cpp - Define TargetMachine for Sparc -----------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
11 //===----------------------------------------------------------------------===//
13 #include "SparcTargetMachine.h"
15 #include "llvm/CodeGen/Passes.h"
16 #include "llvm/PassManager.h"
17 #include "llvm/Support/TargetRegistry.h"
20 extern "C" void LLVMInitializeSparcTarget() {
21 // Register the target.
22 RegisterTargetMachine<SparcV8TargetMachine> X(TheSparcTarget);
23 RegisterTargetMachine<SparcV9TargetMachine> Y(TheSparcV9Target);
26 static std::string computeDataLayout(const SparcSubtarget &ST) {
27 // Sparc is big endian.
28 std::string Ret = "E";
30 // V9 has 64 bit pointers, others have 32bit pointers.
36 // Alignments for 64 bit integers and doubles.
37 Ret += "-i64:64:64-f64:64:64";
39 // On SparcV9 128 floats are aligned to 128 bits, on others only to 64.
40 // On SparcV9 registers can hold 64 or 32 bits, on others only 32.
42 Ret += "-f128:128:128-n32:64";
44 Ret += "-f128:64:64-n32";
49 /// SparcTargetMachine ctor - Create an ILP32 architecture model
51 SparcTargetMachine::SparcTargetMachine(const Target &T, StringRef TT,
52 StringRef CPU, StringRef FS,
53 const TargetOptions &Options,
54 Reloc::Model RM, CodeModel::Model CM,
57 : LLVMTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL),
58 Subtarget(TT, CPU, FS, is64bit),
59 DL(computeDataLayout(Subtarget)),
61 TLInfo(*this), TSInfo(*this),
62 FrameLowering(Subtarget) {
67 /// Sparc Code Generator Pass Configuration Options.
68 class SparcPassConfig : public TargetPassConfig {
70 SparcPassConfig(SparcTargetMachine *TM, PassManagerBase &PM)
71 : TargetPassConfig(TM, PM) {}
73 SparcTargetMachine &getSparcTargetMachine() const {
74 return getTM<SparcTargetMachine>();
77 virtual bool addInstSelector();
78 virtual bool addPreEmitPass();
82 TargetPassConfig *SparcTargetMachine::createPassConfig(PassManagerBase &PM) {
83 return new SparcPassConfig(this, PM);
86 bool SparcPassConfig::addInstSelector() {
87 addPass(createSparcISelDag(getSparcTargetMachine()));
91 bool SparcTargetMachine::addCodeEmitter(PassManagerBase &PM,
92 JITCodeEmitter &JCE) {
93 // Machine code emitter pass for Sparc.
94 PM.add(createSparcJITCodeEmitterPass(*this, JCE));
98 /// addPreEmitPass - This pass may be implemented by targets that want to run
99 /// passes immediately before machine code is emitted. This should return
100 /// true if -print-machineinstrs should print out the code after the passes.
101 bool SparcPassConfig::addPreEmitPass(){
102 addPass(createSparcDelaySlotFillerPass(getSparcTargetMachine()));
106 void SparcV8TargetMachine::anchor() { }
108 SparcV8TargetMachine::SparcV8TargetMachine(const Target &T,
109 StringRef TT, StringRef CPU,
111 const TargetOptions &Options,
114 CodeGenOpt::Level OL)
115 : SparcTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, false) {
118 void SparcV9TargetMachine::anchor() { }
120 SparcV9TargetMachine::SparcV9TargetMachine(const Target &T,
121 StringRef TT, StringRef CPU,
123 const TargetOptions &Options,
126 CodeGenOpt::Level OL)
127 : SparcTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, true) {