1 //===-- SparcTargetMachine.cpp - Define TargetMachine for Sparc -----------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
11 //===----------------------------------------------------------------------===//
13 #include "SparcTargetMachine.h"
14 #include "SparcTargetObjectFile.h"
16 #include "llvm/CodeGen/Passes.h"
17 #include "llvm/IR/LegacyPassManager.h"
18 #include "llvm/Support/TargetRegistry.h"
21 extern "C" void LLVMInitializeSparcTarget() {
22 // Register the target.
23 RegisterTargetMachine<SparcV8TargetMachine> X(TheSparcTarget);
24 RegisterTargetMachine<SparcV9TargetMachine> Y(TheSparcV9Target);
27 static std::string computeDataLayout(bool is64Bit) {
28 // Sparc is big endian.
29 std::string Ret = "E-m:e";
31 // Some ABIs have 32bit pointers.
35 // Alignments for 64 bit integers.
38 // On SparcV9 128 floats are aligned to 128 bits, on others only to 64.
39 // On SparcV9 registers can hold 64 or 32 bits, on others only 32.
43 Ret += "-f128:64-n32";
53 /// SparcTargetMachine ctor - Create an ILP32 architecture model
55 SparcTargetMachine::SparcTargetMachine(const Target &T, StringRef TT,
56 StringRef CPU, StringRef FS,
57 const TargetOptions &Options,
58 Reloc::Model RM, CodeModel::Model CM,
61 : LLVMTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL),
62 TLOF(make_unique<SparcELFTargetObjectFile>()),
63 DL(computeDataLayout(is64bit)),
64 Subtarget(TT, CPU, FS, *this, is64bit) {
68 SparcTargetMachine::~SparcTargetMachine() {}
71 /// Sparc Code Generator Pass Configuration Options.
72 class SparcPassConfig : public TargetPassConfig {
74 SparcPassConfig(SparcTargetMachine *TM, PassManagerBase &PM)
75 : TargetPassConfig(TM, PM) {}
77 SparcTargetMachine &getSparcTargetMachine() const {
78 return getTM<SparcTargetMachine>();
81 void addIRPasses() override;
82 bool addInstSelector() override;
83 void addPreEmitPass() override;
87 TargetPassConfig *SparcTargetMachine::createPassConfig(PassManagerBase &PM) {
88 return new SparcPassConfig(this, PM);
91 void SparcPassConfig::addIRPasses() {
92 addPass(createAtomicExpandPass(&getSparcTargetMachine()));
94 TargetPassConfig::addIRPasses();
97 bool SparcPassConfig::addInstSelector() {
98 addPass(createSparcISelDag(getSparcTargetMachine()));
102 void SparcPassConfig::addPreEmitPass(){
103 addPass(createSparcDelaySlotFillerPass(getSparcTargetMachine()));
106 void SparcV8TargetMachine::anchor() { }
108 SparcV8TargetMachine::SparcV8TargetMachine(const Target &T,
109 StringRef TT, StringRef CPU,
111 const TargetOptions &Options,
114 CodeGenOpt::Level OL)
115 : SparcTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, false) {
118 void SparcV9TargetMachine::anchor() { }
120 SparcV9TargetMachine::SparcV9TargetMachine(const Target &T,
121 StringRef TT, StringRef CPU,
123 const TargetOptions &Options,
126 CodeGenOpt::Level OL)
127 : SparcTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, true) {