1 //===- SparcRegisterInfo.cpp - SPARC Register Information -------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by the LLVM research group and is distributed under
6 // the University of Illinois Open Source License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the SPARC implementation of the MRegisterInfo class.
12 //===----------------------------------------------------------------------===//
15 #include "SparcRegisterInfo.h"
16 #include "SparcSubtarget.h"
17 #include "llvm/CodeGen/MachineInstrBuilder.h"
18 #include "llvm/CodeGen/MachineFunction.h"
19 #include "llvm/CodeGen/MachineFrameInfo.h"
20 #include "llvm/CodeGen/MachineLocation.h"
21 #include "llvm/Type.h"
22 #include "llvm/ADT/STLExtras.h"
26 SparcRegisterInfo::SparcRegisterInfo(SparcSubtarget &st)
27 : SparcGenRegisterInfo(SP::ADJCALLSTACKDOWN, SP::ADJCALLSTACKUP),
31 void SparcRegisterInfo::
32 storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
33 unsigned SrcReg, int FI,
34 const TargetRegisterClass *RC) const {
35 // On the order of operands here: think "[FrameIdx + 0] = SrcReg".
36 if (RC == SP::IntRegsRegisterClass)
37 BuildMI(MBB, I, SP::STri, 3).addFrameIndex(FI).addImm(0).addReg(SrcReg);
38 else if (RC == SP::FPRegsRegisterClass)
39 BuildMI(MBB, I, SP::STFri, 3).addFrameIndex(FI).addImm(0).addReg(SrcReg);
40 else if (RC == SP::DFPRegsRegisterClass)
41 BuildMI(MBB, I, SP::STDFri, 3).addFrameIndex(FI).addImm(0).addReg(SrcReg);
43 assert(0 && "Can't store this register to stack slot");
46 void SparcRegisterInfo::
47 loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
48 unsigned DestReg, int FI,
49 const TargetRegisterClass *RC) const {
50 if (RC == SP::IntRegsRegisterClass)
51 BuildMI(MBB, I, SP::LDri, 2, DestReg).addFrameIndex(FI).addImm(0);
52 else if (RC == SP::FPRegsRegisterClass)
53 BuildMI(MBB, I, SP::LDFri, 2, DestReg).addFrameIndex(FI).addImm (0);
54 else if (RC == SP::DFPRegsRegisterClass)
55 BuildMI(MBB, I, SP::LDDFri, 2, DestReg).addFrameIndex(FI).addImm(0);
57 assert(0 && "Can't load this register from stack slot");
60 void SparcRegisterInfo::copyRegToReg(MachineBasicBlock &MBB,
61 MachineBasicBlock::iterator I,
62 unsigned DestReg, unsigned SrcReg,
63 const TargetRegisterClass *RC) const {
64 if (RC == SP::IntRegsRegisterClass)
65 BuildMI(MBB, I, SP::ORrr, 2, DestReg).addReg(SP::G0).addReg(SrcReg);
66 else if (RC == SP::FPRegsRegisterClass)
67 BuildMI(MBB, I, SP::FMOVS, 1, DestReg).addReg(SrcReg);
68 else if (RC == SP::DFPRegsRegisterClass)
69 BuildMI(MBB, I, Subtarget.isV9() ? SP::FMOVD : SP::FpMOVD,
70 1, DestReg).addReg(SrcReg);
72 assert (0 && "Can't copy this register");
75 MachineInstr *SparcRegisterInfo::foldMemoryOperand(MachineInstr* MI,
79 switch (MI->getOpcode()) {
81 if (MI->getOperand(1).isRegister() && MI->getOperand(1).getReg() == SP::G0&&
82 MI->getOperand(0).isRegister() && MI->getOperand(2).isRegister()) {
83 if (OpNum == 0) // COPY -> STORE
84 return BuildMI(SP::STri, 3).addFrameIndex(FI).addImm(0)
85 .addReg(MI->getOperand(2).getReg());
87 return BuildMI(SP::LDri, 2, MI->getOperand(0).getReg())
88 .addFrameIndex(FI).addImm(0);
95 if (OpNum == 0) // COPY -> STORE
96 return BuildMI(isFloat ? SP::STFri : SP::STDFri, 3)
97 .addFrameIndex(FI).addImm(0).addReg(MI->getOperand(1).getReg());
99 return BuildMI(isFloat ? SP::LDFri : SP::LDDFri, 2,
100 MI->getOperand(0).getReg()).addFrameIndex(FI).addImm(0);
106 void SparcRegisterInfo::
107 eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB,
108 MachineBasicBlock::iterator I) const {
109 MachineInstr &MI = *I;
110 int Size = MI.getOperand(0).getImmedValue();
111 if (MI.getOpcode() == SP::ADJCALLSTACKDOWN)
114 BuildMI(MBB, I, SP::ADDri, 2, SP::O6).addReg(SP::O6).addImm(Size);
119 SparcRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II) const {
121 MachineInstr &MI = *II;
122 while (!MI.getOperand(i).isFrameIndex()) {
124 assert(i < MI.getNumOperands() && "Instr doesn't have FrameIndex operand!");
127 int FrameIndex = MI.getOperand(i).getFrameIndex();
129 // Addressable stack objects are accessed using neg. offsets from %fp
130 MachineFunction &MF = *MI.getParent()->getParent();
131 int Offset = MF.getFrameInfo()->getObjectOffset(FrameIndex) +
132 MI.getOperand(i+1).getImmedValue();
134 // Replace frame index with a frame pointer reference.
135 if (Offset >= -4096 && Offset <= 4095) {
136 // If the offset is small enough to fit in the immediate field, directly
138 MI.getOperand(i).ChangeToRegister(SP::I6);
139 MI.getOperand(i+1).ChangeToImmediate(Offset);
141 // Otherwise, emit a G1 = SETHI %hi(offset). FIXME: it would be better to
142 // scavenge a register here instead of reserving G1 all of the time.
143 unsigned OffHi = (unsigned)Offset >> 10U;
144 BuildMI(*MI.getParent(), II, SP::SETHIi, 1, SP::G1).addImm(OffHi);
146 BuildMI(*MI.getParent(), II, SP::ADDrr, 2,
147 SP::G1).addReg(SP::G1).addReg(SP::I6);
148 // Insert: G1+%lo(offset) into the user.
149 MI.getOperand(i).ChangeToRegister(SP::G1);
150 MI.getOperand(i+1).ChangeToImmediate(Offset & ((1 << 10)-1));
154 void SparcRegisterInfo::
155 processFunctionBeforeFrameFinalized(MachineFunction &MF) const {}
157 void SparcRegisterInfo::emitPrologue(MachineFunction &MF) const {
158 MachineBasicBlock &MBB = MF.front();
159 MachineFrameInfo *MFI = MF.getFrameInfo();
161 // Get the number of bytes to allocate from the FrameInfo
162 int NumBytes = (int) MFI->getStackSize();
164 // Emit the correct save instruction based on the number of bytes in
165 // the frame. Minimum stack frame size according to V8 ABI is:
166 // 16 words for register window spill
167 // 1 word for address of returned aggregate-value
168 // + 6 words for passing parameters on the stack
170 // 23 words * 4 bytes per word = 92 bytes
172 // Round up to next doubleword boundary -- a double-word boundary
173 // is required by the ABI.
174 NumBytes = (NumBytes + 7) & ~7;
175 NumBytes = -NumBytes;
177 if (NumBytes >= -4096) {
178 BuildMI(MBB, MBB.begin(), SP::SAVEri, 2,
179 SP::O6).addImm(NumBytes).addReg(SP::O6);
181 MachineBasicBlock::iterator InsertPt = MBB.begin();
182 // Emit this the hard way. This clobbers G1 which we always know is
184 unsigned OffHi = (unsigned)NumBytes >> 10U;
185 BuildMI(MBB, InsertPt, SP::SETHIi, 1, SP::G1).addImm(OffHi);
187 BuildMI(MBB, InsertPt, SP::ORri, 2, SP::G1)
188 .addReg(SP::G1).addImm(NumBytes & ((1 << 10)-1));
189 BuildMI(MBB, InsertPt, SP::SAVErr, 2,
190 SP::O6).addReg(SP::O6).addReg(SP::G1);
194 void SparcRegisterInfo::emitEpilogue(MachineFunction &MF,
195 MachineBasicBlock &MBB) const {
196 MachineBasicBlock::iterator MBBI = prior(MBB.end());
197 assert(MBBI->getOpcode() == SP::RETL &&
198 "Can only put epilog before 'retl' instruction!");
199 BuildMI(MBB, MBBI, SP::RESTORErr, 2, SP::G0).addReg(SP::G0).addReg(SP::G0);
202 unsigned SparcRegisterInfo::getRARegister() const {
203 assert(0 && "What is the return address register");
207 unsigned SparcRegisterInfo::getFrameRegister(MachineFunction &MF) const {
208 assert(0 && "What is the frame register");
212 #include "SparcGenRegisterInfo.inc"