1 //===- SparcRegisterInfo.cpp - SPARC Register Information -------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the SPARC implementation of the MRegisterInfo class.
12 //===----------------------------------------------------------------------===//
15 #include "SparcRegisterInfo.h"
16 #include "SparcSubtarget.h"
17 #include "llvm/CodeGen/MachineInstrBuilder.h"
18 #include "llvm/CodeGen/MachineFunction.h"
19 #include "llvm/CodeGen/MachineFrameInfo.h"
20 #include "llvm/CodeGen/MachineLocation.h"
21 #include "llvm/Target/TargetInstrInfo.h"
22 #include "llvm/Type.h"
23 #include "llvm/ADT/BitVector.h"
24 #include "llvm/ADT/STLExtras.h"
27 SparcRegisterInfo::SparcRegisterInfo(SparcSubtarget &st,
28 const TargetInstrInfo &tii)
29 : SparcGenRegisterInfo(SP::ADJCALLSTACKDOWN, SP::ADJCALLSTACKUP),
30 Subtarget(st), TII(tii) {
33 void SparcRegisterInfo::
34 storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
35 unsigned SrcReg, bool isKill, int FI,
36 const TargetRegisterClass *RC) const {
37 // On the order of operands here: think "[FrameIdx + 0] = SrcReg".
38 if (RC == SP::IntRegsRegisterClass)
39 BuildMI(MBB, I, TII.get(SP::STri)).addFrameIndex(FI).addImm(0)
40 .addReg(SrcReg, false, false, isKill);
41 else if (RC == SP::FPRegsRegisterClass)
42 BuildMI(MBB, I, TII.get(SP::STFri)).addFrameIndex(FI).addImm(0)
43 .addReg(SrcReg, false, false, isKill);
44 else if (RC == SP::DFPRegsRegisterClass)
45 BuildMI(MBB, I, TII.get(SP::STDFri)).addFrameIndex(FI).addImm(0)
46 .addReg(SrcReg, false, false, isKill);
48 assert(0 && "Can't store this register to stack slot");
51 void SparcRegisterInfo::storeRegToAddr(MachineFunction &MF, unsigned SrcReg,
53 SmallVectorImpl<MachineOperand> &Addr,
54 const TargetRegisterClass *RC,
55 SmallVectorImpl<MachineInstr*> &NewMIs) const {
57 if (RC == SP::IntRegsRegisterClass)
59 else if (RC == SP::FPRegsRegisterClass)
61 else if (RC == SP::DFPRegsRegisterClass)
64 assert(0 && "Can't load this register");
65 MachineInstrBuilder MIB = BuildMI(TII.get(Opc));
66 for (unsigned i = 0, e = Addr.size(); i != e; ++i) {
67 MachineOperand &MO = Addr[i];
69 MIB.addReg(MO.getReg());
70 else if (MO.isImmediate())
71 MIB.addImm(MO.getImm());
74 MIB.addFrameIndex(MO.getIndex());
77 MIB.addReg(SrcReg, false, false, isKill);
78 NewMIs.push_back(MIB);
82 void SparcRegisterInfo::
83 loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
84 unsigned DestReg, int FI,
85 const TargetRegisterClass *RC) const {
86 if (RC == SP::IntRegsRegisterClass)
87 BuildMI(MBB, I, TII.get(SP::LDri), DestReg).addFrameIndex(FI).addImm(0);
88 else if (RC == SP::FPRegsRegisterClass)
89 BuildMI(MBB, I, TII.get(SP::LDFri), DestReg).addFrameIndex(FI).addImm(0);
90 else if (RC == SP::DFPRegsRegisterClass)
91 BuildMI(MBB, I, TII.get(SP::LDDFri), DestReg).addFrameIndex(FI).addImm(0);
93 assert(0 && "Can't load this register from stack slot");
96 void SparcRegisterInfo::loadRegFromAddr(MachineFunction &MF, unsigned DestReg,
97 SmallVectorImpl<MachineOperand> &Addr,
98 const TargetRegisterClass *RC,
99 SmallVectorImpl<MachineInstr*> &NewMIs) const {
101 if (RC == SP::IntRegsRegisterClass)
103 else if (RC == SP::FPRegsRegisterClass)
105 else if (RC == SP::DFPRegsRegisterClass)
108 assert(0 && "Can't load this register");
109 MachineInstrBuilder MIB = BuildMI(TII.get(Opc), DestReg);
110 for (unsigned i = 0, e = Addr.size(); i != e; ++i) {
111 MachineOperand &MO = Addr[i];
113 MIB.addReg(MO.getReg());
115 MIB.addImm(MO.getImm());
118 MIB.addFrameIndex(MO.getIndex());
121 NewMIs.push_back(MIB);
125 void SparcRegisterInfo::copyRegToReg(MachineBasicBlock &MBB,
126 MachineBasicBlock::iterator I,
127 unsigned DestReg, unsigned SrcReg,
128 const TargetRegisterClass *DestRC,
129 const TargetRegisterClass *SrcRC) const {
130 if (DestRC != SrcRC) {
131 cerr << "Not yet supported!";
135 if (DestRC == SP::IntRegsRegisterClass)
136 BuildMI(MBB, I, TII.get(SP::ORrr), DestReg).addReg(SP::G0).addReg(SrcReg);
137 else if (DestRC == SP::FPRegsRegisterClass)
138 BuildMI(MBB, I, TII.get(SP::FMOVS), DestReg).addReg(SrcReg);
139 else if (DestRC == SP::DFPRegsRegisterClass)
140 BuildMI(MBB, I, TII.get(Subtarget.isV9() ? SP::FMOVD : SP::FpMOVD),DestReg)
143 assert (0 && "Can't copy this register");
146 void SparcRegisterInfo::reMaterialize(MachineBasicBlock &MBB,
147 MachineBasicBlock::iterator I,
149 const MachineInstr *Orig) const {
150 MachineInstr *MI = Orig->clone();
151 MI->getOperand(0).setReg(DestReg);
155 MachineInstr *SparcRegisterInfo::foldMemoryOperand(MachineInstr* MI,
156 SmallVectorImpl<unsigned> &Ops,
158 if (Ops.size() != 1) return NULL;
160 unsigned OpNum = Ops[0];
161 bool isFloat = false;
162 MachineInstr *NewMI = NULL;
163 switch (MI->getOpcode()) {
165 if (MI->getOperand(1).isRegister() && MI->getOperand(1).getReg() == SP::G0&&
166 MI->getOperand(0).isRegister() && MI->getOperand(2).isRegister()) {
167 if (OpNum == 0) // COPY -> STORE
168 NewMI = BuildMI(TII.get(SP::STri)).addFrameIndex(FI).addImm(0)
169 .addReg(MI->getOperand(2).getReg());
171 NewMI = BuildMI(TII.get(SP::LDri), MI->getOperand(0).getReg())
172 .addFrameIndex(FI).addImm(0);
179 if (OpNum == 0) // COPY -> STORE
180 NewMI = BuildMI(TII.get(isFloat ? SP::STFri : SP::STDFri))
181 .addFrameIndex(FI).addImm(0).addReg(MI->getOperand(1).getReg());
183 NewMI = BuildMI(TII.get(isFloat ? SP::LDFri : SP::LDDFri),
184 MI->getOperand(0).getReg()).addFrameIndex(FI).addImm(0);
189 NewMI->copyKillDeadInfo(MI);
193 const unsigned* SparcRegisterInfo::getCalleeSavedRegs(const MachineFunction *MF)
195 static const unsigned CalleeSavedRegs[] = { 0 };
196 return CalleeSavedRegs;
199 BitVector SparcRegisterInfo::getReservedRegs(const MachineFunction &MF) const {
200 BitVector Reserved(getNumRegs());
201 Reserved.set(SP::G2);
202 Reserved.set(SP::G3);
203 Reserved.set(SP::G4);
204 Reserved.set(SP::O6);
205 Reserved.set(SP::I6);
206 Reserved.set(SP::I7);
207 Reserved.set(SP::G0);
208 Reserved.set(SP::G5);
209 Reserved.set(SP::G6);
210 Reserved.set(SP::G7);
215 const TargetRegisterClass* const*
216 SparcRegisterInfo::getCalleeSavedRegClasses(const MachineFunction *MF) const {
217 static const TargetRegisterClass * const CalleeSavedRegClasses[] = { 0 };
218 return CalleeSavedRegClasses;
221 bool SparcRegisterInfo::hasFP(const MachineFunction &MF) const {
225 void SparcRegisterInfo::
226 eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB,
227 MachineBasicBlock::iterator I) const {
228 MachineInstr &MI = *I;
229 int Size = MI.getOperand(0).getImm();
230 if (MI.getOpcode() == SP::ADJCALLSTACKDOWN)
233 BuildMI(MBB, I, TII.get(SP::ADDri), SP::O6).addReg(SP::O6).addImm(Size);
237 void SparcRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,
238 int SPAdj, RegScavenger *RS) const {
239 assert(SPAdj == 0 && "Unexpected");
242 MachineInstr &MI = *II;
243 while (!MI.getOperand(i).isFrameIndex()) {
245 assert(i < MI.getNumOperands() && "Instr doesn't have FrameIndex operand!");
248 int FrameIndex = MI.getOperand(i).getIndex();
250 // Addressable stack objects are accessed using neg. offsets from %fp
251 MachineFunction &MF = *MI.getParent()->getParent();
252 int Offset = MF.getFrameInfo()->getObjectOffset(FrameIndex) +
253 MI.getOperand(i+1).getImm();
255 // Replace frame index with a frame pointer reference.
256 if (Offset >= -4096 && Offset <= 4095) {
257 // If the offset is small enough to fit in the immediate field, directly
259 MI.getOperand(i).ChangeToRegister(SP::I6, false);
260 MI.getOperand(i+1).ChangeToImmediate(Offset);
262 // Otherwise, emit a G1 = SETHI %hi(offset). FIXME: it would be better to
263 // scavenge a register here instead of reserving G1 all of the time.
264 unsigned OffHi = (unsigned)Offset >> 10U;
265 BuildMI(*MI.getParent(), II, TII.get(SP::SETHIi), SP::G1).addImm(OffHi);
267 BuildMI(*MI.getParent(), II, TII.get(SP::ADDrr), SP::G1).addReg(SP::G1)
269 // Insert: G1+%lo(offset) into the user.
270 MI.getOperand(i).ChangeToRegister(SP::G1, false);
271 MI.getOperand(i+1).ChangeToImmediate(Offset & ((1 << 10)-1));
275 void SparcRegisterInfo::
276 processFunctionBeforeFrameFinalized(MachineFunction &MF) const {}
278 void SparcRegisterInfo::emitPrologue(MachineFunction &MF) const {
279 MachineBasicBlock &MBB = MF.front();
280 MachineFrameInfo *MFI = MF.getFrameInfo();
282 // Get the number of bytes to allocate from the FrameInfo
283 int NumBytes = (int) MFI->getStackSize();
285 // Emit the correct save instruction based on the number of bytes in
286 // the frame. Minimum stack frame size according to V8 ABI is:
287 // 16 words for register window spill
288 // 1 word for address of returned aggregate-value
289 // + 6 words for passing parameters on the stack
291 // 23 words * 4 bytes per word = 92 bytes
293 // Round up to next doubleword boundary -- a double-word boundary
294 // is required by the ABI.
295 NumBytes = (NumBytes + 7) & ~7;
296 NumBytes = -NumBytes;
298 if (NumBytes >= -4096) {
299 BuildMI(MBB, MBB.begin(), TII.get(SP::SAVEri),
300 SP::O6).addImm(NumBytes).addReg(SP::O6);
302 MachineBasicBlock::iterator InsertPt = MBB.begin();
303 // Emit this the hard way. This clobbers G1 which we always know is
305 unsigned OffHi = (unsigned)NumBytes >> 10U;
306 BuildMI(MBB, InsertPt, TII.get(SP::SETHIi), SP::G1).addImm(OffHi);
308 BuildMI(MBB, InsertPt, TII.get(SP::ORri), SP::G1)
309 .addReg(SP::G1).addImm(NumBytes & ((1 << 10)-1));
310 BuildMI(MBB, InsertPt, TII.get(SP::SAVErr), SP::O6)
311 .addReg(SP::O6).addReg(SP::G1);
315 void SparcRegisterInfo::emitEpilogue(MachineFunction &MF,
316 MachineBasicBlock &MBB) const {
317 MachineBasicBlock::iterator MBBI = prior(MBB.end());
318 assert(MBBI->getOpcode() == SP::RETL &&
319 "Can only put epilog before 'retl' instruction!");
320 BuildMI(MBB, MBBI, TII.get(SP::RESTORErr), SP::G0).addReg(SP::G0)
324 unsigned SparcRegisterInfo::getRARegister() const {
325 assert(0 && "What is the return address register");
329 unsigned SparcRegisterInfo::getFrameRegister(MachineFunction &MF) const {
330 assert(0 && "What is the frame register");
334 unsigned SparcRegisterInfo::getEHExceptionRegister() const {
335 assert(0 && "What is the exception register");
339 unsigned SparcRegisterInfo::getEHHandlerRegister() const {
340 assert(0 && "What is the exception handler register");
344 int SparcRegisterInfo::getDwarfRegNum(unsigned RegNum, bool isEH) const {
345 assert(0 && "What is the dwarf register number");
349 #include "SparcGenRegisterInfo.inc"