1 //===-- SparcInstrInfo.td - Target Description for Sparc Target -----------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the Sparc instructions in TableGen format.
12 //===----------------------------------------------------------------------===//
14 //===----------------------------------------------------------------------===//
15 // Instruction format superclass
16 //===----------------------------------------------------------------------===//
18 include "SparcInstrFormats.td"
20 //===----------------------------------------------------------------------===//
21 // Feature predicates.
22 //===----------------------------------------------------------------------===//
24 // True when generating 32-bit code.
25 def Is32Bit : Predicate<"!Subtarget->is64Bit()">;
27 // True when generating 64-bit code. This also implies HasV9.
28 def Is64Bit : Predicate<"Subtarget->is64Bit()">;
30 // HasV9 - This predicate is true when the target processor supports V9
31 // instructions. Note that the machine may be running in 32-bit mode.
32 def HasV9 : Predicate<"Subtarget->isV9()">,
33 AssemblerPredicate<"FeatureV9">;
35 // HasNoV9 - This predicate is true when the target doesn't have V9
36 // instructions. Use of this is just a hack for the isel not having proper
37 // costs for V8 instructions that are more expensive than their V9 ones.
38 def HasNoV9 : Predicate<"!Subtarget->isV9()">;
40 // HasVIS - This is true when the target processor has VIS extensions.
41 def HasVIS : Predicate<"Subtarget->isVIS()">,
42 AssemblerPredicate<"FeatureVIS">;
43 def HasVIS2 : Predicate<"Subtarget->isVIS2()">,
44 AssemblerPredicate<"FeatureVIS2">;
45 def HasVIS3 : Predicate<"Subtarget->isVIS3()">,
46 AssemblerPredicate<"FeatureVIS3">;
48 // HasHardQuad - This is true when the target processor supports quad floating
49 // point instructions.
50 def HasHardQuad : Predicate<"Subtarget->hasHardQuad()">;
52 // UseDeprecatedInsts - This predicate is true when the target processor is a
53 // V8, or when it is V9 but the V8 deprecated instructions are efficient enough
54 // to use when appropriate. In either of these cases, the instruction selector
55 // will pick deprecated instructions.
56 def UseDeprecatedInsts : Predicate<"Subtarget->useDeprecatedV8Instructions()">;
58 //===----------------------------------------------------------------------===//
59 // Instruction Pattern Stuff
60 //===----------------------------------------------------------------------===//
62 def simm11 : PatLeaf<(imm), [{ return isInt<11>(N->getSExtValue()); }]>;
64 def simm13 : PatLeaf<(imm), [{ return isInt<13>(N->getSExtValue()); }]>;
66 def LO10 : SDNodeXForm<imm, [{
67 return CurDAG->getTargetConstant((unsigned)N->getZExtValue() & 1023, SDLoc(N),
71 def HI22 : SDNodeXForm<imm, [{
72 // Transformation function: shift the immediate value down into the low bits.
73 return CurDAG->getTargetConstant((unsigned)N->getZExtValue() >> 10, SDLoc(N),
77 def SETHIimm : PatLeaf<(imm), [{
78 return isShiftedUInt<22, 10>(N->getZExtValue());
82 def ADDRrr : ComplexPattern<iPTR, 2, "SelectADDRrr", [], []>;
83 def ADDRri : ComplexPattern<iPTR, 2, "SelectADDRri", [frameindex], []>;
86 def SparcMEMrrAsmOperand : AsmOperandClass {
88 let ParserMethod = "parseMEMOperand";
91 def SparcMEMriAsmOperand : AsmOperandClass {
93 let ParserMethod = "parseMEMOperand";
96 def MEMrr : Operand<iPTR> {
97 let PrintMethod = "printMemOperand";
98 let MIOperandInfo = (ops ptr_rc, ptr_rc);
99 let ParserMatchClass = SparcMEMrrAsmOperand;
101 def MEMri : Operand<iPTR> {
102 let PrintMethod = "printMemOperand";
103 let MIOperandInfo = (ops ptr_rc, i32imm);
104 let ParserMatchClass = SparcMEMriAsmOperand;
107 def TLSSym : Operand<iPTR>;
109 // Branch targets have OtherVT type.
110 def brtarget : Operand<OtherVT> {
111 let EncoderMethod = "getBranchTargetOpValue";
114 def bprtarget : Operand<OtherVT> {
115 let EncoderMethod = "getBranchPredTargetOpValue";
118 def bprtarget16 : Operand<OtherVT> {
119 let EncoderMethod = "getBranchOnRegTargetOpValue";
122 def calltarget : Operand<i32> {
123 let EncoderMethod = "getCallTargetOpValue";
124 let DecoderMethod = "DecodeCall";
127 def simm13Op : Operand<i32> {
128 let DecoderMethod = "DecodeSIMM13";
131 // Operand for printing out a condition code.
132 let PrintMethod = "printCCOperand" in
133 def CCOp : Operand<i32>;
136 SDTypeProfile<0, 2, [SDTCisInt<0>, SDTCisSameAs<0, 1>]>;
138 SDTypeProfile<0, 2, [SDTCisFP<0>, SDTCisSameAs<0, 1>]>;
140 SDTypeProfile<0, 2, [SDTCisVT<0, OtherVT>, SDTCisVT<1, i32>]>;
142 SDTypeProfile<1, 3, [SDTCisSameAs<0, 1>, SDTCisSameAs<1, 2>, SDTCisVT<3, i32>]>;
144 SDTypeProfile<1, 1, [SDTCisVT<0, f32>, SDTCisFP<1>]>;
146 SDTypeProfile<1, 1, [SDTCisFP<0>, SDTCisVT<1, f32>]>;
148 SDTypeProfile<1, 1, [SDTCisVT<0, f64>, SDTCisFP<1>]>;
150 SDTypeProfile<1, 1, [SDTCisFP<0>, SDTCisVT<1, f64>]>;
153 SDTypeProfile<1, 3, [SDTCisInt<0>, SDTCisSameAs<0, 1>, SDTCisPtrTy<2>]>;
155 SDTypeProfile<1, 2, [SDTCisPtrTy<0>, SDTCisPtrTy<1>]>;
157 def SPcmpicc : SDNode<"SPISD::CMPICC", SDTSPcmpicc, [SDNPOutGlue]>;
158 def SPcmpfcc : SDNode<"SPISD::CMPFCC", SDTSPcmpfcc, [SDNPOutGlue]>;
159 def SPbricc : SDNode<"SPISD::BRICC", SDTSPbrcc, [SDNPHasChain, SDNPInGlue]>;
160 def SPbrxcc : SDNode<"SPISD::BRXCC", SDTSPbrcc, [SDNPHasChain, SDNPInGlue]>;
161 def SPbrfcc : SDNode<"SPISD::BRFCC", SDTSPbrcc, [SDNPHasChain, SDNPInGlue]>;
163 def SPhi : SDNode<"SPISD::Hi", SDTIntUnaryOp>;
164 def SPlo : SDNode<"SPISD::Lo", SDTIntUnaryOp>;
166 def SPftoi : SDNode<"SPISD::FTOI", SDTSPFTOI>;
167 def SPitof : SDNode<"SPISD::ITOF", SDTSPITOF>;
168 def SPftox : SDNode<"SPISD::FTOX", SDTSPFTOX>;
169 def SPxtof : SDNode<"SPISD::XTOF", SDTSPXTOF>;
171 def SPselecticc : SDNode<"SPISD::SELECT_ICC", SDTSPselectcc, [SDNPInGlue]>;
172 def SPselectxcc : SDNode<"SPISD::SELECT_XCC", SDTSPselectcc, [SDNPInGlue]>;
173 def SPselectfcc : SDNode<"SPISD::SELECT_FCC", SDTSPselectcc, [SDNPInGlue]>;
175 // These are target-independent nodes, but have target-specific formats.
176 def SDT_SPCallSeqStart : SDCallSeqStart<[ SDTCisVT<0, i32> ]>;
177 def SDT_SPCallSeqEnd : SDCallSeqEnd<[ SDTCisVT<0, i32>,
180 def callseq_start : SDNode<"ISD::CALLSEQ_START", SDT_SPCallSeqStart,
181 [SDNPHasChain, SDNPOutGlue]>;
182 def callseq_end : SDNode<"ISD::CALLSEQ_END", SDT_SPCallSeqEnd,
183 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]>;
185 def SDT_SPCall : SDTypeProfile<0, -1, [SDTCisVT<0, i32>]>;
186 def call : SDNode<"SPISD::CALL", SDT_SPCall,
187 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue,
190 def SDT_SPRet : SDTypeProfile<0, 1, [SDTCisVT<0, i32>]>;
191 def retflag : SDNode<"SPISD::RET_FLAG", SDT_SPRet,
192 [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>;
194 def flushw : SDNode<"SPISD::FLUSHW", SDTNone,
195 [SDNPHasChain, SDNPSideEffect, SDNPMayStore]>;
197 def tlsadd : SDNode<"SPISD::TLS_ADD", SDTSPtlsadd>;
198 def tlsld : SDNode<"SPISD::TLS_LD", SDTSPtlsld>;
199 def tlscall : SDNode<"SPISD::TLS_CALL", SDT_SPCall,
200 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue,
203 def getPCX : Operand<iPTR> {
204 let PrintMethod = "printGetPCX";
207 //===----------------------------------------------------------------------===//
208 // SPARC Flag Conditions
209 //===----------------------------------------------------------------------===//
211 // Note that these values must be kept in sync with the CCOp::CondCode enum
213 class ICC_VAL<int N> : PatLeaf<(i32 N)>;
214 def ICC_NE : ICC_VAL< 9>; // Not Equal
215 def ICC_E : ICC_VAL< 1>; // Equal
216 def ICC_G : ICC_VAL<10>; // Greater
217 def ICC_LE : ICC_VAL< 2>; // Less or Equal
218 def ICC_GE : ICC_VAL<11>; // Greater or Equal
219 def ICC_L : ICC_VAL< 3>; // Less
220 def ICC_GU : ICC_VAL<12>; // Greater Unsigned
221 def ICC_LEU : ICC_VAL< 4>; // Less or Equal Unsigned
222 def ICC_CC : ICC_VAL<13>; // Carry Clear/Great or Equal Unsigned
223 def ICC_CS : ICC_VAL< 5>; // Carry Set/Less Unsigned
224 def ICC_POS : ICC_VAL<14>; // Positive
225 def ICC_NEG : ICC_VAL< 6>; // Negative
226 def ICC_VC : ICC_VAL<15>; // Overflow Clear
227 def ICC_VS : ICC_VAL< 7>; // Overflow Set
229 class FCC_VAL<int N> : PatLeaf<(i32 N)>;
230 def FCC_U : FCC_VAL<23>; // Unordered
231 def FCC_G : FCC_VAL<22>; // Greater
232 def FCC_UG : FCC_VAL<21>; // Unordered or Greater
233 def FCC_L : FCC_VAL<20>; // Less
234 def FCC_UL : FCC_VAL<19>; // Unordered or Less
235 def FCC_LG : FCC_VAL<18>; // Less or Greater
236 def FCC_NE : FCC_VAL<17>; // Not Equal
237 def FCC_E : FCC_VAL<25>; // Equal
238 def FCC_UE : FCC_VAL<24>; // Unordered or Equal
239 def FCC_GE : FCC_VAL<25>; // Greater or Equal
240 def FCC_UGE : FCC_VAL<26>; // Unordered or Greater or Equal
241 def FCC_LE : FCC_VAL<27>; // Less or Equal
242 def FCC_ULE : FCC_VAL<28>; // Unordered or Less or Equal
243 def FCC_O : FCC_VAL<29>; // Ordered
245 //===----------------------------------------------------------------------===//
246 // Instruction Class Templates
247 //===----------------------------------------------------------------------===//
249 /// F3_12 multiclass - Define a normal F3_1/F3_2 pattern in one shot.
250 multiclass F3_12<string OpcStr, bits<6> Op3Val, SDNode OpNode,
251 RegisterClass RC, ValueType Ty, Operand immOp> {
252 def rr : F3_1<2, Op3Val,
253 (outs RC:$rd), (ins RC:$rs1, RC:$rs2),
254 !strconcat(OpcStr, " $rs1, $rs2, $rd"),
255 [(set Ty:$rd, (OpNode Ty:$rs1, Ty:$rs2))]>;
256 def ri : F3_2<2, Op3Val,
257 (outs RC:$rd), (ins RC:$rs1, immOp:$simm13),
258 !strconcat(OpcStr, " $rs1, $simm13, $rd"),
259 [(set Ty:$rd, (OpNode Ty:$rs1, (Ty simm13:$simm13)))]>;
262 /// F3_12np multiclass - Define a normal F3_1/F3_2 pattern in one shot, with no
264 multiclass F3_12np<string OpcStr, bits<6> Op3Val> {
265 def rr : F3_1<2, Op3Val,
266 (outs IntRegs:$rd), (ins IntRegs:$rs1, IntRegs:$rs2),
267 !strconcat(OpcStr, " $rs1, $rs2, $rd"), []>;
268 def ri : F3_2<2, Op3Val,
269 (outs IntRegs:$rd), (ins IntRegs:$rs1, simm13Op:$simm13),
270 !strconcat(OpcStr, " $rs1, $simm13, $rd"), []>;
273 // Load multiclass - Define both Reg+Reg/Reg+Imm patterns in one shot.
274 multiclass Load<string OpcStr, bits<6> Op3Val, SDPatternOperator OpNode,
275 RegisterClass RC, ValueType Ty> {
276 def rr : F3_1<3, Op3Val,
277 (outs RC:$dst), (ins MEMrr:$addr),
278 !strconcat(OpcStr, " [$addr], $dst"),
279 [(set Ty:$dst, (OpNode ADDRrr:$addr))]>;
280 def ri : F3_2<3, Op3Val,
281 (outs RC:$dst), (ins MEMri:$addr),
282 !strconcat(OpcStr, " [$addr], $dst"),
283 [(set Ty:$dst, (OpNode ADDRri:$addr))]>;
286 // TODO: Instructions of the LoadASI class are currently asm only; hooking up
287 // CodeGen's address spaces to use these is a future task.
288 class LoadASI<string OpcStr, bits<6> Op3Val, SDPatternOperator OpNode,
289 RegisterClass RC, ValueType Ty> :
290 F3_1_asi<3, Op3Val, (outs RC:$dst), (ins MEMrr:$addr, i8imm:$asi),
291 !strconcat(OpcStr, "a [$addr] $asi, $dst"),
294 // LoadA multiclass - As above, but also define alternate address space variant
295 multiclass LoadA<string OpcStr, bits<6> Op3Val, bits<6> LoadAOp3Val,
296 SDPatternOperator OpNode, RegisterClass RC, ValueType Ty> :
297 Load<OpcStr, Op3Val, OpNode, RC, Ty> {
298 def Arr : LoadASI<OpcStr, LoadAOp3Val, OpNode, RC, Ty>;
301 // Store multiclass - Define both Reg+Reg/Reg+Imm patterns in one shot.
302 multiclass Store<string OpcStr, bits<6> Op3Val, SDPatternOperator OpNode,
303 RegisterClass RC, ValueType Ty> {
304 def rr : F3_1<3, Op3Val,
305 (outs), (ins MEMrr:$addr, RC:$rd),
306 !strconcat(OpcStr, " $rd, [$addr]"),
307 [(OpNode Ty:$rd, ADDRrr:$addr)]>;
308 def ri : F3_2<3, Op3Val,
309 (outs), (ins MEMri:$addr, RC:$rd),
310 !strconcat(OpcStr, " $rd, [$addr]"),
311 [(OpNode Ty:$rd, ADDRri:$addr)]>;
314 // TODO: Instructions of the StoreASI class are currently asm only; hooking up
315 // CodeGen's address spaces to use these is a future task.
316 class StoreASI<string OpcStr, bits<6> Op3Val,
317 SDPatternOperator OpNode, RegisterClass RC, ValueType Ty> :
318 F3_1_asi<3, Op3Val, (outs), (ins MEMrr:$addr, RC:$rd, i8imm:$asi),
319 !strconcat(OpcStr, "a $rd, [$addr] $asi"),
322 multiclass StoreA<string OpcStr, bits<6> Op3Val, bits<6> StoreAOp3Val,
323 SDPatternOperator OpNode, RegisterClass RC, ValueType Ty> :
324 Store<OpcStr, Op3Val, OpNode, RC, Ty> {
325 def Arr : StoreASI<OpcStr, StoreAOp3Val, OpNode, RC, Ty>;
328 //===----------------------------------------------------------------------===//
330 //===----------------------------------------------------------------------===//
332 // Pseudo instructions.
333 class Pseudo<dag outs, dag ins, string asmstr, list<dag> pattern>
334 : InstSP<outs, ins, asmstr, pattern> {
335 let isCodeGenOnly = 1;
341 def GETPCX : Pseudo<(outs getPCX:$getpcseq), (ins), "$getpcseq", [] >;
344 let Defs = [O6], Uses = [O6] in {
345 def ADJCALLSTACKDOWN : Pseudo<(outs), (ins i32imm:$amt),
346 "!ADJCALLSTACKDOWN $amt",
347 [(callseq_start timm:$amt)]>;
348 def ADJCALLSTACKUP : Pseudo<(outs), (ins i32imm:$amt1, i32imm:$amt2),
349 "!ADJCALLSTACKUP $amt1",
350 [(callseq_end timm:$amt1, timm:$amt2)]>;
353 let hasSideEffects = 1, mayStore = 1 in {
354 let rd = 0, rs1 = 0, rs2 = 0 in
355 def FLUSHW : F3_1<0b10, 0b101011, (outs), (ins),
357 [(flushw)]>, Requires<[HasV9]>;
358 let rd = 0, rs1 = 1, simm13 = 3 in
359 def TA3 : F3_2<0b10, 0b111010, (outs), (ins),
364 // SELECT_CC_* - Used to implement the SELECT_CC DAG operation. Expanded after
365 // instruction selection into a branch sequence. This has to handle all
366 // permutations of selection between i32/f32/f64 on ICC and FCC.
367 // Expanded after instruction selection.
368 let Uses = [ICC], usesCustomInserter = 1 in {
369 def SELECT_CC_Int_ICC
370 : Pseudo<(outs IntRegs:$dst), (ins IntRegs:$T, IntRegs:$F, i32imm:$Cond),
371 "; SELECT_CC_Int_ICC PSEUDO!",
372 [(set i32:$dst, (SPselecticc i32:$T, i32:$F, imm:$Cond))]>;
374 : Pseudo<(outs FPRegs:$dst), (ins FPRegs:$T, FPRegs:$F, i32imm:$Cond),
375 "; SELECT_CC_FP_ICC PSEUDO!",
376 [(set f32:$dst, (SPselecticc f32:$T, f32:$F, imm:$Cond))]>;
378 def SELECT_CC_DFP_ICC
379 : Pseudo<(outs DFPRegs:$dst), (ins DFPRegs:$T, DFPRegs:$F, i32imm:$Cond),
380 "; SELECT_CC_DFP_ICC PSEUDO!",
381 [(set f64:$dst, (SPselecticc f64:$T, f64:$F, imm:$Cond))]>;
383 def SELECT_CC_QFP_ICC
384 : Pseudo<(outs QFPRegs:$dst), (ins QFPRegs:$T, QFPRegs:$F, i32imm:$Cond),
385 "; SELECT_CC_QFP_ICC PSEUDO!",
386 [(set f128:$dst, (SPselecticc f128:$T, f128:$F, imm:$Cond))]>;
389 let usesCustomInserter = 1, Uses = [FCC0] in {
391 def SELECT_CC_Int_FCC
392 : Pseudo<(outs IntRegs:$dst), (ins IntRegs:$T, IntRegs:$F, i32imm:$Cond),
393 "; SELECT_CC_Int_FCC PSEUDO!",
394 [(set i32:$dst, (SPselectfcc i32:$T, i32:$F, imm:$Cond))]>;
397 : Pseudo<(outs FPRegs:$dst), (ins FPRegs:$T, FPRegs:$F, i32imm:$Cond),
398 "; SELECT_CC_FP_FCC PSEUDO!",
399 [(set f32:$dst, (SPselectfcc f32:$T, f32:$F, imm:$Cond))]>;
400 def SELECT_CC_DFP_FCC
401 : Pseudo<(outs DFPRegs:$dst), (ins DFPRegs:$T, DFPRegs:$F, i32imm:$Cond),
402 "; SELECT_CC_DFP_FCC PSEUDO!",
403 [(set f64:$dst, (SPselectfcc f64:$T, f64:$F, imm:$Cond))]>;
404 def SELECT_CC_QFP_FCC
405 : Pseudo<(outs QFPRegs:$dst), (ins QFPRegs:$T, QFPRegs:$F, i32imm:$Cond),
406 "; SELECT_CC_QFP_FCC PSEUDO!",
407 [(set f128:$dst, (SPselectfcc f128:$T, f128:$F, imm:$Cond))]>;
410 // Section B.1 - Load Integer Instructions, p. 90
411 let DecoderMethod = "DecodeLoadInt" in {
412 defm LDSB : LoadA<"ldsb", 0b001001, 0b011001, sextloadi8, IntRegs, i32>;
413 defm LDSH : LoadA<"ldsh", 0b001010, 0b011010, sextloadi16, IntRegs, i32>;
414 defm LDUB : LoadA<"ldub", 0b000001, 0b010001, zextloadi8, IntRegs, i32>;
415 defm LDUH : LoadA<"lduh", 0b000010, 0b010010, zextloadi16, IntRegs, i32>;
416 defm LD : LoadA<"ld", 0b000000, 0b010000, load, IntRegs, i32>;
419 let DecoderMethod = "DecodeLoadIntPair" in
420 defm LDD : LoadA<"ldd", 0b000011, 0b010011, load, IntPair, v2i32>;
422 // Section B.2 - Load Floating-point Instructions, p. 92
423 let DecoderMethod = "DecodeLoadFP" in {
424 defm LDF : Load<"ld", 0b100000, load, FPRegs, f32>;
425 def LDFArr : LoadASI<"ld", 0b110000, load, FPRegs, f32>,
428 let DecoderMethod = "DecodeLoadDFP" in {
429 defm LDDF : Load<"ldd", 0b100011, load, DFPRegs, f64>;
430 def LDDFArr : LoadASI<"ldd", 0b110011, load, DFPRegs, f64>,
433 let DecoderMethod = "DecodeLoadQFP" in
434 defm LDQF : LoadA<"ldq", 0b100010, 0b110010, load, QFPRegs, f128>,
435 Requires<[HasV9, HasHardQuad]>;
437 // Section B.4 - Store Integer Instructions, p. 95
438 let DecoderMethod = "DecodeStoreInt" in {
439 defm STB : StoreA<"stb", 0b000101, 0b010101, truncstorei8, IntRegs, i32>;
440 defm STH : StoreA<"sth", 0b000110, 0b010110, truncstorei16, IntRegs, i32>;
441 defm ST : StoreA<"st", 0b000100, 0b010100, store, IntRegs, i32>;
444 let DecoderMethod = "DecodeStoreIntPair" in
445 defm STD : StoreA<"std", 0b000111, 0b010111, store, IntPair, v2i32>;
447 // Section B.5 - Store Floating-point Instructions, p. 97
448 let DecoderMethod = "DecodeStoreFP" in {
449 defm STF : Store<"st", 0b100100, store, FPRegs, f32>;
450 def STFArr : StoreASI<"st", 0b110100, store, FPRegs, f32>,
453 let DecoderMethod = "DecodeStoreDFP" in {
454 defm STDF : Store<"std", 0b100111, store, DFPRegs, f64>;
455 def STDFArr : StoreASI<"std", 0b110111, store, DFPRegs, f64>,
458 let DecoderMethod = "DecodeStoreQFP" in
459 defm STQF : StoreA<"stq", 0b100110, 0b110110, store, QFPRegs, f128>,
460 Requires<[HasV9, HasHardQuad]>;
462 // Section B.8 - SWAP Register with Memory Instruction
464 let Constraints = "$val = $dst", DecoderMethod = "DecodeSWAP" in {
465 def SWAPrr : F3_1<3, 0b001111,
466 (outs IntRegs:$dst), (ins MEMrr:$addr, IntRegs:$val),
467 "swap [$addr], $dst",
468 [(set i32:$dst, (atomic_swap_32 ADDRrr:$addr, i32:$val))]>;
469 def SWAPri : F3_2<3, 0b001111,
470 (outs IntRegs:$dst), (ins MEMri:$addr, IntRegs:$val),
471 "swap [$addr], $dst",
472 [(set i32:$dst, (atomic_swap_32 ADDRri:$addr, i32:$val))]>;
473 def SWAPArr : F3_1_asi<3, 0b011111,
474 (outs IntRegs:$dst), (ins MEMrr:$addr, i8imm:$asi, IntRegs:$val),
475 "swapa [$addr] $asi, $dst",
476 [/*FIXME: pattern?*/]>;
480 // Section B.9 - SETHI Instruction, p. 104
481 def SETHIi: F2_1<0b100,
482 (outs IntRegs:$rd), (ins i32imm:$imm22),
484 [(set i32:$rd, SETHIimm:$imm22)]>;
486 // Section B.10 - NOP Instruction, p. 105
487 // (It's a special case of SETHI)
488 let rd = 0, imm22 = 0 in
489 def NOP : F2_1<0b100, (outs), (ins), "nop", []>;
491 // Section B.11 - Logical Instructions, p. 106
492 defm AND : F3_12<"and", 0b000001, and, IntRegs, i32, simm13Op>;
494 def ANDNrr : F3_1<2, 0b000101,
495 (outs IntRegs:$rd), (ins IntRegs:$rs1, IntRegs:$rs2),
496 "andn $rs1, $rs2, $rd",
497 [(set i32:$rd, (and i32:$rs1, (not i32:$rs2)))]>;
498 def ANDNri : F3_2<2, 0b000101,
499 (outs IntRegs:$rd), (ins IntRegs:$rs1, simm13Op:$simm13),
500 "andn $rs1, $simm13, $rd", []>;
502 defm OR : F3_12<"or", 0b000010, or, IntRegs, i32, simm13Op>;
504 def ORNrr : F3_1<2, 0b000110,
505 (outs IntRegs:$rd), (ins IntRegs:$rs1, IntRegs:$rs2),
506 "orn $rs1, $rs2, $rd",
507 [(set i32:$rd, (or i32:$rs1, (not i32:$rs2)))]>;
508 def ORNri : F3_2<2, 0b000110,
509 (outs IntRegs:$rd), (ins IntRegs:$rs1, simm13Op:$simm13),
510 "orn $rs1, $simm13, $rd", []>;
511 defm XOR : F3_12<"xor", 0b000011, xor, IntRegs, i32, simm13Op>;
513 def XNORrr : F3_1<2, 0b000111,
514 (outs IntRegs:$rd), (ins IntRegs:$rs1, IntRegs:$rs2),
515 "xnor $rs1, $rs2, $rd",
516 [(set i32:$rd, (not (xor i32:$rs1, i32:$rs2)))]>;
517 def XNORri : F3_2<2, 0b000111,
518 (outs IntRegs:$rd), (ins IntRegs:$rs1, simm13Op:$simm13),
519 "xnor $rs1, $simm13, $rd", []>;
521 let Defs = [ICC] in {
522 defm ANDCC : F3_12np<"andcc", 0b010001>;
523 defm ANDNCC : F3_12np<"andncc", 0b010101>;
524 defm ORCC : F3_12np<"orcc", 0b010010>;
525 defm ORNCC : F3_12np<"orncc", 0b010110>;
526 defm XORCC : F3_12np<"xorcc", 0b010011>;
527 defm XNORCC : F3_12np<"xnorcc", 0b010111>;
530 // Section B.12 - Shift Instructions, p. 107
531 defm SLL : F3_12<"sll", 0b100101, shl, IntRegs, i32, simm13Op>;
532 defm SRL : F3_12<"srl", 0b100110, srl, IntRegs, i32, simm13Op>;
533 defm SRA : F3_12<"sra", 0b100111, sra, IntRegs, i32, simm13Op>;
535 // Section B.13 - Add Instructions, p. 108
536 defm ADD : F3_12<"add", 0b000000, add, IntRegs, i32, simm13Op>;
538 // "LEA" forms of add (patterns to make tblgen happy)
539 let Predicates = [Is32Bit], isCodeGenOnly = 1 in
540 def LEA_ADDri : F3_2<2, 0b000000,
541 (outs IntRegs:$dst), (ins MEMri:$addr),
542 "add ${addr:arith}, $dst",
543 [(set iPTR:$dst, ADDRri:$addr)]>;
546 defm ADDCC : F3_12<"addcc", 0b010000, addc, IntRegs, i32, simm13Op>;
549 defm ADDC : F3_12np<"addx", 0b001000>;
551 let Uses = [ICC], Defs = [ICC] in
552 defm ADDE : F3_12<"addxcc", 0b011000, adde, IntRegs, i32, simm13Op>;
554 // Section B.15 - Subtract Instructions, p. 110
555 defm SUB : F3_12 <"sub" , 0b000100, sub, IntRegs, i32, simm13Op>;
556 let Uses = [ICC], Defs = [ICC] in
557 defm SUBE : F3_12 <"subxcc" , 0b011100, sube, IntRegs, i32, simm13Op>;
560 defm SUBCC : F3_12 <"subcc", 0b010100, subc, IntRegs, i32, simm13Op>;
563 defm SUBC : F3_12np <"subx", 0b001100>;
565 // cmp (from Section A.3) is a specialized alias for subcc
566 let Defs = [ICC], rd = 0 in {
567 def CMPrr : F3_1<2, 0b010100,
568 (outs), (ins IntRegs:$rs1, IntRegs:$rs2),
570 [(SPcmpicc i32:$rs1, i32:$rs2)]>;
571 def CMPri : F3_2<2, 0b010100,
572 (outs), (ins IntRegs:$rs1, simm13Op:$simm13),
574 [(SPcmpicc i32:$rs1, (i32 simm13:$simm13))]>;
577 // Section B.18 - Multiply Instructions, p. 113
579 defm UMUL : F3_12np<"umul", 0b001010>;
580 defm SMUL : F3_12 <"smul", 0b001011, mul, IntRegs, i32, simm13Op>;
583 let Defs = [Y, ICC] in {
584 defm UMULCC : F3_12np<"umulcc", 0b011010>;
585 defm SMULCC : F3_12np<"smulcc", 0b011011>;
588 // Section B.19 - Divide Instructions, p. 115
589 let Uses = [Y], Defs = [Y] in {
590 defm UDIV : F3_12np<"udiv", 0b001110>;
591 defm SDIV : F3_12np<"sdiv", 0b001111>;
594 let Uses = [Y], Defs = [Y, ICC] in {
595 defm UDIVCC : F3_12np<"udivcc", 0b011110>;
596 defm SDIVCC : F3_12np<"sdivcc", 0b011111>;
599 // Section B.20 - SAVE and RESTORE, p. 117
600 defm SAVE : F3_12np<"save" , 0b111100>;
601 defm RESTORE : F3_12np<"restore", 0b111101>;
603 // Section B.21 - Branch on Integer Condition Codes Instructions, p. 119
605 // unconditional branch class.
606 class BranchAlways<dag ins, string asmstr, list<dag> pattern>
607 : F2_2<0b010, 0, (outs), ins, asmstr, pattern> {
609 let isTerminator = 1;
610 let hasDelaySlot = 1;
615 def BA : BranchAlways<(ins brtarget:$imm22), "ba $imm22", [(br bb:$imm22)]>;
618 let isBranch = 1, isTerminator = 1, hasDelaySlot = 1 in {
620 // conditional branch class:
621 class BranchSP<dag ins, string asmstr, list<dag> pattern>
622 : F2_2<0b010, 0, (outs), ins, asmstr, pattern>;
624 // conditional branch with annul class:
625 class BranchSPA<dag ins, string asmstr, list<dag> pattern>
626 : F2_2<0b010, 1, (outs), ins, asmstr, pattern>;
628 // Conditional branch class on %icc|%xcc with predication:
629 multiclass IPredBranch<string regstr, list<dag> CCPattern> {
630 def CC : F2_3<0b001, 0, 1, (outs), (ins bprtarget:$imm19, CCOp:$cond),
631 !strconcat("b$cond ", !strconcat(regstr, ", $imm19")),
633 def CCA : F2_3<0b001, 1, 1, (outs), (ins bprtarget:$imm19, CCOp:$cond),
634 !strconcat("b$cond,a ", !strconcat(regstr, ", $imm19")),
636 def CCNT : F2_3<0b001, 0, 0, (outs), (ins bprtarget:$imm19, CCOp:$cond),
637 !strconcat("b$cond,pn ", !strconcat(regstr, ", $imm19")),
639 def CCANT : F2_3<0b001, 1, 0, (outs), (ins bprtarget:$imm19, CCOp:$cond),
640 !strconcat("b$cond,a,pn ", !strconcat(regstr, ", $imm19")),
644 } // let isBranch = 1, isTerminator = 1, hasDelaySlot = 1
647 // Indirect branch instructions.
648 let isTerminator = 1, isBarrier = 1, hasDelaySlot = 1, isBranch =1,
649 isIndirectBranch = 1, rd = 0, isCodeGenOnly = 1 in {
650 def BINDrr : F3_1<2, 0b111000,
651 (outs), (ins MEMrr:$ptr),
653 [(brind ADDRrr:$ptr)]>;
654 def BINDri : F3_2<2, 0b111000,
655 (outs), (ins MEMri:$ptr),
657 [(brind ADDRri:$ptr)]>;
660 let Uses = [ICC] in {
661 def BCOND : BranchSP<(ins brtarget:$imm22, CCOp:$cond),
663 [(SPbricc bb:$imm22, imm:$cond)]>;
664 def BCONDA : BranchSPA<(ins brtarget:$imm22, CCOp:$cond),
665 "b$cond,a $imm22", []>;
667 let Predicates = [HasV9], cc = 0b00 in
668 defm BPI : IPredBranch<"%icc", []>;
671 // Section B.22 - Branch on Floating-point Condition Codes Instructions, p. 121
673 let isBranch = 1, isTerminator = 1, hasDelaySlot = 1 in {
675 // floating-point conditional branch class:
676 class FPBranchSP<dag ins, string asmstr, list<dag> pattern>
677 : F2_2<0b110, 0, (outs), ins, asmstr, pattern>;
679 // floating-point conditional branch with annul class:
680 class FPBranchSPA<dag ins, string asmstr, list<dag> pattern>
681 : F2_2<0b110, 1, (outs), ins, asmstr, pattern>;
683 // Conditional branch class on %fcc0-%fcc3 with predication:
684 multiclass FPredBranch {
685 def CC : F2_3<0b101, 0, 1, (outs), (ins bprtarget:$imm19, CCOp:$cond,
687 "fb$cond $cc, $imm19", []>;
688 def CCA : F2_3<0b101, 1, 1, (outs), (ins bprtarget:$imm19, CCOp:$cond,
690 "fb$cond,a $cc, $imm19", []>;
691 def CCNT : F2_3<0b101, 0, 0, (outs), (ins bprtarget:$imm19, CCOp:$cond,
693 "fb$cond,pn $cc, $imm19", []>;
694 def CCANT : F2_3<0b101, 1, 0, (outs), (ins bprtarget:$imm19, CCOp:$cond,
696 "fb$cond,a,pn $cc, $imm19", []>;
698 } // let isBranch = 1, isTerminator = 1, hasDelaySlot = 1
700 let Uses = [FCC0] in {
701 def FBCOND : FPBranchSP<(ins brtarget:$imm22, CCOp:$cond),
703 [(SPbrfcc bb:$imm22, imm:$cond)]>;
704 def FBCONDA : FPBranchSPA<(ins brtarget:$imm22, CCOp:$cond),
705 "fb$cond,a $imm22", []>;
708 let Predicates = [HasV9] in
709 defm BPF : FPredBranch;
712 // Section B.24 - Call and Link Instruction, p. 125
713 // This is the only Format 1 instruction
715 hasDelaySlot = 1, isCall = 1 in {
716 def CALL : InstSP<(outs), (ins calltarget:$disp, variable_ops),
720 let Inst{29-0} = disp;
723 // indirect calls: special cases of JMPL.
724 let isCodeGenOnly = 1, rd = 15 in {
725 def CALLrr : F3_1<2, 0b111000,
726 (outs), (ins MEMrr:$ptr, variable_ops),
728 [(call ADDRrr:$ptr)]>;
729 def CALLri : F3_2<2, 0b111000,
730 (outs), (ins MEMri:$ptr, variable_ops),
732 [(call ADDRri:$ptr)]>;
736 // Section B.25 - Jump and Link Instruction
739 let isTerminator = 1, hasDelaySlot = 1, isBarrier = 1,
740 DecoderMethod = "DecodeJMPL" in {
741 def JMPLrr: F3_1<2, 0b111000, (outs IntRegs:$dst), (ins MEMrr:$addr),
742 "jmpl $addr, $dst", []>;
743 def JMPLri: F3_2<2, 0b111000, (outs IntRegs:$dst), (ins MEMri:$addr),
744 "jmpl $addr, $dst", []>;
747 // Section A.3 - Synthetic Instructions, p. 85
748 // special cases of JMPL:
749 let isReturn = 1, isTerminator = 1, hasDelaySlot = 1, isBarrier = 1,
750 isCodeGenOnly = 1 in {
751 let rd = 0, rs1 = 15 in
752 def RETL: F3_2<2, 0b111000, (outs), (ins i32imm:$val),
753 "jmp %o7+$val", [(retflag simm13:$val)]>;
755 let rd = 0, rs1 = 31 in
756 def RET: F3_2<2, 0b111000, (outs), (ins i32imm:$val),
760 // Section B.26 - Return from Trap Instruction
761 let isReturn = 1, isTerminator = 1, hasDelaySlot = 1,
762 isBarrier = 1, rd = 0, DecoderMethod = "DecodeReturn" in {
763 def RETTrr : F3_1<2, 0b111001, (outs), (ins MEMrr:$addr),
765 def RETTri : F3_2<2, 0b111001, (outs), (ins MEMri:$addr),
770 // Section B.27 - Trap on Integer Condition Codes Instruction
771 multiclass TRAP<string regStr> {
772 def rr : TRAPSPrr<0b111010, (outs), (ins IntRegs:$rs1, IntRegs:$rs2,
774 !strconcat(!strconcat("t$cond ", regStr), ", $rs1 + $rs2"), []>;
775 def ri : TRAPSPri<0b111010, (outs), (ins IntRegs:$rs1, i32imm:$imm,
777 !strconcat(!strconcat("t$cond ", regStr), ", $rs1 + $imm"), []>;
780 let hasSideEffects = 1, Uses = [ICC], cc = 0b00 in
781 defm TICC : TRAP<"%icc">;
783 let isBarrier = 1, isTerminator = 1, rd = 0b01000, rs1 = 0, simm13 = 5 in
784 def TA5 : F3_2<0b10, 0b111010, (outs), (ins), "ta 5", [(trap)]>;
786 // Section B.28 - Read State Register Instructions
788 def RDASR : F3_1<2, 0b101000,
789 (outs IntRegs:$rd), (ins ASRRegs:$rs1),
792 // PSR, WIM, and TBR don't exist on the SparcV9, only the V8.
793 let Predicates = [HasNoV9] in {
794 let rs2 = 0, rs1 = 0, Uses=[PSR] in
795 def RDPSR : F3_1<2, 0b101001,
796 (outs IntRegs:$rd), (ins),
799 let rs2 = 0, rs1 = 0, Uses=[WIM] in
800 def RDWIM : F3_1<2, 0b101010,
801 (outs IntRegs:$rd), (ins),
804 let rs2 = 0, rs1 = 0, Uses=[TBR] in
805 def RDTBR : F3_1<2, 0b101011,
806 (outs IntRegs:$rd), (ins),
810 // Section B.29 - Write State Register Instructions
811 def WRASRrr : F3_1<2, 0b110000,
812 (outs ASRRegs:$rd), (ins IntRegs:$rs1, IntRegs:$rs2),
813 "wr $rs1, $rs2, $rd", []>;
814 def WRASRri : F3_2<2, 0b110000,
815 (outs ASRRegs:$rd), (ins IntRegs:$rs1, simm13Op:$simm13),
816 "wr $rs1, $simm13, $rd", []>;
818 // PSR, WIM, and TBR don't exist on the SparcV9, only the V8.
819 let Predicates = [HasNoV9] in {
820 let Defs = [PSR], rd=0 in {
821 def WRPSRrr : F3_1<2, 0b110001,
822 (outs), (ins IntRegs:$rs1, IntRegs:$rs2),
823 "wr $rs1, $rs2, %psr", []>;
824 def WRPSRri : F3_2<2, 0b110001,
825 (outs), (ins IntRegs:$rs1, simm13Op:$simm13),
826 "wr $rs1, $simm13, %psr", []>;
829 let Defs = [WIM], rd=0 in {
830 def WRWIMrr : F3_1<2, 0b110010,
831 (outs), (ins IntRegs:$rs1, IntRegs:$rs2),
832 "wr $rs1, $rs2, %wim", []>;
833 def WRWIMri : F3_2<2, 0b110010,
834 (outs), (ins IntRegs:$rs1, simm13Op:$simm13),
835 "wr $rs1, $simm13, %wim", []>;
838 let Defs = [TBR], rd=0 in {
839 def WRTBRrr : F3_1<2, 0b110011,
840 (outs), (ins IntRegs:$rs1, IntRegs:$rs2),
841 "wr $rs1, $rs2, %tbr", []>;
842 def WRTBRri : F3_2<2, 0b110011,
843 (outs), (ins IntRegs:$rs1, simm13Op:$simm13),
844 "wr $rs1, $simm13, %tbr", []>;
848 // Section B.30 - STBAR Instruction
849 let hasSideEffects = 1, rd = 0, rs1 = 0b01111, rs2 = 0 in
850 def STBAR : F3_1<2, 0b101000, (outs), (ins), "stbar", []>;
853 // Section B.31 - Unimplmented Instruction
855 def UNIMP : F2_1<0b000, (outs), (ins i32imm:$imm22),
858 // Section B.32 - Flush Instruction Memory
860 def FLUSHrr : F3_1<2, 0b111011, (outs), (ins MEMrr:$addr),
862 def FLUSHri : F3_2<2, 0b111011, (outs), (ins MEMri:$addr),
865 // The no-arg FLUSH is only here for the benefit of the InstAlias
866 // "flush", which cannot seem to use FLUSHrr, due to the inability
867 // to construct a MEMrr with fixed G0 registers.
868 let rs1 = 0, rs2 = 0 in
869 def FLUSH : F3_1<2, 0b111011, (outs), (ins), "flush %g0", []>;
872 // Section B.33 - Floating-point Operate (FPop) Instructions
874 // Convert Integer to Floating-point Instructions, p. 141
875 def FITOS : F3_3u<2, 0b110100, 0b011000100,
876 (outs FPRegs:$rd), (ins FPRegs:$rs2),
878 [(set FPRegs:$rd, (SPitof FPRegs:$rs2))]>;
879 def FITOD : F3_3u<2, 0b110100, 0b011001000,
880 (outs DFPRegs:$rd), (ins FPRegs:$rs2),
882 [(set DFPRegs:$rd, (SPitof FPRegs:$rs2))]>;
883 def FITOQ : F3_3u<2, 0b110100, 0b011001100,
884 (outs QFPRegs:$rd), (ins FPRegs:$rs2),
886 [(set QFPRegs:$rd, (SPitof FPRegs:$rs2))]>,
887 Requires<[HasHardQuad]>;
889 // Convert Floating-point to Integer Instructions, p. 142
890 def FSTOI : F3_3u<2, 0b110100, 0b011010001,
891 (outs FPRegs:$rd), (ins FPRegs:$rs2),
893 [(set FPRegs:$rd, (SPftoi FPRegs:$rs2))]>;
894 def FDTOI : F3_3u<2, 0b110100, 0b011010010,
895 (outs FPRegs:$rd), (ins DFPRegs:$rs2),
897 [(set FPRegs:$rd, (SPftoi DFPRegs:$rs2))]>;
898 def FQTOI : F3_3u<2, 0b110100, 0b011010011,
899 (outs FPRegs:$rd), (ins QFPRegs:$rs2),
901 [(set FPRegs:$rd, (SPftoi QFPRegs:$rs2))]>,
902 Requires<[HasHardQuad]>;
904 // Convert between Floating-point Formats Instructions, p. 143
905 def FSTOD : F3_3u<2, 0b110100, 0b011001001,
906 (outs DFPRegs:$rd), (ins FPRegs:$rs2),
908 [(set f64:$rd, (fextend f32:$rs2))]>;
909 def FSTOQ : F3_3u<2, 0b110100, 0b011001101,
910 (outs QFPRegs:$rd), (ins FPRegs:$rs2),
912 [(set f128:$rd, (fextend f32:$rs2))]>,
913 Requires<[HasHardQuad]>;
914 def FDTOS : F3_3u<2, 0b110100, 0b011000110,
915 (outs FPRegs:$rd), (ins DFPRegs:$rs2),
917 [(set f32:$rd, (fround f64:$rs2))]>;
918 def FDTOQ : F3_3u<2, 0b110100, 0b011001110,
919 (outs QFPRegs:$rd), (ins DFPRegs:$rs2),
921 [(set f128:$rd, (fextend f64:$rs2))]>,
922 Requires<[HasHardQuad]>;
923 def FQTOS : F3_3u<2, 0b110100, 0b011000111,
924 (outs FPRegs:$rd), (ins QFPRegs:$rs2),
926 [(set f32:$rd, (fround f128:$rs2))]>,
927 Requires<[HasHardQuad]>;
928 def FQTOD : F3_3u<2, 0b110100, 0b011001011,
929 (outs DFPRegs:$rd), (ins QFPRegs:$rs2),
931 [(set f64:$rd, (fround f128:$rs2))]>,
932 Requires<[HasHardQuad]>;
934 // Floating-point Move Instructions, p. 144
935 def FMOVS : F3_3u<2, 0b110100, 0b000000001,
936 (outs FPRegs:$rd), (ins FPRegs:$rs2),
937 "fmovs $rs2, $rd", []>;
938 def FNEGS : F3_3u<2, 0b110100, 0b000000101,
939 (outs FPRegs:$rd), (ins FPRegs:$rs2),
941 [(set f32:$rd, (fneg f32:$rs2))]>;
942 def FABSS : F3_3u<2, 0b110100, 0b000001001,
943 (outs FPRegs:$rd), (ins FPRegs:$rs2),
945 [(set f32:$rd, (fabs f32:$rs2))]>;
948 // Floating-point Square Root Instructions, p.145
949 def FSQRTS : F3_3u<2, 0b110100, 0b000101001,
950 (outs FPRegs:$rd), (ins FPRegs:$rs2),
952 [(set f32:$rd, (fsqrt f32:$rs2))]>;
953 def FSQRTD : F3_3u<2, 0b110100, 0b000101010,
954 (outs DFPRegs:$rd), (ins DFPRegs:$rs2),
956 [(set f64:$rd, (fsqrt f64:$rs2))]>;
957 def FSQRTQ : F3_3u<2, 0b110100, 0b000101011,
958 (outs QFPRegs:$rd), (ins QFPRegs:$rs2),
960 [(set f128:$rd, (fsqrt f128:$rs2))]>,
961 Requires<[HasHardQuad]>;
965 // Floating-point Add and Subtract Instructions, p. 146
966 def FADDS : F3_3<2, 0b110100, 0b001000001,
967 (outs FPRegs:$rd), (ins FPRegs:$rs1, FPRegs:$rs2),
968 "fadds $rs1, $rs2, $rd",
969 [(set f32:$rd, (fadd f32:$rs1, f32:$rs2))]>;
970 def FADDD : F3_3<2, 0b110100, 0b001000010,
971 (outs DFPRegs:$rd), (ins DFPRegs:$rs1, DFPRegs:$rs2),
972 "faddd $rs1, $rs2, $rd",
973 [(set f64:$rd, (fadd f64:$rs1, f64:$rs2))]>;
974 def FADDQ : F3_3<2, 0b110100, 0b001000011,
975 (outs QFPRegs:$rd), (ins QFPRegs:$rs1, QFPRegs:$rs2),
976 "faddq $rs1, $rs2, $rd",
977 [(set f128:$rd, (fadd f128:$rs1, f128:$rs2))]>,
978 Requires<[HasHardQuad]>;
980 def FSUBS : F3_3<2, 0b110100, 0b001000101,
981 (outs FPRegs:$rd), (ins FPRegs:$rs1, FPRegs:$rs2),
982 "fsubs $rs1, $rs2, $rd",
983 [(set f32:$rd, (fsub f32:$rs1, f32:$rs2))]>;
984 def FSUBD : F3_3<2, 0b110100, 0b001000110,
985 (outs DFPRegs:$rd), (ins DFPRegs:$rs1, DFPRegs:$rs2),
986 "fsubd $rs1, $rs2, $rd",
987 [(set f64:$rd, (fsub f64:$rs1, f64:$rs2))]>;
988 def FSUBQ : F3_3<2, 0b110100, 0b001000111,
989 (outs QFPRegs:$rd), (ins QFPRegs:$rs1, QFPRegs:$rs2),
990 "fsubq $rs1, $rs2, $rd",
991 [(set f128:$rd, (fsub f128:$rs1, f128:$rs2))]>,
992 Requires<[HasHardQuad]>;
995 // Floating-point Multiply and Divide Instructions, p. 147
996 def FMULS : F3_3<2, 0b110100, 0b001001001,
997 (outs FPRegs:$rd), (ins FPRegs:$rs1, FPRegs:$rs2),
998 "fmuls $rs1, $rs2, $rd",
999 [(set f32:$rd, (fmul f32:$rs1, f32:$rs2))]>;
1000 def FMULD : F3_3<2, 0b110100, 0b001001010,
1001 (outs DFPRegs:$rd), (ins DFPRegs:$rs1, DFPRegs:$rs2),
1002 "fmuld $rs1, $rs2, $rd",
1003 [(set f64:$rd, (fmul f64:$rs1, f64:$rs2))]>;
1004 def FMULQ : F3_3<2, 0b110100, 0b001001011,
1005 (outs QFPRegs:$rd), (ins QFPRegs:$rs1, QFPRegs:$rs2),
1006 "fmulq $rs1, $rs2, $rd",
1007 [(set f128:$rd, (fmul f128:$rs1, f128:$rs2))]>,
1008 Requires<[HasHardQuad]>;
1010 def FSMULD : F3_3<2, 0b110100, 0b001101001,
1011 (outs DFPRegs:$rd), (ins FPRegs:$rs1, FPRegs:$rs2),
1012 "fsmuld $rs1, $rs2, $rd",
1013 [(set f64:$rd, (fmul (fextend f32:$rs1),
1014 (fextend f32:$rs2)))]>;
1015 def FDMULQ : F3_3<2, 0b110100, 0b001101110,
1016 (outs QFPRegs:$rd), (ins DFPRegs:$rs1, DFPRegs:$rs2),
1017 "fdmulq $rs1, $rs2, $rd",
1018 [(set f128:$rd, (fmul (fextend f64:$rs1),
1019 (fextend f64:$rs2)))]>,
1020 Requires<[HasHardQuad]>;
1022 def FDIVS : F3_3<2, 0b110100, 0b001001101,
1023 (outs FPRegs:$rd), (ins FPRegs:$rs1, FPRegs:$rs2),
1024 "fdivs $rs1, $rs2, $rd",
1025 [(set f32:$rd, (fdiv f32:$rs1, f32:$rs2))]>;
1026 def FDIVD : F3_3<2, 0b110100, 0b001001110,
1027 (outs DFPRegs:$rd), (ins DFPRegs:$rs1, DFPRegs:$rs2),
1028 "fdivd $rs1, $rs2, $rd",
1029 [(set f64:$rd, (fdiv f64:$rs1, f64:$rs2))]>;
1030 def FDIVQ : F3_3<2, 0b110100, 0b001001111,
1031 (outs QFPRegs:$rd), (ins QFPRegs:$rs1, QFPRegs:$rs2),
1032 "fdivq $rs1, $rs2, $rd",
1033 [(set f128:$rd, (fdiv f128:$rs1, f128:$rs2))]>,
1034 Requires<[HasHardQuad]>;
1036 // Floating-point Compare Instructions, p. 148
1037 // Note: the 2nd template arg is different for these guys.
1038 // Note 2: the result of a FCMP is not available until the 2nd cycle
1039 // after the instr is retired, but there is no interlock in Sparc V8.
1040 // This behavior is modeled with a forced noop after the instruction in
1043 let Defs = [FCC0], rd = 0, isCodeGenOnly = 1 in {
1044 def FCMPS : F3_3c<2, 0b110101, 0b001010001,
1045 (outs), (ins FPRegs:$rs1, FPRegs:$rs2),
1047 [(SPcmpfcc f32:$rs1, f32:$rs2)]>;
1048 def FCMPD : F3_3c<2, 0b110101, 0b001010010,
1049 (outs), (ins DFPRegs:$rs1, DFPRegs:$rs2),
1051 [(SPcmpfcc f64:$rs1, f64:$rs2)]>;
1052 def FCMPQ : F3_3c<2, 0b110101, 0b001010011,
1053 (outs), (ins QFPRegs:$rs1, QFPRegs:$rs2),
1055 [(SPcmpfcc f128:$rs1, f128:$rs2)]>,
1056 Requires<[HasHardQuad]>;
1059 //===----------------------------------------------------------------------===//
1060 // Instructions for Thread Local Storage(TLS).
1061 //===----------------------------------------------------------------------===//
1062 let isCodeGenOnly = 1, isAsmParserOnly = 1 in {
1063 def TLS_ADDrr : F3_1<2, 0b000000,
1065 (ins IntRegs:$rs1, IntRegs:$rs2, TLSSym:$sym),
1066 "add $rs1, $rs2, $rd, $sym",
1068 (tlsadd i32:$rs1, i32:$rs2, tglobaltlsaddr:$sym))]>;
1071 def TLS_LDrr : F3_1<3, 0b000000,
1072 (outs IntRegs:$dst), (ins MEMrr:$addr, TLSSym:$sym),
1073 "ld [$addr], $dst, $sym",
1075 (tlsld ADDRrr:$addr, tglobaltlsaddr:$sym))]>;
1077 let Uses = [O6], isCall = 1, hasDelaySlot = 1 in
1078 def TLS_CALL : InstSP<(outs),
1079 (ins calltarget:$disp, TLSSym:$sym, variable_ops),
1081 [(tlscall texternalsym:$disp, tglobaltlsaddr:$sym)]> {
1084 let Inst{29-0} = disp;
1088 //===----------------------------------------------------------------------===//
1090 //===----------------------------------------------------------------------===//
1092 // V9 Conditional Moves.
1093 let Predicates = [HasV9], Constraints = "$f = $rd" in {
1094 // Move Integer Register on Condition (MOVcc) p. 194 of the V9 manual.
1095 let Uses = [ICC], intcc = 1, cc = 0b00 in {
1097 : F4_1<0b101100, (outs IntRegs:$rd),
1098 (ins IntRegs:$rs2, IntRegs:$f, CCOp:$cond),
1099 "mov$cond %icc, $rs2, $rd",
1100 [(set i32:$rd, (SPselecticc i32:$rs2, i32:$f, imm:$cond))]>;
1103 : F4_2<0b101100, (outs IntRegs:$rd),
1104 (ins i32imm:$simm11, IntRegs:$f, CCOp:$cond),
1105 "mov$cond %icc, $simm11, $rd",
1107 (SPselecticc simm11:$simm11, i32:$f, imm:$cond))]>;
1110 let Uses = [FCC0], intcc = 0, cc = 0b00 in {
1112 : F4_1<0b101100, (outs IntRegs:$rd),
1113 (ins IntRegs:$rs2, IntRegs:$f, CCOp:$cond),
1114 "mov$cond %fcc0, $rs2, $rd",
1115 [(set i32:$rd, (SPselectfcc i32:$rs2, i32:$f, imm:$cond))]>;
1117 : F4_2<0b101100, (outs IntRegs:$rd),
1118 (ins i32imm:$simm11, IntRegs:$f, CCOp:$cond),
1119 "mov$cond %fcc0, $simm11, $rd",
1121 (SPselectfcc simm11:$simm11, i32:$f, imm:$cond))]>;
1124 let Uses = [ICC], intcc = 1, opf_cc = 0b00 in {
1126 : F4_3<0b110101, 0b000001, (outs FPRegs:$rd),
1127 (ins FPRegs:$rs2, FPRegs:$f, CCOp:$cond),
1128 "fmovs$cond %icc, $rs2, $rd",
1129 [(set f32:$rd, (SPselecticc f32:$rs2, f32:$f, imm:$cond))]>;
1131 : F4_3<0b110101, 0b000010, (outs DFPRegs:$rd),
1132 (ins DFPRegs:$rs2, DFPRegs:$f, CCOp:$cond),
1133 "fmovd$cond %icc, $rs2, $rd",
1134 [(set f64:$rd, (SPselecticc f64:$rs2, f64:$f, imm:$cond))]>;
1136 : F4_3<0b110101, 0b000011, (outs QFPRegs:$rd),
1137 (ins QFPRegs:$rs2, QFPRegs:$f, CCOp:$cond),
1138 "fmovq$cond %icc, $rs2, $rd",
1139 [(set f128:$rd, (SPselecticc f128:$rs2, f128:$f, imm:$cond))]>,
1140 Requires<[HasHardQuad]>;
1143 let Uses = [FCC0], intcc = 0, opf_cc = 0b00 in {
1145 : F4_3<0b110101, 0b000001, (outs FPRegs:$rd),
1146 (ins FPRegs:$rs2, FPRegs:$f, CCOp:$cond),
1147 "fmovs$cond %fcc0, $rs2, $rd",
1148 [(set f32:$rd, (SPselectfcc f32:$rs2, f32:$f, imm:$cond))]>;
1150 : F4_3<0b110101, 0b000010, (outs DFPRegs:$rd),
1151 (ins DFPRegs:$rs2, DFPRegs:$f, CCOp:$cond),
1152 "fmovd$cond %fcc0, $rs2, $rd",
1153 [(set f64:$rd, (SPselectfcc f64:$rs2, f64:$f, imm:$cond))]>;
1155 : F4_3<0b110101, 0b000011, (outs QFPRegs:$rd),
1156 (ins QFPRegs:$rs2, QFPRegs:$f, CCOp:$cond),
1157 "fmovq$cond %fcc0, $rs2, $rd",
1158 [(set f128:$rd, (SPselectfcc f128:$rs2, f128:$f, imm:$cond))]>,
1159 Requires<[HasHardQuad]>;
1164 // Floating-Point Move Instructions, p. 164 of the V9 manual.
1165 let Predicates = [HasV9] in {
1166 def FMOVD : F3_3u<2, 0b110100, 0b000000010,
1167 (outs DFPRegs:$rd), (ins DFPRegs:$rs2),
1168 "fmovd $rs2, $rd", []>;
1169 def FMOVQ : F3_3u<2, 0b110100, 0b000000011,
1170 (outs QFPRegs:$rd), (ins QFPRegs:$rs2),
1171 "fmovq $rs2, $rd", []>,
1172 Requires<[HasHardQuad]>;
1173 def FNEGD : F3_3u<2, 0b110100, 0b000000110,
1174 (outs DFPRegs:$rd), (ins DFPRegs:$rs2),
1176 [(set f64:$rd, (fneg f64:$rs2))]>;
1177 def FNEGQ : F3_3u<2, 0b110100, 0b000000111,
1178 (outs QFPRegs:$rd), (ins QFPRegs:$rs2),
1180 [(set f128:$rd, (fneg f128:$rs2))]>,
1181 Requires<[HasHardQuad]>;
1182 def FABSD : F3_3u<2, 0b110100, 0b000001010,
1183 (outs DFPRegs:$rd), (ins DFPRegs:$rs2),
1185 [(set f64:$rd, (fabs f64:$rs2))]>;
1186 def FABSQ : F3_3u<2, 0b110100, 0b000001011,
1187 (outs QFPRegs:$rd), (ins QFPRegs:$rs2),
1189 [(set f128:$rd, (fabs f128:$rs2))]>,
1190 Requires<[HasHardQuad]>;
1193 // Floating-point compare instruction with %fcc0-%fcc3.
1194 def V9FCMPS : F3_3c<2, 0b110101, 0b001010001,
1195 (outs FCCRegs:$rd), (ins FPRegs:$rs1, FPRegs:$rs2),
1196 "fcmps $rd, $rs1, $rs2", []>;
1197 def V9FCMPD : F3_3c<2, 0b110101, 0b001010010,
1198 (outs FCCRegs:$rd), (ins DFPRegs:$rs1, DFPRegs:$rs2),
1199 "fcmpd $rd, $rs1, $rs2", []>;
1200 def V9FCMPQ : F3_3c<2, 0b110101, 0b001010011,
1201 (outs FCCRegs:$rd), (ins QFPRegs:$rs1, QFPRegs:$rs2),
1202 "fcmpq $rd, $rs1, $rs2", []>,
1203 Requires<[HasHardQuad]>;
1205 let hasSideEffects = 1 in {
1206 def V9FCMPES : F3_3c<2, 0b110101, 0b001010101,
1207 (outs FCCRegs:$rd), (ins FPRegs:$rs1, FPRegs:$rs2),
1208 "fcmpes $rd, $rs1, $rs2", []>;
1209 def V9FCMPED : F3_3c<2, 0b110101, 0b001010110,
1210 (outs FCCRegs:$rd), (ins DFPRegs:$rs1, DFPRegs:$rs2),
1211 "fcmped $rd, $rs1, $rs2", []>;
1212 def V9FCMPEQ : F3_3c<2, 0b110101, 0b001010111,
1213 (outs FCCRegs:$rd), (ins QFPRegs:$rs1, QFPRegs:$rs2),
1214 "fcmpeq $rd, $rs1, $rs2", []>,
1215 Requires<[HasHardQuad]>;
1218 // Floating point conditional move instrucitons with %fcc0-%fcc3.
1219 let Predicates = [HasV9] in {
1220 let Constraints = "$f = $rd", intcc = 0 in {
1222 : F4_1<0b101100, (outs IntRegs:$rd),
1223 (ins FCCRegs:$cc, IntRegs:$rs2, IntRegs:$f, CCOp:$cond),
1224 "mov$cond $cc, $rs2, $rd", []>;
1226 : F4_2<0b101100, (outs IntRegs:$rd),
1227 (ins FCCRegs:$cc, i32imm:$simm11, IntRegs:$f, CCOp:$cond),
1228 "mov$cond $cc, $simm11, $rd", []>;
1230 : F4_3<0b110101, 0b000001, (outs FPRegs:$rd),
1231 (ins FCCRegs:$opf_cc, FPRegs:$rs2, FPRegs:$f, CCOp:$cond),
1232 "fmovs$cond $opf_cc, $rs2, $rd", []>;
1234 : F4_3<0b110101, 0b000010, (outs DFPRegs:$rd),
1235 (ins FCCRegs:$opf_cc, DFPRegs:$rs2, DFPRegs:$f, CCOp:$cond),
1236 "fmovd$cond $opf_cc, $rs2, $rd", []>;
1238 : F4_3<0b110101, 0b000011, (outs QFPRegs:$rd),
1239 (ins FCCRegs:$opf_cc, QFPRegs:$rs2, QFPRegs:$f, CCOp:$cond),
1240 "fmovq$cond $opf_cc, $rs2, $rd", []>,
1241 Requires<[HasHardQuad]>;
1242 } // Constraints = "$f = $rd", ...
1243 } // let Predicates = [hasV9]
1246 // POPCrr - This does a ctpop of a 64-bit register. As such, we have to clear
1247 // the top 32-bits before using it. To do this clearing, we use a SRLri X,0.
1249 def POPCrr : F3_1<2, 0b101110,
1250 (outs IntRegs:$rd), (ins IntRegs:$rs2),
1251 "popc $rs2, $rd", []>, Requires<[HasV9]>;
1252 def : Pat<(ctpop i32:$src),
1253 (POPCrr (SRLri $src, 0))>;
1255 let Predicates = [HasV9], hasSideEffects = 1, rd = 0, rs1 = 0b01111 in
1256 def MEMBARi : F3_2<2, 0b101000, (outs), (ins simm13Op:$simm13),
1257 "membar $simm13", []>;
1259 // TODO: Should add a CASArr variant. In fact, the CAS instruction,
1260 // unlike other instructions, only comes in a form which requires an
1261 // ASI be provided. The ASI value hardcoded here is ASI_PRIMARY, the
1262 // default unprivileged ASI for SparcV9. (Also of note: some modern
1263 // SparcV8 implementations provide CASA as an extension, but require
1264 // the use of SparcV8's default ASI, 0xA ("User Data") instead.)
1265 let Predicates = [HasV9], Constraints = "$swap = $rd", asi = 0b10000000 in
1266 def CASrr: F3_1_asi<3, 0b111100,
1267 (outs IntRegs:$rd), (ins IntRegs:$rs1, IntRegs:$rs2,
1269 "cas [$rs1], $rs2, $rd",
1271 (atomic_cmp_swap iPTR:$rs1, i32:$rs2, i32:$swap))]>;
1273 let Defs = [ICC] in {
1274 defm TADDCC : F3_12np<"taddcc", 0b100000>;
1275 defm TSUBCC : F3_12np<"tsubcc", 0b100001>;
1277 let hasSideEffects = 1 in {
1278 defm TADDCCTV : F3_12np<"taddcctv", 0b100010>;
1279 defm TSUBCCTV : F3_12np<"tsubcctv", 0b100011>;
1283 //===----------------------------------------------------------------------===//
1284 // Non-Instruction Patterns
1285 //===----------------------------------------------------------------------===//
1287 // Small immediates.
1288 def : Pat<(i32 simm13:$val),
1289 (ORri (i32 G0), imm:$val)>;
1290 // Arbitrary immediates.
1291 def : Pat<(i32 imm:$val),
1292 (ORri (SETHIi (HI22 imm:$val)), (LO10 imm:$val))>;
1295 // Global addresses, constant pool entries
1296 let Predicates = [Is32Bit] in {
1298 def : Pat<(SPhi tglobaladdr:$in), (SETHIi tglobaladdr:$in)>;
1299 def : Pat<(SPlo tglobaladdr:$in), (ORri (i32 G0), tglobaladdr:$in)>;
1300 def : Pat<(SPhi tconstpool:$in), (SETHIi tconstpool:$in)>;
1301 def : Pat<(SPlo tconstpool:$in), (ORri (i32 G0), tconstpool:$in)>;
1303 // GlobalTLS addresses
1304 def : Pat<(SPhi tglobaltlsaddr:$in), (SETHIi tglobaltlsaddr:$in)>;
1305 def : Pat<(SPlo tglobaltlsaddr:$in), (ORri (i32 G0), tglobaltlsaddr:$in)>;
1306 def : Pat<(add (SPhi tglobaltlsaddr:$in1), (SPlo tglobaltlsaddr:$in2)),
1307 (ADDri (SETHIi tglobaltlsaddr:$in1), (tglobaltlsaddr:$in2))>;
1308 def : Pat<(xor (SPhi tglobaltlsaddr:$in1), (SPlo tglobaltlsaddr:$in2)),
1309 (XORri (SETHIi tglobaltlsaddr:$in1), (tglobaltlsaddr:$in2))>;
1312 def : Pat<(SPhi tblockaddress:$in), (SETHIi tblockaddress:$in)>;
1313 def : Pat<(SPlo tblockaddress:$in), (ORri (i32 G0), tblockaddress:$in)>;
1315 // Add reg, lo. This is used when taking the addr of a global/constpool entry.
1316 def : Pat<(add iPTR:$r, (SPlo tglobaladdr:$in)), (ADDri $r, tglobaladdr:$in)>;
1317 def : Pat<(add iPTR:$r, (SPlo tconstpool:$in)), (ADDri $r, tconstpool:$in)>;
1318 def : Pat<(add iPTR:$r, (SPlo tblockaddress:$in)),
1319 (ADDri $r, tblockaddress:$in)>;
1323 def : Pat<(call tglobaladdr:$dst),
1324 (CALL tglobaladdr:$dst)>;
1325 def : Pat<(call texternalsym:$dst),
1326 (CALL texternalsym:$dst)>;
1328 // Map integer extload's to zextloads.
1329 def : Pat<(i32 (extloadi1 ADDRrr:$src)), (LDUBrr ADDRrr:$src)>;
1330 def : Pat<(i32 (extloadi1 ADDRri:$src)), (LDUBri ADDRri:$src)>;
1331 def : Pat<(i32 (extloadi8 ADDRrr:$src)), (LDUBrr ADDRrr:$src)>;
1332 def : Pat<(i32 (extloadi8 ADDRri:$src)), (LDUBri ADDRri:$src)>;
1333 def : Pat<(i32 (extloadi16 ADDRrr:$src)), (LDUHrr ADDRrr:$src)>;
1334 def : Pat<(i32 (extloadi16 ADDRri:$src)), (LDUHri ADDRri:$src)>;
1336 // zextload bool -> zextload byte
1337 def : Pat<(i32 (zextloadi1 ADDRrr:$src)), (LDUBrr ADDRrr:$src)>;
1338 def : Pat<(i32 (zextloadi1 ADDRri:$src)), (LDUBri ADDRri:$src)>;
1340 // store 0, addr -> store %g0, addr
1341 def : Pat<(store (i32 0), ADDRrr:$dst), (STrr ADDRrr:$dst, (i32 G0))>;
1342 def : Pat<(store (i32 0), ADDRri:$dst), (STri ADDRri:$dst, (i32 G0))>;
1344 // store bar for all atomic_fence in V8.
1345 let Predicates = [HasNoV9] in
1346 def : Pat<(atomic_fence imm, imm), (STBAR)>;
1348 // atomic_load_32 addr -> load addr
1349 def : Pat<(i32 (atomic_load ADDRrr:$src)), (LDrr ADDRrr:$src)>;
1350 def : Pat<(i32 (atomic_load ADDRri:$src)), (LDri ADDRri:$src)>;
1352 // atomic_store_32 val, addr -> store val, addr
1353 def : Pat<(atomic_store ADDRrr:$dst, i32:$val), (STrr ADDRrr:$dst, $val)>;
1354 def : Pat<(atomic_store ADDRri:$dst, i32:$val), (STri ADDRri:$dst, $val)>;
1357 def : Pat<(vector_extract (v2i32 IntPair:$Rn), 0),
1358 (i32 (EXTRACT_SUBREG IntPair:$Rn, sub_even))>;
1359 def : Pat<(vector_extract (v2i32 IntPair:$Rn), 1),
1360 (i32 (EXTRACT_SUBREG IntPair:$Rn, sub_odd))>;
1363 def : Pat<(build_vector (i32 IntRegs:$a1), (i32 IntRegs:$a2)),
1365 (INSERT_SUBREG (v2i32 (IMPLICIT_DEF)), (i32 IntRegs:$a1), sub_even),
1366 (i32 IntRegs:$a2), sub_odd)>;
1369 include "SparcInstr64Bit.td"
1370 include "SparcInstrVIS.td"
1371 include "SparcInstrAliases.td"