1 //===- SparcV8Instrs.td - Target Description for SparcV8 Target -----------===//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by the LLVM research group and is distributed under
6 // the University of Illinois Open Source License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the SparcV8 instructions in TableGen format.
12 //===----------------------------------------------------------------------===//
14 //===----------------------------------------------------------------------===//
15 // Instruction format superclass
16 //===----------------------------------------------------------------------===//
18 class InstV8 : Instruction { // SparcV8 instruction baseline
24 let Inst{31-30} = op; // Top two bits are the 'op' field
26 // Bit attributes specific to SparcV8 instructions
27 bit isPasi = 0; // Does this instruction affect an alternate addr space?
28 bit isPrivileged = 0; // Is this a privileged instruction?
31 include "SparcV8InstrFormats.td"
33 //===----------------------------------------------------------------------===//
34 // Instruction Pattern Stuff
35 //===----------------------------------------------------------------------===//
37 def simm13 : PatLeaf<(imm), [{
38 // simm13 predicate - True if the imm fits in a 13-bit sign extended field.
39 return (((int)N->getValue() << (32-13)) >> (32-13)) == (int)N->getValue();
42 def LO10 : SDNodeXForm<imm, [{
43 return CurDAG->getTargetConstant((unsigned)N->getValue() & 1023, MVT::i32);
46 def HI22 : SDNodeXForm<imm, [{
47 // Transformation function: shift the immediate value down into the low bits.
48 return CurDAG->getTargetConstant((unsigned)N->getValue() >> 10, MVT::i32);
51 def SETHIimm : PatLeaf<(imm), [{
52 return (((unsigned)N->getValue() >> 10) << 10) == (unsigned)N->getValue();
56 def ADDRrr : ComplexPattern<i32, 2, "SelectADDRrr", []>;
57 def ADDRri : ComplexPattern<i32, 2, "SelectADDRri", []>;
60 def MEMrr : Operand<i32> {
61 let PrintMethod = "printMemOperand";
62 let NumMIOperands = 2;
63 let MIOperandInfo = (ops IntRegs, IntRegs);
65 def MEMri : Operand<i32> {
66 let PrintMethod = "printMemOperand";
67 let NumMIOperands = 2;
68 let MIOperandInfo = (ops IntRegs, i32imm);
71 // Branch targets have OtherVT type.
72 def brtarget : Operand<OtherVT>;
75 SDTypeProfile<1, 2, [SDTCisVT<0, FlagVT>, SDTCisInt<1>, SDTCisSameAs<1, 2>]>;
77 SDTypeProfile<1, 2, [SDTCisVT<0, FlagVT>, SDTCisFP<1>, SDTCisSameAs<1, 2>]>;
79 SDTypeProfile<0, 3, [SDTCisVT<0, OtherVT>, SDTCisVT<1, OtherVT>,
80 SDTCisVT<2, FlagVT>]>;
82 def V8cmpicc : SDNode<"V8ISD::CMPICC", SDTV8cmpicc>;
83 def V8cmpfcc : SDNode<"V8ISD::CMPFCC", SDTV8cmpfcc>;
84 def V8bricc : SDNode<"V8ISD::BRICC", SDTV8brcc, [SDNPHasChain]>;
85 def V8brfcc : SDNode<"V8ISD::BRFCC", SDTV8brcc, [SDNPHasChain]>;
87 def V8hi : SDNode<"V8ISD::Hi", SDTIntUnaryOp>;
88 def V8lo : SDNode<"V8ISD::Lo", SDTIntUnaryOp>;
90 def V8ftoi : SDNode<"V8ISD::FTOI", SDTFPUnaryOp>;
91 def V8itof : SDNode<"V8ISD::ITOF", SDTFPUnaryOp>;
93 //===----------------------------------------------------------------------===//
95 //===----------------------------------------------------------------------===//
97 // Pseudo instructions.
98 class PseudoInstV8<string asmstr, dag ops> : InstV8 {
99 let AsmString = asmstr;
100 dag OperandList = ops;
102 def PHI : PseudoInstV8<"PHI", (ops variable_ops)>;
103 def ADJCALLSTACKDOWN : PseudoInstV8<"!ADJCALLSTACKDOWN $amt",
105 def ADJCALLSTACKUP : PseudoInstV8<"!ADJCALLSTACKUP $amt",
107 //def IMPLICIT_USE : PseudoInstV8<"!IMPLICIT_USE",(ops variable_ops)>;
108 def IMPLICIT_DEF : PseudoInstV8<"!IMPLICIT_DEF $dst",
110 def FpMOVD : PseudoInstV8<"!FpMOVD", // pseudo 64-bit double move
111 (ops DFPRegs:$dst, DFPRegs:$src)>;
113 // Section A.3 - Synthetic Instructions, p. 85
114 // special cases of JMPL:
115 let isReturn = 1, isTerminator = 1, hasDelaySlot = 1 in {
116 let rd = O7.Num, rs1 = G0.Num, simm13 = 8 in
117 def RETL: F3_2<2, 0b111000, (ops),
121 // Section B.1 - Load Integer Instructions, p. 90
122 def LDSBrr : F3_1<3, 0b001001,
123 (ops IntRegs:$dst, MEMrr:$addr),
124 "ldsb [$addr], $dst",
125 [(set IntRegs:$dst, (sextload ADDRrr:$addr, i8))]>;
126 def LDSBri : F3_2<3, 0b001001,
127 (ops IntRegs:$dst, MEMri:$addr),
128 "ldsb [$addr], $dst",
129 [(set IntRegs:$dst, (sextload ADDRri:$addr, i8))]>;
130 def LDSHrr : F3_1<3, 0b001010,
131 (ops IntRegs:$dst, MEMrr:$addr),
132 "ldsh [$addr], $dst",
133 [(set IntRegs:$dst, (sextload ADDRrr:$addr, i16))]>;
134 def LDSHri : F3_2<3, 0b001010,
135 (ops IntRegs:$dst, MEMri:$addr),
136 "ldsh [$addr], $dst",
137 [(set IntRegs:$dst, (sextload ADDRri:$addr, i16))]>;
138 def LDUBrr : F3_1<3, 0b000001,
139 (ops IntRegs:$dst, MEMrr:$addr),
140 "ldub [$addr], $dst",
141 [(set IntRegs:$dst, (zextload ADDRrr:$addr, i8))]>;
142 def LDUBri : F3_2<3, 0b000001,
143 (ops IntRegs:$dst, MEMri:$addr),
144 "ldub [$addr], $dst",
145 [(set IntRegs:$dst, (zextload ADDRri:$addr, i8))]>;
146 def LDUHrr : F3_1<3, 0b000010,
147 (ops IntRegs:$dst, MEMrr:$addr),
148 "lduh [$addr], $dst",
149 [(set IntRegs:$dst, (zextload ADDRrr:$addr, i16))]>;
150 def LDUHri : F3_2<3, 0b000010,
151 (ops IntRegs:$dst, MEMri:$addr),
152 "lduh [$addr], $dst",
153 [(set IntRegs:$dst, (zextload ADDRri:$addr, i16))]>;
154 def LDrr : F3_1<3, 0b000000,
155 (ops IntRegs:$dst, MEMrr:$addr),
157 [(set IntRegs:$dst, (load ADDRrr:$addr))]>;
158 def LDri : F3_2<3, 0b000000,
159 (ops IntRegs:$dst, MEMri:$addr),
161 [(set IntRegs:$dst, (load ADDRri:$addr))]>;
162 def LDDrr : F3_1<3, 0b000011,
163 (ops IntRegs:$dst, MEMrr:$addr),
164 "ldd [$addr], $dst", []>;
165 def LDDri : F3_2<3, 0b000011,
166 (ops IntRegs:$dst, MEMri:$addr),
167 "ldd [$addr], $dst", []>;
169 // Section B.2 - Load Floating-point Instructions, p. 92
170 def LDFrr : F3_1<3, 0b100000,
171 (ops FPRegs:$dst, MEMrr:$addr),
173 [(set FPRegs:$dst, (load ADDRrr:$addr))]>;
174 def LDFri : F3_2<3, 0b100000,
175 (ops FPRegs:$dst, MEMri:$addr),
177 [(set FPRegs:$dst, (load ADDRri:$addr))]>;
178 def LDDFrr : F3_1<3, 0b100011,
179 (ops DFPRegs:$dst, MEMrr:$addr),
181 [(set DFPRegs:$dst, (load ADDRrr:$addr))]>;
182 def LDDFri : F3_2<3, 0b100011,
183 (ops DFPRegs:$dst, MEMri:$addr),
185 [(set DFPRegs:$dst, (load ADDRri:$addr))]>;
187 // Section B.4 - Store Integer Instructions, p. 95
188 def STBrr : F3_1<3, 0b000101,
189 (ops MEMrr:$addr, IntRegs:$src),
191 [(truncstore IntRegs:$src, ADDRrr:$addr, i8)]>;
192 def STBri : F3_2<3, 0b000101,
193 (ops MEMri:$addr, IntRegs:$src),
195 [(truncstore IntRegs:$src, ADDRri:$addr, i8)]>;
196 def STHrr : F3_1<3, 0b000110,
197 (ops MEMrr:$addr, IntRegs:$src),
199 [(truncstore IntRegs:$src, ADDRrr:$addr, i16)]>;
200 def STHri : F3_2<3, 0b000110,
201 (ops MEMri:$addr, IntRegs:$src),
203 [(truncstore IntRegs:$src, ADDRri:$addr, i16)]>;
204 def STrr : F3_1<3, 0b000100,
205 (ops MEMrr:$addr, IntRegs:$src),
207 [(store IntRegs:$src, ADDRrr:$addr)]>;
208 def STri : F3_2<3, 0b000100,
209 (ops MEMri:$addr, IntRegs:$src),
211 [(store IntRegs:$src, ADDRri:$addr)]>;
212 def STDrr : F3_1<3, 0b000111,
213 (ops MEMrr:$addr, IntRegs:$src),
214 "std $src, [$addr]", []>;
215 def STDri : F3_2<3, 0b000111,
216 (ops MEMri:$addr, IntRegs:$src),
217 "std $src, [$addr]", []>;
219 // Section B.5 - Store Floating-point Instructions, p. 97
220 def STFrr : F3_1<3, 0b100100,
221 (ops MEMrr:$addr, FPRegs:$src),
223 [(store FPRegs:$src, ADDRrr:$addr)]>;
224 def STFri : F3_2<3, 0b100100,
225 (ops MEMri:$addr, FPRegs:$src),
227 [(store FPRegs:$src, ADDRri:$addr)]>;
228 def STDFrr : F3_1<3, 0b100111,
229 (ops MEMrr:$addr, DFPRegs:$src),
231 [(store DFPRegs:$src, ADDRrr:$addr)]>;
232 def STDFri : F3_2<3, 0b100111,
233 (ops MEMri:$addr, DFPRegs:$src),
235 [(store DFPRegs:$src, ADDRri:$addr)]>;
237 // Section B.9 - SETHI Instruction, p. 104
238 def SETHIi: F2_1<0b100,
239 (ops IntRegs:$dst, i32imm:$src),
241 [(set IntRegs:$dst, SETHIimm:$src)]>;
243 // Section B.10 - NOP Instruction, p. 105
244 // (It's a special case of SETHI)
245 let rd = 0, imm22 = 0 in
246 def NOP : F2_1<0b100, (ops), "nop", []>;
248 // Section B.11 - Logical Instructions, p. 106
249 def ANDrr : F3_1<2, 0b000001,
250 (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c),
252 [(set IntRegs:$dst, (and IntRegs:$b, IntRegs:$c))]>;
253 def ANDri : F3_2<2, 0b000001,
254 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c),
256 [(set IntRegs:$dst, (and IntRegs:$b, simm13:$c))]>;
257 def ANDNrr : F3_1<2, 0b000101,
258 (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c),
260 [(set IntRegs:$dst, (and IntRegs:$b, (not IntRegs:$c)))]>;
261 def ANDNri : F3_2<2, 0b000101,
262 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c),
263 "andn $b, $c, $dst", []>;
264 def ORrr : F3_1<2, 0b000010,
265 (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c),
267 [(set IntRegs:$dst, (or IntRegs:$b, IntRegs:$c))]>;
268 def ORri : F3_2<2, 0b000010,
269 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c),
271 [(set IntRegs:$dst, (or IntRegs:$b, simm13:$c))]>;
272 def ORNrr : F3_1<2, 0b000110,
273 (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c),
275 [(set IntRegs:$dst, (or IntRegs:$b, (not IntRegs:$c)))]>;
276 def ORNri : F3_2<2, 0b000110,
277 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c),
278 "orn $b, $c, $dst", []>;
279 def XORrr : F3_1<2, 0b000011,
280 (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c),
282 [(set IntRegs:$dst, (xor IntRegs:$b, IntRegs:$c))]>;
283 def XORri : F3_2<2, 0b000011,
284 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c),
286 [(set IntRegs:$dst, (xor IntRegs:$b, simm13:$c))]>;
287 def XNORrr : F3_1<2, 0b000111,
288 (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c),
290 [(set IntRegs:$dst, (xor IntRegs:$b, (not IntRegs:$c)))]>;
291 def XNORri : F3_2<2, 0b000111,
292 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c),
293 "xnor $b, $c, $dst", []>;
295 // Section B.12 - Shift Instructions, p. 107
296 def SLLrr : F3_1<2, 0b100101,
297 (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c),
299 [(set IntRegs:$dst, (shl IntRegs:$b, IntRegs:$c))]>;
300 def SLLri : F3_2<2, 0b100101,
301 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c),
303 [(set IntRegs:$dst, (shl IntRegs:$b, simm13:$c))]>;
304 def SRLrr : F3_1<2, 0b100110,
305 (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c),
307 [(set IntRegs:$dst, (srl IntRegs:$b, IntRegs:$c))]>;
308 def SRLri : F3_2<2, 0b100110,
309 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c),
311 [(set IntRegs:$dst, (srl IntRegs:$b, simm13:$c))]>;
312 def SRArr : F3_1<2, 0b100111,
313 (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c),
315 [(set IntRegs:$dst, (sra IntRegs:$b, IntRegs:$c))]>;
316 def SRAri : F3_2<2, 0b100111,
317 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c),
319 [(set IntRegs:$dst, (sra IntRegs:$b, simm13:$c))]>;
321 // Section B.13 - Add Instructions, p. 108
322 def ADDrr : F3_1<2, 0b000000,
323 (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c),
325 [(set IntRegs:$dst, (add IntRegs:$b, IntRegs:$c))]>;
326 def ADDri : F3_2<2, 0b000000,
327 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c),
329 [(set IntRegs:$dst, (add IntRegs:$b, simm13:$c))]>;
330 def ADDCCrr : F3_1<2, 0b010000,
331 (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c),
332 "addcc $b, $c, $dst", []>;
333 def ADDCCri : F3_2<2, 0b010000,
334 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c),
335 "addcc $b, $c, $dst", []>;
336 def ADDXrr : F3_1<2, 0b001000,
337 (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c),
338 "addx $b, $c, $dst", []>;
339 def ADDXri : F3_2<2, 0b001000,
340 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c),
341 "addx $b, $c, $dst", []>;
343 // Section B.15 - Subtract Instructions, p. 110
344 def SUBrr : F3_1<2, 0b000100,
345 (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c),
347 [(set IntRegs:$dst, (sub IntRegs:$b, IntRegs:$c))]>;
348 def SUBri : F3_2<2, 0b000100,
349 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c),
351 [(set IntRegs:$dst, (sub IntRegs:$b, simm13:$c))]>;
352 def SUBXrr : F3_1<2, 0b001100,
353 (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c),
354 "subx $b, $c, $dst", []>;
355 def SUBXri : F3_2<2, 0b001100,
356 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c),
357 "subx $b, $c, $dst", []>;
358 def SUBCCrr : F3_1<2, 0b010100,
359 (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c),
360 "subcc $b, $c, $dst", []>;
361 def SUBCCri : F3_2<2, 0b010100,
362 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c),
363 "subcc $b, $c, $dst", []>;
364 def SUBXCCrr: F3_1<2, 0b011100,
365 (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c),
366 "subxcc $b, $c, $dst", []>;
368 // Section B.18 - Multiply Instructions, p. 113
369 def UMULrr : F3_1<2, 0b001010,
370 (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c),
371 "umul $b, $c, $dst", []>;
372 def UMULri : F3_2<2, 0b001010,
373 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c),
374 "umul $b, $c, $dst", []>;
375 def SMULrr : F3_1<2, 0b001011,
376 (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c),
378 [(set IntRegs:$dst, (mul IntRegs:$b, IntRegs:$c))]>;
379 def SMULri : F3_2<2, 0b001011,
380 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c),
382 [(set IntRegs:$dst, (mul IntRegs:$b, simm13:$c))]>;
384 // Section B.19 - Divide Instructions, p. 115
385 def UDIVrr : F3_1<2, 0b001110,
386 (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c),
387 "udiv $b, $c, $dst", []>;
388 def UDIVri : F3_2<2, 0b001110,
389 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c),
390 "udiv $b, $c, $dst", []>;
391 def SDIVrr : F3_1<2, 0b001111,
392 (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c),
393 "sdiv $b, $c, $dst", []>;
394 def SDIVri : F3_2<2, 0b001111,
395 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c),
396 "sdiv $b, $c, $dst", []>;
398 // Section B.20 - SAVE and RESTORE, p. 117
399 def SAVErr : F3_1<2, 0b111100,
400 (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c),
401 "save $b, $c, $dst", []>;
402 def SAVEri : F3_2<2, 0b111100,
403 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c),
404 "save $b, $c, $dst", []>;
405 def RESTORErr : F3_1<2, 0b111101,
406 (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c),
407 "restore $b, $c, $dst", []>;
408 def RESTOREri : F3_2<2, 0b111101,
409 (ops IntRegs:$dst, IntRegs:$b, i32imm:$c),
410 "restore $b, $c, $dst", []>;
412 // Section B.21 - Branch on Integer Condition Codes Instructions, p. 119
414 // conditional branch class:
415 class BranchV8<bits<4> cc, dag ops, string asmstr, list<dag> pattern>
416 : F2_2<cc, 0b010, ops, asmstr, pattern> {
418 let isTerminator = 1;
419 let hasDelaySlot = 1;
423 def BA : BranchV8<0b1000, (ops brtarget:$dst),
426 def BNE : BranchV8<0b1001, (ops brtarget:$dst),
428 [(V8bricc bb:$dst, SETNE, ICC)]>;
429 def BE : BranchV8<0b0001, (ops brtarget:$dst),
431 [(V8bricc bb:$dst, SETEQ, ICC)]>;
432 def BG : BranchV8<0b1010, (ops brtarget:$dst),
434 [(V8bricc bb:$dst, SETGT, ICC)]>;
435 def BLE : BranchV8<0b0010, (ops brtarget:$dst),
437 [(V8bricc bb:$dst, SETLE, ICC)]>;
438 def BGE : BranchV8<0b1011, (ops brtarget:$dst),
440 [(V8bricc bb:$dst, SETGE, ICC)]>;
441 def BL : BranchV8<0b0011, (ops brtarget:$dst),
443 [(V8bricc bb:$dst, SETLT, ICC)]>;
444 def BGU : BranchV8<0b1100, (ops brtarget:$dst),
446 [(V8bricc bb:$dst, SETUGT, ICC)]>;
447 def BLEU : BranchV8<0b0100, (ops brtarget:$dst),
449 [(V8bricc bb:$dst, SETULE, ICC)]>;
450 def BCC : BranchV8<0b1101, (ops brtarget:$dst),
452 [(V8bricc bb:$dst, SETUGE, ICC)]>;
453 def BCS : BranchV8<0b0101, (ops brtarget:$dst),
455 [(V8bricc bb:$dst, SETULT, ICC)]>;
457 // Section B.22 - Branch on Floating-point Condition Codes Instructions, p. 121
459 // floating-point conditional branch class:
460 class FPBranchV8<bits<4> cc, dag ops, string asmstr, list<dag> pattern>
461 : F2_2<cc, 0b110, ops, asmstr, pattern> {
463 let isTerminator = 1;
464 let hasDelaySlot = 1;
467 def FBU : FPBranchV8<0b0111, (ops brtarget:$dst),
469 [(V8brfcc bb:$dst, SETUO, FCC)]>;
470 def FBG : FPBranchV8<0b0110, (ops brtarget:$dst),
472 [(V8brfcc bb:$dst, SETGT, FCC)]>;
473 def FBUG : FPBranchV8<0b0101, (ops brtarget:$dst),
475 [(V8brfcc bb:$dst, SETUGT, FCC)]>;
476 def FBL : FPBranchV8<0b0100, (ops brtarget:$dst),
478 [(V8brfcc bb:$dst, SETLT, FCC)]>;
479 def FBUL : FPBranchV8<0b0011, (ops brtarget:$dst),
481 [(V8brfcc bb:$dst, SETULT, FCC)]>;
482 def FBLG : FPBranchV8<0b0010, (ops brtarget:$dst),
484 [(V8brfcc bb:$dst, SETONE, FCC)]>;
485 def FBNE : FPBranchV8<0b0001, (ops brtarget:$dst),
487 [(V8brfcc bb:$dst, SETNE, FCC)]>;
488 def FBE : FPBranchV8<0b1001, (ops brtarget:$dst),
490 [(V8brfcc bb:$dst, SETEQ, FCC)]>;
491 def FBUE : FPBranchV8<0b1010, (ops brtarget:$dst),
493 [(V8brfcc bb:$dst, SETUEQ, FCC)]>;
494 def FBGE : FPBranchV8<0b1011, (ops brtarget:$dst),
496 [(V8brfcc bb:$dst, SETGE, FCC)]>;
497 def FBUGE: FPBranchV8<0b1100, (ops brtarget:$dst),
499 [(V8brfcc bb:$dst, SETUGE, FCC)]>;
500 def FBLE : FPBranchV8<0b1101, (ops brtarget:$dst),
502 [(V8brfcc bb:$dst, SETLE, FCC)]>;
503 def FBULE: FPBranchV8<0b1110, (ops brtarget:$dst),
505 [(V8brfcc bb:$dst, SETULE, FCC)]>;
506 def FBO : FPBranchV8<0b1111, (ops brtarget:$dst),
508 [(V8brfcc bb:$dst, SETO, FCC)]>;
512 // Section B.24 - Call and Link Instruction, p. 125
513 // This is the only Format 1 instruction
514 let Uses = [O0, O1, O2, O3, O4, O5], hasDelaySlot = 1, isCall = 1 in {
516 let Defs = [O0, O1, O2, O3, O4, O5, O7, G1, G2, G3, G4, G5, G6, G7,
517 D0, D1, D2, D3, D4, D5, D6, D7, D8, D9, D10, D11, D12, D13, D14, D15] in
519 let OperandList = (ops IntRegs:$dst);
522 let Inst{29-0} = disp;
523 let AsmString = "call $dst";
526 // indirect call (O7 is an EXPLICIT def in indirect calls, so it cannot also
527 // be an implicit def):
528 let Defs = [O0, O1, O2, O3, O4, O5, G1, G2, G3, G4, G5, G6, G7,
529 D0, D1, D2, D3, D4, D5, D6, D7, D8, D9, D10, D11, D12, D13, D14, D15] in
530 def JMPLrr : F3_1<2, 0b111000,
531 (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c),
532 "jmpl $b+$c, $dst", []>;
535 // Section B.28 - Read State Register Instructions
536 def RDY : F3_1<2, 0b101000,
540 // Section B.29 - Write State Register Instructions
541 def WRYrr : F3_1<2, 0b110000,
542 (ops IntRegs:$b, IntRegs:$c),
543 "wr $b, $c, %y", []>;
544 def WRYri : F3_2<2, 0b110000,
545 (ops IntRegs:$b, i32imm:$c),
546 "wr $b, $c, %y", []>;
548 // Convert Integer to Floating-point Instructions, p. 141
549 def FITOS : F3_3<2, 0b110100, 0b011000100,
550 (ops FPRegs:$dst, FPRegs:$src),
552 [(set FPRegs:$dst, (V8itof FPRegs:$src))]>;
553 def FITOD : F3_3<2, 0b110100, 0b011001000,
554 (ops DFPRegs:$dst, DFPRegs:$src),
556 [(set DFPRegs:$dst, (V8itof DFPRegs:$src))]>;
558 // Convert Floating-point to Integer Instructions, p. 142
559 def FSTOI : F3_3<2, 0b110100, 0b011010001,
560 (ops FPRegs:$dst, FPRegs:$src),
562 [(set FPRegs:$dst, (V8ftoi FPRegs:$src))]>;
563 def FDTOI : F3_3<2, 0b110100, 0b011010010,
564 (ops DFPRegs:$dst, DFPRegs:$src),
566 [(set DFPRegs:$dst, (V8ftoi DFPRegs:$src))]>;
568 // Convert between Floating-point Formats Instructions, p. 143
569 def FSTOD : F3_3<2, 0b110100, 0b011001001,
570 (ops DFPRegs:$dst, FPRegs:$src),
572 [(set DFPRegs:$dst, (fextend FPRegs:$src))]>;
573 def FDTOS : F3_3<2, 0b110100, 0b011000110,
574 (ops FPRegs:$dst, DFPRegs:$src),
576 [(set FPRegs:$dst, (fround DFPRegs:$src))]>;
578 // Floating-point Move Instructions, p. 144
579 def FMOVS : F3_3<2, 0b110100, 0b000000001,
580 (ops FPRegs:$dst, FPRegs:$src),
581 "fmovs $src, $dst", []>;
582 def FNEGS : F3_3<2, 0b110100, 0b000000101,
583 (ops FPRegs:$dst, FPRegs:$src),
585 [(set FPRegs:$dst, (fneg FPRegs:$src))]>;
586 def FABSS : F3_3<2, 0b110100, 0b000001001,
587 (ops FPRegs:$dst, FPRegs:$src),
589 [(set FPRegs:$dst, (fabs FPRegs:$src))]>;
590 // FIXME: ADD FNEGD/FABSD pseudo instructions.
593 // Floating-point Square Root Instructions, p.145
594 def FSQRTS : F3_3<2, 0b110100, 0b000101001,
595 (ops FPRegs:$dst, FPRegs:$src),
597 [(set FPRegs:$dst, (fsqrt FPRegs:$src))]>;
598 def FSQRTD : F3_3<2, 0b110100, 0b000101010,
599 (ops DFPRegs:$dst, DFPRegs:$src),
601 [(set DFPRegs:$dst, (fsqrt DFPRegs:$src))]>;
605 // Floating-point Add and Subtract Instructions, p. 146
606 def FADDS : F3_3<2, 0b110100, 0b001000001,
607 (ops FPRegs:$dst, FPRegs:$src1, FPRegs:$src2),
608 "fadds $src1, $src2, $dst",
609 [(set FPRegs:$dst, (fadd FPRegs:$src1, FPRegs:$src2))]>;
610 def FADDD : F3_3<2, 0b110100, 0b001000010,
611 (ops DFPRegs:$dst, DFPRegs:$src1, DFPRegs:$src2),
612 "faddd $src1, $src2, $dst",
613 [(set DFPRegs:$dst, (fadd DFPRegs:$src1, DFPRegs:$src2))]>;
614 def FSUBS : F3_3<2, 0b110100, 0b001000101,
615 (ops FPRegs:$dst, FPRegs:$src1, FPRegs:$src2),
616 "fsubs $src1, $src2, $dst",
617 [(set FPRegs:$dst, (fsub FPRegs:$src1, FPRegs:$src2))]>;
618 def FSUBD : F3_3<2, 0b110100, 0b001000110,
619 (ops DFPRegs:$dst, DFPRegs:$src1, DFPRegs:$src2),
620 "fsubd $src1, $src2, $dst",
621 [(set DFPRegs:$dst, (fsub DFPRegs:$src1, DFPRegs:$src2))]>;
623 // Floating-point Multiply and Divide Instructions, p. 147
624 def FMULS : F3_3<2, 0b110100, 0b001001001,
625 (ops FPRegs:$dst, FPRegs:$src1, FPRegs:$src2),
626 "fmuls $src1, $src2, $dst",
627 [(set FPRegs:$dst, (fmul FPRegs:$src1, FPRegs:$src2))]>;
628 def FMULD : F3_3<2, 0b110100, 0b001001010,
629 (ops DFPRegs:$dst, DFPRegs:$src1, DFPRegs:$src2),
630 "fmuld $src1, $src2, $dst",
631 [(set DFPRegs:$dst, (fmul DFPRegs:$src1, DFPRegs:$src2))]>;
632 def FSMULD : F3_3<2, 0b110100, 0b001101001,
633 (ops DFPRegs:$dst, FPRegs:$src1, FPRegs:$src2),
634 "fsmuld $src1, $src2, $dst",
635 [(set DFPRegs:$dst, (fmul (fextend FPRegs:$src1),
636 (fextend FPRegs:$src2)))]>;
637 def FDIVS : F3_3<2, 0b110100, 0b001001101,
638 (ops FPRegs:$dst, FPRegs:$src1, FPRegs:$src2),
639 "fdivs $src1, $src2, $dst",
640 [(set FPRegs:$dst, (fdiv FPRegs:$src1, FPRegs:$src2))]>;
641 def FDIVD : F3_3<2, 0b110100, 0b001001110,
642 (ops DFPRegs:$dst, DFPRegs:$src1, DFPRegs:$src2),
643 "fdivd $src1, $src2, $dst",
644 [(set DFPRegs:$dst, (fdiv DFPRegs:$src1, DFPRegs:$src2))]>;
646 // Floating-point Compare Instructions, p. 148
647 // Note: the 2nd template arg is different for these guys.
648 // Note 2: the result of a FCMP is not available until the 2nd cycle
649 // after the instr is retired, but there is no interlock. This behavior
650 // is modelled with a forced noop after the instruction.
651 def FCMPS : F3_3<2, 0b110101, 0b001010001,
652 (ops FPRegs:$src1, FPRegs:$src2),
653 "fcmps $src1, $src2\n\tnop",
654 [(set FCC, (V8cmpfcc FPRegs:$src1, FPRegs:$src2))]>;
655 def FCMPD : F3_3<2, 0b110101, 0b001010010,
656 (ops DFPRegs:$src1, DFPRegs:$src2),
657 "fcmpd $src1, $src2\n\tnop",
658 [(set FCC, (V8cmpfcc DFPRegs:$src1, DFPRegs:$src2))]>;
660 //===----------------------------------------------------------------------===//
661 // Non-Instruction Patterns
662 //===----------------------------------------------------------------------===//
665 def : Pat<(i32 simm13:$val),
666 (ORri G0, imm:$val)>;
667 // Arbitrary immediates.
668 def : Pat<(i32 imm:$val),
669 (ORri (SETHIi (HI22 imm:$val)), (LO10 imm:$val))>;
671 // Global addresses, constant pool entries
672 def : Pat<(V8hi tglobaladdr:$in), (SETHIi tglobaladdr:$in)>;
673 def : Pat<(V8lo tglobaladdr:$in), (ORri G0, tglobaladdr:$in)>;
674 def : Pat<(V8hi tconstpool:$in), (SETHIi tconstpool:$in)>;
675 def : Pat<(V8lo tconstpool:$in), (ORri G0, tconstpool:$in)>;