1 //===-- SparcInstrInfo.td - Target Description for Sparc Target -----------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the Sparc instructions in TableGen format.
12 //===----------------------------------------------------------------------===//
14 //===----------------------------------------------------------------------===//
15 // Instruction format superclass
16 //===----------------------------------------------------------------------===//
18 include "SparcInstrFormats.td"
20 //===----------------------------------------------------------------------===//
21 // Feature predicates.
22 //===----------------------------------------------------------------------===//
24 // True when generating 32-bit code.
25 def Is32Bit : Predicate<"!Subtarget->is64Bit()">;
27 // True when generating 64-bit code. This also implies HasV9.
28 def Is64Bit : Predicate<"Subtarget->is64Bit()">;
30 // HasV9 - This predicate is true when the target processor supports V9
31 // instructions. Note that the machine may be running in 32-bit mode.
32 def HasV9 : Predicate<"Subtarget->isV9()">,
33 AssemblerPredicate<"FeatureV9">;
35 // HasNoV9 - This predicate is true when the target doesn't have V9
36 // instructions. Use of this is just a hack for the isel not having proper
37 // costs for V8 instructions that are more expensive than their V9 ones.
38 def HasNoV9 : Predicate<"!Subtarget->isV9()">;
40 // HasVIS - This is true when the target processor has VIS extensions.
41 def HasVIS : Predicate<"Subtarget->isVIS()">,
42 AssemblerPredicate<"FeatureVIS">;
43 def HasVIS2 : Predicate<"Subtarget->isVIS2()">,
44 AssemblerPredicate<"FeatureVIS2">;
45 def HasVIS3 : Predicate<"Subtarget->isVIS3()">,
46 AssemblerPredicate<"FeatureVIS3">;
48 // HasHardQuad - This is true when the target processor supports quad floating
49 // point instructions.
50 def HasHardQuad : Predicate<"Subtarget->hasHardQuad()">;
52 // UseDeprecatedInsts - This predicate is true when the target processor is a
53 // V8, or when it is V9 but the V8 deprecated instructions are efficient enough
54 // to use when appropriate. In either of these cases, the instruction selector
55 // will pick deprecated instructions.
56 def UseDeprecatedInsts : Predicate<"Subtarget->useDeprecatedV8Instructions()">;
58 //===----------------------------------------------------------------------===//
59 // Instruction Pattern Stuff
60 //===----------------------------------------------------------------------===//
62 def simm11 : PatLeaf<(imm), [{ return isInt<11>(N->getSExtValue()); }]>;
64 def simm13 : PatLeaf<(imm), [{ return isInt<13>(N->getSExtValue()); }]>;
66 def LO10 : SDNodeXForm<imm, [{
67 return CurDAG->getTargetConstant((unsigned)N->getZExtValue() & 1023, SDLoc(N),
71 def HI22 : SDNodeXForm<imm, [{
72 // Transformation function: shift the immediate value down into the low bits.
73 return CurDAG->getTargetConstant((unsigned)N->getZExtValue() >> 10, SDLoc(N),
77 def SETHIimm : PatLeaf<(imm), [{
78 return isShiftedUInt<22, 10>(N->getZExtValue());
82 def ADDRrr : ComplexPattern<iPTR, 2, "SelectADDRrr", [], []>;
83 def ADDRri : ComplexPattern<iPTR, 2, "SelectADDRri", [frameindex], []>;
86 def SparcMEMrrAsmOperand : AsmOperandClass {
88 let ParserMethod = "parseMEMOperand";
91 def SparcMEMriAsmOperand : AsmOperandClass {
93 let ParserMethod = "parseMEMOperand";
96 def MEMrr : Operand<iPTR> {
97 let PrintMethod = "printMemOperand";
98 let MIOperandInfo = (ops ptr_rc, ptr_rc);
99 let ParserMatchClass = SparcMEMrrAsmOperand;
101 def MEMri : Operand<iPTR> {
102 let PrintMethod = "printMemOperand";
103 let MIOperandInfo = (ops ptr_rc, i32imm);
104 let ParserMatchClass = SparcMEMriAsmOperand;
107 def TLSSym : Operand<iPTR>;
109 // Branch targets have OtherVT type.
110 def brtarget : Operand<OtherVT> {
111 let EncoderMethod = "getBranchTargetOpValue";
114 def bprtarget : Operand<OtherVT> {
115 let EncoderMethod = "getBranchPredTargetOpValue";
118 def bprtarget16 : Operand<OtherVT> {
119 let EncoderMethod = "getBranchOnRegTargetOpValue";
122 def calltarget : Operand<i32> {
123 let EncoderMethod = "getCallTargetOpValue";
124 let DecoderMethod = "DecodeCall";
127 def simm13Op : Operand<i32> {
128 let DecoderMethod = "DecodeSIMM13";
131 // Operand for printing out a condition code.
132 let PrintMethod = "printCCOperand" in
133 def CCOp : Operand<i32>;
136 SDTypeProfile<0, 2, [SDTCisInt<0>, SDTCisSameAs<0, 1>]>;
138 SDTypeProfile<0, 2, [SDTCisFP<0>, SDTCisSameAs<0, 1>]>;
140 SDTypeProfile<0, 2, [SDTCisVT<0, OtherVT>, SDTCisVT<1, i32>]>;
142 SDTypeProfile<1, 3, [SDTCisSameAs<0, 1>, SDTCisSameAs<1, 2>, SDTCisVT<3, i32>]>;
144 SDTypeProfile<1, 1, [SDTCisVT<0, f32>, SDTCisFP<1>]>;
146 SDTypeProfile<1, 1, [SDTCisFP<0>, SDTCisVT<1, f32>]>;
148 SDTypeProfile<1, 1, [SDTCisVT<0, f64>, SDTCisFP<1>]>;
150 SDTypeProfile<1, 1, [SDTCisFP<0>, SDTCisVT<1, f64>]>;
153 SDTypeProfile<1, 3, [SDTCisInt<0>, SDTCisSameAs<0, 1>, SDTCisPtrTy<2>]>;
155 SDTypeProfile<1, 2, [SDTCisPtrTy<0>, SDTCisPtrTy<1>]>;
157 def SPcmpicc : SDNode<"SPISD::CMPICC", SDTSPcmpicc, [SDNPOutGlue]>;
158 def SPcmpfcc : SDNode<"SPISD::CMPFCC", SDTSPcmpfcc, [SDNPOutGlue]>;
159 def SPbricc : SDNode<"SPISD::BRICC", SDTSPbrcc, [SDNPHasChain, SDNPInGlue]>;
160 def SPbrxcc : SDNode<"SPISD::BRXCC", SDTSPbrcc, [SDNPHasChain, SDNPInGlue]>;
161 def SPbrfcc : SDNode<"SPISD::BRFCC", SDTSPbrcc, [SDNPHasChain, SDNPInGlue]>;
163 def SPhi : SDNode<"SPISD::Hi", SDTIntUnaryOp>;
164 def SPlo : SDNode<"SPISD::Lo", SDTIntUnaryOp>;
166 def SPftoi : SDNode<"SPISD::FTOI", SDTSPFTOI>;
167 def SPitof : SDNode<"SPISD::ITOF", SDTSPITOF>;
168 def SPftox : SDNode<"SPISD::FTOX", SDTSPFTOX>;
169 def SPxtof : SDNode<"SPISD::XTOF", SDTSPXTOF>;
171 def SPselecticc : SDNode<"SPISD::SELECT_ICC", SDTSPselectcc, [SDNPInGlue]>;
172 def SPselectxcc : SDNode<"SPISD::SELECT_XCC", SDTSPselectcc, [SDNPInGlue]>;
173 def SPselectfcc : SDNode<"SPISD::SELECT_FCC", SDTSPselectcc, [SDNPInGlue]>;
175 // These are target-independent nodes, but have target-specific formats.
176 def SDT_SPCallSeqStart : SDCallSeqStart<[ SDTCisVT<0, i32> ]>;
177 def SDT_SPCallSeqEnd : SDCallSeqEnd<[ SDTCisVT<0, i32>,
180 def callseq_start : SDNode<"ISD::CALLSEQ_START", SDT_SPCallSeqStart,
181 [SDNPHasChain, SDNPOutGlue]>;
182 def callseq_end : SDNode<"ISD::CALLSEQ_END", SDT_SPCallSeqEnd,
183 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]>;
185 def SDT_SPCall : SDTypeProfile<0, -1, [SDTCisVT<0, i32>]>;
186 def call : SDNode<"SPISD::CALL", SDT_SPCall,
187 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue,
190 def SDT_SPRet : SDTypeProfile<0, 1, [SDTCisVT<0, i32>]>;
191 def retflag : SDNode<"SPISD::RET_FLAG", SDT_SPRet,
192 [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>;
194 def flushw : SDNode<"SPISD::FLUSHW", SDTNone,
195 [SDNPHasChain, SDNPSideEffect, SDNPMayStore]>;
197 def tlsadd : SDNode<"SPISD::TLS_ADD", SDTSPtlsadd>;
198 def tlsld : SDNode<"SPISD::TLS_LD", SDTSPtlsld>;
199 def tlscall : SDNode<"SPISD::TLS_CALL", SDT_SPCall,
200 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue,
203 def getPCX : Operand<iPTR> {
204 let PrintMethod = "printGetPCX";
207 //===----------------------------------------------------------------------===//
208 // SPARC Flag Conditions
209 //===----------------------------------------------------------------------===//
211 // Note that these values must be kept in sync with the CCOp::CondCode enum
213 class ICC_VAL<int N> : PatLeaf<(i32 N)>;
214 def ICC_NE : ICC_VAL< 9>; // Not Equal
215 def ICC_E : ICC_VAL< 1>; // Equal
216 def ICC_G : ICC_VAL<10>; // Greater
217 def ICC_LE : ICC_VAL< 2>; // Less or Equal
218 def ICC_GE : ICC_VAL<11>; // Greater or Equal
219 def ICC_L : ICC_VAL< 3>; // Less
220 def ICC_GU : ICC_VAL<12>; // Greater Unsigned
221 def ICC_LEU : ICC_VAL< 4>; // Less or Equal Unsigned
222 def ICC_CC : ICC_VAL<13>; // Carry Clear/Great or Equal Unsigned
223 def ICC_CS : ICC_VAL< 5>; // Carry Set/Less Unsigned
224 def ICC_POS : ICC_VAL<14>; // Positive
225 def ICC_NEG : ICC_VAL< 6>; // Negative
226 def ICC_VC : ICC_VAL<15>; // Overflow Clear
227 def ICC_VS : ICC_VAL< 7>; // Overflow Set
229 class FCC_VAL<int N> : PatLeaf<(i32 N)>;
230 def FCC_U : FCC_VAL<23>; // Unordered
231 def FCC_G : FCC_VAL<22>; // Greater
232 def FCC_UG : FCC_VAL<21>; // Unordered or Greater
233 def FCC_L : FCC_VAL<20>; // Less
234 def FCC_UL : FCC_VAL<19>; // Unordered or Less
235 def FCC_LG : FCC_VAL<18>; // Less or Greater
236 def FCC_NE : FCC_VAL<17>; // Not Equal
237 def FCC_E : FCC_VAL<25>; // Equal
238 def FCC_UE : FCC_VAL<24>; // Unordered or Equal
239 def FCC_GE : FCC_VAL<25>; // Greater or Equal
240 def FCC_UGE : FCC_VAL<26>; // Unordered or Greater or Equal
241 def FCC_LE : FCC_VAL<27>; // Less or Equal
242 def FCC_ULE : FCC_VAL<28>; // Unordered or Less or Equal
243 def FCC_O : FCC_VAL<29>; // Ordered
245 //===----------------------------------------------------------------------===//
246 // Instruction Class Templates
247 //===----------------------------------------------------------------------===//
249 /// F3_12 multiclass - Define a normal F3_1/F3_2 pattern in one shot.
250 multiclass F3_12<string OpcStr, bits<6> Op3Val, SDNode OpNode,
251 RegisterClass RC, ValueType Ty, Operand immOp> {
252 def rr : F3_1<2, Op3Val,
253 (outs RC:$rd), (ins RC:$rs1, RC:$rs2),
254 !strconcat(OpcStr, " $rs1, $rs2, $rd"),
255 [(set Ty:$rd, (OpNode Ty:$rs1, Ty:$rs2))]>;
256 def ri : F3_2<2, Op3Val,
257 (outs RC:$rd), (ins RC:$rs1, immOp:$simm13),
258 !strconcat(OpcStr, " $rs1, $simm13, $rd"),
259 [(set Ty:$rd, (OpNode Ty:$rs1, (Ty simm13:$simm13)))]>;
262 /// F3_12np multiclass - Define a normal F3_1/F3_2 pattern in one shot, with no
264 multiclass F3_12np<string OpcStr, bits<6> Op3Val> {
265 def rr : F3_1<2, Op3Val,
266 (outs IntRegs:$rd), (ins IntRegs:$rs1, IntRegs:$rs2),
267 !strconcat(OpcStr, " $rs1, $rs2, $rd"), []>;
268 def ri : F3_2<2, Op3Val,
269 (outs IntRegs:$rd), (ins IntRegs:$rs1, simm13Op:$simm13),
270 !strconcat(OpcStr, " $rs1, $simm13, $rd"), []>;
273 // Load multiclass - Define both Reg+Reg/Reg+Imm patterns in one shot.
274 multiclass Load<string OpcStr, bits<6> Op3Val, SDPatternOperator OpNode,
275 RegisterClass RC, ValueType Ty> {
276 def rr : F3_1<3, Op3Val,
277 (outs RC:$dst), (ins MEMrr:$addr),
278 !strconcat(OpcStr, " [$addr], $dst"),
279 [(set Ty:$dst, (OpNode ADDRrr:$addr))]>;
280 def ri : F3_2<3, Op3Val,
281 (outs RC:$dst), (ins MEMri:$addr),
282 !strconcat(OpcStr, " [$addr], $dst"),
283 [(set Ty:$dst, (OpNode ADDRri:$addr))]>;
286 // Store multiclass - Define both Reg+Reg/Reg+Imm patterns in one shot.
287 multiclass Store<string OpcStr, bits<6> Op3Val, SDPatternOperator OpNode,
288 RegisterClass RC, ValueType Ty> {
289 def rr : F3_1<3, Op3Val,
290 (outs), (ins MEMrr:$addr, RC:$rd),
291 !strconcat(OpcStr, " $rd, [$addr]"),
292 [(OpNode Ty:$rd, ADDRrr:$addr)]>;
293 def ri : F3_2<3, Op3Val,
294 (outs), (ins MEMri:$addr, RC:$rd),
295 !strconcat(OpcStr, " $rd, [$addr]"),
296 [(OpNode Ty:$rd, ADDRri:$addr)]>;
299 //===----------------------------------------------------------------------===//
301 //===----------------------------------------------------------------------===//
303 // Pseudo instructions.
304 class Pseudo<dag outs, dag ins, string asmstr, list<dag> pattern>
305 : InstSP<outs, ins, asmstr, pattern> {
306 let isCodeGenOnly = 1;
312 def GETPCX : Pseudo<(outs getPCX:$getpcseq), (ins), "$getpcseq", [] >;
315 let Defs = [O6], Uses = [O6] in {
316 def ADJCALLSTACKDOWN : Pseudo<(outs), (ins i32imm:$amt),
317 "!ADJCALLSTACKDOWN $amt",
318 [(callseq_start timm:$amt)]>;
319 def ADJCALLSTACKUP : Pseudo<(outs), (ins i32imm:$amt1, i32imm:$amt2),
320 "!ADJCALLSTACKUP $amt1",
321 [(callseq_end timm:$amt1, timm:$amt2)]>;
324 let hasSideEffects = 1, mayStore = 1 in {
325 let rd = 0, rs1 = 0, rs2 = 0 in
326 def FLUSHW : F3_1<0b10, 0b101011, (outs), (ins),
328 [(flushw)]>, Requires<[HasV9]>;
329 let rd = 0, rs1 = 1, simm13 = 3 in
330 def TA3 : F3_2<0b10, 0b111010, (outs), (ins),
335 let isBarrier = 1, isTerminator = 1, rd = 0b01000, rs1 = 0, simm13 = 5 in
336 def TA5 : F3_2<0b10, 0b111010, (outs), (ins), "ta 5", [(trap)]>;
339 def UNIMP : F2_1<0b000, (outs), (ins i32imm:$imm22),
342 // SELECT_CC_* - Used to implement the SELECT_CC DAG operation. Expanded after
343 // instruction selection into a branch sequence. This has to handle all
344 // permutations of selection between i32/f32/f64 on ICC and FCC.
345 // Expanded after instruction selection.
346 let Uses = [ICC], usesCustomInserter = 1 in {
347 def SELECT_CC_Int_ICC
348 : Pseudo<(outs IntRegs:$dst), (ins IntRegs:$T, IntRegs:$F, i32imm:$Cond),
349 "; SELECT_CC_Int_ICC PSEUDO!",
350 [(set i32:$dst, (SPselecticc i32:$T, i32:$F, imm:$Cond))]>;
352 : Pseudo<(outs FPRegs:$dst), (ins FPRegs:$T, FPRegs:$F, i32imm:$Cond),
353 "; SELECT_CC_FP_ICC PSEUDO!",
354 [(set f32:$dst, (SPselecticc f32:$T, f32:$F, imm:$Cond))]>;
356 def SELECT_CC_DFP_ICC
357 : Pseudo<(outs DFPRegs:$dst), (ins DFPRegs:$T, DFPRegs:$F, i32imm:$Cond),
358 "; SELECT_CC_DFP_ICC PSEUDO!",
359 [(set f64:$dst, (SPselecticc f64:$T, f64:$F, imm:$Cond))]>;
361 def SELECT_CC_QFP_ICC
362 : Pseudo<(outs QFPRegs:$dst), (ins QFPRegs:$T, QFPRegs:$F, i32imm:$Cond),
363 "; SELECT_CC_QFP_ICC PSEUDO!",
364 [(set f128:$dst, (SPselecticc f128:$T, f128:$F, imm:$Cond))]>;
367 let usesCustomInserter = 1, Uses = [FCC0] in {
369 def SELECT_CC_Int_FCC
370 : Pseudo<(outs IntRegs:$dst), (ins IntRegs:$T, IntRegs:$F, i32imm:$Cond),
371 "; SELECT_CC_Int_FCC PSEUDO!",
372 [(set i32:$dst, (SPselectfcc i32:$T, i32:$F, imm:$Cond))]>;
375 : Pseudo<(outs FPRegs:$dst), (ins FPRegs:$T, FPRegs:$F, i32imm:$Cond),
376 "; SELECT_CC_FP_FCC PSEUDO!",
377 [(set f32:$dst, (SPselectfcc f32:$T, f32:$F, imm:$Cond))]>;
378 def SELECT_CC_DFP_FCC
379 : Pseudo<(outs DFPRegs:$dst), (ins DFPRegs:$T, DFPRegs:$F, i32imm:$Cond),
380 "; SELECT_CC_DFP_FCC PSEUDO!",
381 [(set f64:$dst, (SPselectfcc f64:$T, f64:$F, imm:$Cond))]>;
382 def SELECT_CC_QFP_FCC
383 : Pseudo<(outs QFPRegs:$dst), (ins QFPRegs:$T, QFPRegs:$F, i32imm:$Cond),
384 "; SELECT_CC_QFP_FCC PSEUDO!",
385 [(set f128:$dst, (SPselectfcc f128:$T, f128:$F, imm:$Cond))]>;
389 let isTerminator = 1, hasDelaySlot = 1, isBarrier = 1,
390 DecoderMethod = "DecodeJMPL" in {
391 def JMPLrr: F3_1<2, 0b111000, (outs IntRegs:$dst), (ins MEMrr:$addr),
392 "jmpl $addr, $dst", []>;
393 def JMPLri: F3_2<2, 0b111000, (outs IntRegs:$dst), (ins MEMri:$addr),
394 "jmpl $addr, $dst", []>;
397 // Section A.3 - Synthetic Instructions, p. 85
398 // special cases of JMPL:
399 let isReturn = 1, isTerminator = 1, hasDelaySlot = 1, isBarrier = 1,
400 isCodeGenOnly = 1 in {
401 let rd = 0, rs1 = 15 in
402 def RETL: F3_2<2, 0b111000, (outs), (ins i32imm:$val),
403 "jmp %o7+$val", [(retflag simm13:$val)]>;
405 let rd = 0, rs1 = 31 in
406 def RET: F3_2<2, 0b111000, (outs), (ins i32imm:$val),
410 let isReturn = 1, isTerminator = 1, hasDelaySlot = 1,
411 isBarrier = 1, rd = 0, DecoderMethod = "DecodeReturn" in {
412 def RETTrr : F3_1<2, 0b111001, (outs), (ins MEMrr:$addr),
414 def RETTri : F3_2<2, 0b111001, (outs), (ins MEMri:$addr),
418 // Section B.1 - Load Integer Instructions, p. 90
419 let DecoderMethod = "DecodeLoadInt" in {
420 defm LDSB : Load<"ldsb", 0b001001, sextloadi8, IntRegs, i32>;
421 defm LDSH : Load<"ldsh", 0b001010, sextloadi16, IntRegs, i32>;
422 defm LDUB : Load<"ldub", 0b000001, zextloadi8, IntRegs, i32>;
423 defm LDUH : Load<"lduh", 0b000010, zextloadi16, IntRegs, i32>;
424 defm LD : Load<"ld", 0b000000, load, IntRegs, i32>;
427 // Section B.2 - Load Floating-point Instructions, p. 92
428 let DecoderMethod = "DecodeLoadFP" in
429 defm LDF : Load<"ld", 0b100000, load, FPRegs, f32>;
430 let DecoderMethod = "DecodeLoadDFP" in
431 defm LDDF : Load<"ldd", 0b100011, load, DFPRegs, f64>;
432 let DecoderMethod = "DecodeLoadQFP" in
433 defm LDQF : Load<"ldq", 0b100010, load, QFPRegs, f128>,
434 Requires<[HasV9, HasHardQuad]>;
436 // Section B.4 - Store Integer Instructions, p. 95
437 let DecoderMethod = "DecodeStoreInt" in {
438 defm STB : Store<"stb", 0b000101, truncstorei8, IntRegs, i32>;
439 defm STH : Store<"sth", 0b000110, truncstorei16, IntRegs, i32>;
440 defm ST : Store<"st", 0b000100, store, IntRegs, i32>;
443 // Section B.5 - Store Floating-point Instructions, p. 97
444 let DecoderMethod = "DecodeStoreFP" in
445 defm STF : Store<"st", 0b100100, store, FPRegs, f32>;
446 let DecoderMethod = "DecodeStoreDFP" in
447 defm STDF : Store<"std", 0b100111, store, DFPRegs, f64>;
448 let DecoderMethod = "DecodeStoreQFP" in
449 defm STQF : Store<"stq", 0b100110, store, QFPRegs, f128>,
450 Requires<[HasV9, HasHardQuad]>;
452 // Section B.9 - SETHI Instruction, p. 104
453 def SETHIi: F2_1<0b100,
454 (outs IntRegs:$rd), (ins i32imm:$imm22),
456 [(set i32:$rd, SETHIimm:$imm22)]>;
458 // Section B.10 - NOP Instruction, p. 105
459 // (It's a special case of SETHI)
460 let rd = 0, imm22 = 0 in
461 def NOP : F2_1<0b100, (outs), (ins), "nop", []>;
463 // Section B.11 - Logical Instructions, p. 106
464 defm AND : F3_12<"and", 0b000001, and, IntRegs, i32, simm13Op>;
466 def ANDNrr : F3_1<2, 0b000101,
467 (outs IntRegs:$rd), (ins IntRegs:$rs1, IntRegs:$rs2),
468 "andn $rs1, $rs2, $rd",
469 [(set i32:$rd, (and i32:$rs1, (not i32:$rs2)))]>;
470 def ANDNri : F3_2<2, 0b000101,
471 (outs IntRegs:$rd), (ins IntRegs:$rs1, simm13Op:$simm13),
472 "andn $rs1, $simm13, $rd", []>;
474 defm OR : F3_12<"or", 0b000010, or, IntRegs, i32, simm13Op>;
476 def ORNrr : F3_1<2, 0b000110,
477 (outs IntRegs:$rd), (ins IntRegs:$rs1, IntRegs:$rs2),
478 "orn $rs1, $rs2, $rd",
479 [(set i32:$rd, (or i32:$rs1, (not i32:$rs2)))]>;
480 def ORNri : F3_2<2, 0b000110,
481 (outs IntRegs:$rd), (ins IntRegs:$rs1, simm13Op:$simm13),
482 "orn $rs1, $simm13, $rd", []>;
483 defm XOR : F3_12<"xor", 0b000011, xor, IntRegs, i32, simm13Op>;
485 def XNORrr : F3_1<2, 0b000111,
486 (outs IntRegs:$rd), (ins IntRegs:$rs1, IntRegs:$rs2),
487 "xnor $rs1, $rs2, $rd",
488 [(set i32:$rd, (not (xor i32:$rs1, i32:$rs2)))]>;
489 def XNORri : F3_2<2, 0b000111,
490 (outs IntRegs:$rd), (ins IntRegs:$rs1, simm13Op:$simm13),
491 "xnor $rs1, $simm13, $rd", []>;
493 let Defs = [ICC] in {
494 defm ANDCC : F3_12np<"andcc", 0b010001>;
495 defm ANDNCC : F3_12np<"andncc", 0b010101>;
496 defm ORCC : F3_12np<"orcc", 0b010010>;
497 defm ORNCC : F3_12np<"orncc", 0b010110>;
498 defm XORCC : F3_12np<"xorcc", 0b010011>;
499 defm XNORCC : F3_12np<"xnorcc", 0b010111>;
502 // Section B.12 - Shift Instructions, p. 107
503 defm SLL : F3_12<"sll", 0b100101, shl, IntRegs, i32, simm13Op>;
504 defm SRL : F3_12<"srl", 0b100110, srl, IntRegs, i32, simm13Op>;
505 defm SRA : F3_12<"sra", 0b100111, sra, IntRegs, i32, simm13Op>;
507 // Section B.13 - Add Instructions, p. 108
508 defm ADD : F3_12<"add", 0b000000, add, IntRegs, i32, simm13Op>;
510 // "LEA" forms of add (patterns to make tblgen happy)
511 let Predicates = [Is32Bit], isCodeGenOnly = 1 in
512 def LEA_ADDri : F3_2<2, 0b000000,
513 (outs IntRegs:$dst), (ins MEMri:$addr),
514 "add ${addr:arith}, $dst",
515 [(set iPTR:$dst, ADDRri:$addr)]>;
518 defm ADDCC : F3_12<"addcc", 0b010000, addc, IntRegs, i32, simm13Op>;
521 defm ADDC : F3_12np<"addx", 0b001000>;
523 let Uses = [ICC], Defs = [ICC] in
524 defm ADDE : F3_12<"addxcc", 0b011000, adde, IntRegs, i32, simm13Op>;
526 // Section B.15 - Subtract Instructions, p. 110
527 defm SUB : F3_12 <"sub" , 0b000100, sub, IntRegs, i32, simm13Op>;
528 let Uses = [ICC], Defs = [ICC] in
529 defm SUBE : F3_12 <"subxcc" , 0b011100, sube, IntRegs, i32, simm13Op>;
532 defm SUBCC : F3_12 <"subcc", 0b010100, subc, IntRegs, i32, simm13Op>;
535 defm SUBC : F3_12np <"subx", 0b001100>;
537 let Defs = [ICC], rd = 0 in {
538 def CMPrr : F3_1<2, 0b010100,
539 (outs), (ins IntRegs:$rs1, IntRegs:$rs2),
541 [(SPcmpicc i32:$rs1, i32:$rs2)]>;
542 def CMPri : F3_2<2, 0b010100,
543 (outs), (ins IntRegs:$rs1, simm13Op:$simm13),
545 [(SPcmpicc i32:$rs1, (i32 simm13:$simm13))]>;
548 // Section B.18 - Multiply Instructions, p. 113
550 defm UMUL : F3_12np<"umul", 0b001010>;
551 defm SMUL : F3_12 <"smul", 0b001011, mul, IntRegs, i32, simm13Op>;
554 let Defs = [Y, ICC] in {
555 defm UMULCC : F3_12np<"umulcc", 0b011010>;
556 defm SMULCC : F3_12np<"smulcc", 0b011011>;
559 // Section B.19 - Divide Instructions, p. 115
561 defm UDIV : F3_12np<"udiv", 0b001110>;
562 defm SDIV : F3_12np<"sdiv", 0b001111>;
565 let Defs = [Y, ICC] in {
566 defm UDIVCC : F3_12np<"udivcc", 0b011110>;
567 defm SDIVCC : F3_12np<"sdivcc", 0b011111>;
570 // Section B.20 - SAVE and RESTORE, p. 117
571 defm SAVE : F3_12np<"save" , 0b111100>;
572 defm RESTORE : F3_12np<"restore", 0b111101>;
574 // Section B.21 - Branch on Integer Condition Codes Instructions, p. 119
576 // unconditional branch class.
577 class BranchAlways<dag ins, string asmstr, list<dag> pattern>
578 : F2_2<0b010, 0, (outs), ins, asmstr, pattern> {
580 let isTerminator = 1;
581 let hasDelaySlot = 1;
586 def BA : BranchAlways<(ins brtarget:$imm22), "ba $imm22", [(br bb:$imm22)]>;
589 let isBranch = 1, isTerminator = 1, hasDelaySlot = 1 in {
591 // conditional branch class:
592 class BranchSP<dag ins, string asmstr, list<dag> pattern>
593 : F2_2<0b010, 0, (outs), ins, asmstr, pattern>;
595 // conditional branch with annul class:
596 class BranchSPA<dag ins, string asmstr, list<dag> pattern>
597 : F2_2<0b010, 1, (outs), ins, asmstr, pattern>;
599 // Conditional branch class on %icc|%xcc with predication:
600 multiclass IPredBranch<string regstr, list<dag> CCPattern> {
601 def CC : F2_3<0b001, 0, 1, (outs), (ins bprtarget:$imm19, CCOp:$cond),
602 !strconcat("b$cond ", !strconcat(regstr, ", $imm19")),
604 def CCA : F2_3<0b001, 1, 1, (outs), (ins bprtarget:$imm19, CCOp:$cond),
605 !strconcat("b$cond,a ", !strconcat(regstr, ", $imm19")),
607 def CCNT : F2_3<0b001, 0, 0, (outs), (ins bprtarget:$imm19, CCOp:$cond),
608 !strconcat("b$cond,pn ", !strconcat(regstr, ", $imm19")),
610 def CCANT : F2_3<0b001, 1, 0, (outs), (ins bprtarget:$imm19, CCOp:$cond),
611 !strconcat("b$cond,a,pn ", !strconcat(regstr, ", $imm19")),
615 } // let isBranch = 1, isTerminator = 1, hasDelaySlot = 1
618 // Indirect branch instructions.
619 let isTerminator = 1, isBarrier = 1, hasDelaySlot = 1, isBranch =1,
620 isIndirectBranch = 1, rd = 0, isCodeGenOnly = 1 in {
621 def BINDrr : F3_1<2, 0b111000,
622 (outs), (ins MEMrr:$ptr),
624 [(brind ADDRrr:$ptr)]>;
625 def BINDri : F3_2<2, 0b111000,
626 (outs), (ins MEMri:$ptr),
628 [(brind ADDRri:$ptr)]>;
631 let Uses = [ICC] in {
632 def BCOND : BranchSP<(ins brtarget:$imm22, CCOp:$cond),
634 [(SPbricc bb:$imm22, imm:$cond)]>;
635 def BCONDA : BranchSPA<(ins brtarget:$imm22, CCOp:$cond),
636 "b$cond,a $imm22", []>;
638 let Predicates = [HasV9], cc = 0b00 in
639 defm BPI : IPredBranch<"%icc", []>;
642 // Section B.22 - Branch on Floating-point Condition Codes Instructions, p. 121
644 let isBranch = 1, isTerminator = 1, hasDelaySlot = 1 in {
646 // floating-point conditional branch class:
647 class FPBranchSP<dag ins, string asmstr, list<dag> pattern>
648 : F2_2<0b110, 0, (outs), ins, asmstr, pattern>;
650 // floating-point conditional branch with annul class:
651 class FPBranchSPA<dag ins, string asmstr, list<dag> pattern>
652 : F2_2<0b110, 1, (outs), ins, asmstr, pattern>;
654 // Conditional branch class on %fcc0-%fcc3 with predication:
655 multiclass FPredBranch {
656 def CC : F2_3<0b101, 0, 1, (outs), (ins bprtarget:$imm19, CCOp:$cond,
658 "fb$cond $cc, $imm19", []>;
659 def CCA : F2_3<0b101, 1, 1, (outs), (ins bprtarget:$imm19, CCOp:$cond,
661 "fb$cond,a $cc, $imm19", []>;
662 def CCNT : F2_3<0b101, 0, 0, (outs), (ins bprtarget:$imm19, CCOp:$cond,
664 "fb$cond,pn $cc, $imm19", []>;
665 def CCANT : F2_3<0b101, 1, 0, (outs), (ins bprtarget:$imm19, CCOp:$cond,
667 "fb$cond,a,pn $cc, $imm19", []>;
669 } // let isBranch = 1, isTerminator = 1, hasDelaySlot = 1
671 let Uses = [FCC0] in {
672 def FBCOND : FPBranchSP<(ins brtarget:$imm22, CCOp:$cond),
674 [(SPbrfcc bb:$imm22, imm:$cond)]>;
675 def FBCONDA : FPBranchSPA<(ins brtarget:$imm22, CCOp:$cond),
676 "fb$cond,a $imm22", []>;
679 let Predicates = [HasV9] in
680 defm BPF : FPredBranch;
683 // Section B.24 - Call and Link Instruction, p. 125
684 // This is the only Format 1 instruction
686 hasDelaySlot = 1, isCall = 1 in {
687 def CALL : InstSP<(outs), (ins calltarget:$disp, variable_ops),
691 let Inst{29-0} = disp;
694 // indirect calls: special cases of JMPL.
695 let isCodeGenOnly = 1, rd = 15 in {
696 def CALLrr : F3_1<2, 0b111000,
697 (outs), (ins MEMrr:$ptr, variable_ops),
699 [(call ADDRrr:$ptr)]>;
700 def CALLri : F3_2<2, 0b111000,
701 (outs), (ins MEMri:$ptr, variable_ops),
703 [(call ADDRri:$ptr)]>;
707 // Section B.28 - Read State Register Instructions
708 let Uses = [Y], rs1 = 0, rs2 = 0 in
709 def RDY : F3_1<2, 0b101000,
710 (outs IntRegs:$dst), (ins),
713 // Section B.29 - Write State Register Instructions
714 let Defs = [Y], rd = 0 in {
715 def WRYrr : F3_1<2, 0b110000,
716 (outs), (ins IntRegs:$rs1, IntRegs:$rs2),
717 "wr $rs1, $rs2, %y", []>;
718 def WRYri : F3_2<2, 0b110000,
719 (outs), (ins IntRegs:$rs1, simm13Op:$simm13),
720 "wr $rs1, $simm13, %y", []>;
722 // Convert Integer to Floating-point Instructions, p. 141
723 def FITOS : F3_3u<2, 0b110100, 0b011000100,
724 (outs FPRegs:$rd), (ins FPRegs:$rs2),
726 [(set FPRegs:$rd, (SPitof FPRegs:$rs2))]>;
727 def FITOD : F3_3u<2, 0b110100, 0b011001000,
728 (outs DFPRegs:$rd), (ins FPRegs:$rs2),
730 [(set DFPRegs:$rd, (SPitof FPRegs:$rs2))]>;
731 def FITOQ : F3_3u<2, 0b110100, 0b011001100,
732 (outs QFPRegs:$rd), (ins FPRegs:$rs2),
734 [(set QFPRegs:$rd, (SPitof FPRegs:$rs2))]>,
735 Requires<[HasHardQuad]>;
737 // Convert Floating-point to Integer Instructions, p. 142
738 def FSTOI : F3_3u<2, 0b110100, 0b011010001,
739 (outs FPRegs:$rd), (ins FPRegs:$rs2),
741 [(set FPRegs:$rd, (SPftoi FPRegs:$rs2))]>;
742 def FDTOI : F3_3u<2, 0b110100, 0b011010010,
743 (outs FPRegs:$rd), (ins DFPRegs:$rs2),
745 [(set FPRegs:$rd, (SPftoi DFPRegs:$rs2))]>;
746 def FQTOI : F3_3u<2, 0b110100, 0b011010011,
747 (outs FPRegs:$rd), (ins QFPRegs:$rs2),
749 [(set FPRegs:$rd, (SPftoi QFPRegs:$rs2))]>,
750 Requires<[HasHardQuad]>;
752 // Convert between Floating-point Formats Instructions, p. 143
753 def FSTOD : F3_3u<2, 0b110100, 0b011001001,
754 (outs DFPRegs:$rd), (ins FPRegs:$rs2),
756 [(set f64:$rd, (fextend f32:$rs2))]>;
757 def FSTOQ : F3_3u<2, 0b110100, 0b011001101,
758 (outs QFPRegs:$rd), (ins FPRegs:$rs2),
760 [(set f128:$rd, (fextend f32:$rs2))]>,
761 Requires<[HasHardQuad]>;
762 def FDTOS : F3_3u<2, 0b110100, 0b011000110,
763 (outs FPRegs:$rd), (ins DFPRegs:$rs2),
765 [(set f32:$rd, (fround f64:$rs2))]>;
766 def FDTOQ : F3_3u<2, 0b110100, 0b011001110,
767 (outs QFPRegs:$rd), (ins DFPRegs:$rs2),
769 [(set f128:$rd, (fextend f64:$rs2))]>,
770 Requires<[HasHardQuad]>;
771 def FQTOS : F3_3u<2, 0b110100, 0b011000111,
772 (outs FPRegs:$rd), (ins QFPRegs:$rs2),
774 [(set f32:$rd, (fround f128:$rs2))]>,
775 Requires<[HasHardQuad]>;
776 def FQTOD : F3_3u<2, 0b110100, 0b011001011,
777 (outs DFPRegs:$rd), (ins QFPRegs:$rs2),
779 [(set f64:$rd, (fround f128:$rs2))]>,
780 Requires<[HasHardQuad]>;
782 // Floating-point Move Instructions, p. 144
783 def FMOVS : F3_3u<2, 0b110100, 0b000000001,
784 (outs FPRegs:$rd), (ins FPRegs:$rs2),
785 "fmovs $rs2, $rd", []>;
786 def FNEGS : F3_3u<2, 0b110100, 0b000000101,
787 (outs FPRegs:$rd), (ins FPRegs:$rs2),
789 [(set f32:$rd, (fneg f32:$rs2))]>;
790 def FABSS : F3_3u<2, 0b110100, 0b000001001,
791 (outs FPRegs:$rd), (ins FPRegs:$rs2),
793 [(set f32:$rd, (fabs f32:$rs2))]>;
796 // Floating-point Square Root Instructions, p.145
797 def FSQRTS : F3_3u<2, 0b110100, 0b000101001,
798 (outs FPRegs:$rd), (ins FPRegs:$rs2),
800 [(set f32:$rd, (fsqrt f32:$rs2))]>;
801 def FSQRTD : F3_3u<2, 0b110100, 0b000101010,
802 (outs DFPRegs:$rd), (ins DFPRegs:$rs2),
804 [(set f64:$rd, (fsqrt f64:$rs2))]>;
805 def FSQRTQ : F3_3u<2, 0b110100, 0b000101011,
806 (outs QFPRegs:$rd), (ins QFPRegs:$rs2),
808 [(set f128:$rd, (fsqrt f128:$rs2))]>,
809 Requires<[HasHardQuad]>;
813 // Floating-point Add and Subtract Instructions, p. 146
814 def FADDS : F3_3<2, 0b110100, 0b001000001,
815 (outs FPRegs:$rd), (ins FPRegs:$rs1, FPRegs:$rs2),
816 "fadds $rs1, $rs2, $rd",
817 [(set f32:$rd, (fadd f32:$rs1, f32:$rs2))]>;
818 def FADDD : F3_3<2, 0b110100, 0b001000010,
819 (outs DFPRegs:$rd), (ins DFPRegs:$rs1, DFPRegs:$rs2),
820 "faddd $rs1, $rs2, $rd",
821 [(set f64:$rd, (fadd f64:$rs1, f64:$rs2))]>;
822 def FADDQ : F3_3<2, 0b110100, 0b001000011,
823 (outs QFPRegs:$rd), (ins QFPRegs:$rs1, QFPRegs:$rs2),
824 "faddq $rs1, $rs2, $rd",
825 [(set f128:$rd, (fadd f128:$rs1, f128:$rs2))]>,
826 Requires<[HasHardQuad]>;
828 def FSUBS : F3_3<2, 0b110100, 0b001000101,
829 (outs FPRegs:$rd), (ins FPRegs:$rs1, FPRegs:$rs2),
830 "fsubs $rs1, $rs2, $rd",
831 [(set f32:$rd, (fsub f32:$rs1, f32:$rs2))]>;
832 def FSUBD : F3_3<2, 0b110100, 0b001000110,
833 (outs DFPRegs:$rd), (ins DFPRegs:$rs1, DFPRegs:$rs2),
834 "fsubd $rs1, $rs2, $rd",
835 [(set f64:$rd, (fsub f64:$rs1, f64:$rs2))]>;
836 def FSUBQ : F3_3<2, 0b110100, 0b001000111,
837 (outs QFPRegs:$rd), (ins QFPRegs:$rs1, QFPRegs:$rs2),
838 "fsubq $rs1, $rs2, $rd",
839 [(set f128:$rd, (fsub f128:$rs1, f128:$rs2))]>,
840 Requires<[HasHardQuad]>;
843 // Floating-point Multiply and Divide Instructions, p. 147
844 def FMULS : F3_3<2, 0b110100, 0b001001001,
845 (outs FPRegs:$rd), (ins FPRegs:$rs1, FPRegs:$rs2),
846 "fmuls $rs1, $rs2, $rd",
847 [(set f32:$rd, (fmul f32:$rs1, f32:$rs2))]>;
848 def FMULD : F3_3<2, 0b110100, 0b001001010,
849 (outs DFPRegs:$rd), (ins DFPRegs:$rs1, DFPRegs:$rs2),
850 "fmuld $rs1, $rs2, $rd",
851 [(set f64:$rd, (fmul f64:$rs1, f64:$rs2))]>;
852 def FMULQ : F3_3<2, 0b110100, 0b001001011,
853 (outs QFPRegs:$rd), (ins QFPRegs:$rs1, QFPRegs:$rs2),
854 "fmulq $rs1, $rs2, $rd",
855 [(set f128:$rd, (fmul f128:$rs1, f128:$rs2))]>,
856 Requires<[HasHardQuad]>;
858 def FSMULD : F3_3<2, 0b110100, 0b001101001,
859 (outs DFPRegs:$rd), (ins FPRegs:$rs1, FPRegs:$rs2),
860 "fsmuld $rs1, $rs2, $rd",
861 [(set f64:$rd, (fmul (fextend f32:$rs1),
862 (fextend f32:$rs2)))]>;
863 def FDMULQ : F3_3<2, 0b110100, 0b001101110,
864 (outs QFPRegs:$rd), (ins DFPRegs:$rs1, DFPRegs:$rs2),
865 "fdmulq $rs1, $rs2, $rd",
866 [(set f128:$rd, (fmul (fextend f64:$rs1),
867 (fextend f64:$rs2)))]>,
868 Requires<[HasHardQuad]>;
870 def FDIVS : F3_3<2, 0b110100, 0b001001101,
871 (outs FPRegs:$rd), (ins FPRegs:$rs1, FPRegs:$rs2),
872 "fdivs $rs1, $rs2, $rd",
873 [(set f32:$rd, (fdiv f32:$rs1, f32:$rs2))]>;
874 def FDIVD : F3_3<2, 0b110100, 0b001001110,
875 (outs DFPRegs:$rd), (ins DFPRegs:$rs1, DFPRegs:$rs2),
876 "fdivd $rs1, $rs2, $rd",
877 [(set f64:$rd, (fdiv f64:$rs1, f64:$rs2))]>;
878 def FDIVQ : F3_3<2, 0b110100, 0b001001111,
879 (outs QFPRegs:$rd), (ins QFPRegs:$rs1, QFPRegs:$rs2),
880 "fdivq $rs1, $rs2, $rd",
881 [(set f128:$rd, (fdiv f128:$rs1, f128:$rs2))]>,
882 Requires<[HasHardQuad]>;
884 // Floating-point Compare Instructions, p. 148
885 // Note: the 2nd template arg is different for these guys.
886 // Note 2: the result of a FCMP is not available until the 2nd cycle
887 // after the instr is retired, but there is no interlock in Sparc V8.
888 // This behavior is modeled with a forced noop after the instruction in
891 let Defs = [FCC0], rd = 0, isCodeGenOnly = 1 in {
892 def FCMPS : F3_3c<2, 0b110101, 0b001010001,
893 (outs), (ins FPRegs:$rs1, FPRegs:$rs2),
895 [(SPcmpfcc f32:$rs1, f32:$rs2)]>;
896 def FCMPD : F3_3c<2, 0b110101, 0b001010010,
897 (outs), (ins DFPRegs:$rs1, DFPRegs:$rs2),
899 [(SPcmpfcc f64:$rs1, f64:$rs2)]>;
900 def FCMPQ : F3_3c<2, 0b110101, 0b001010011,
901 (outs), (ins QFPRegs:$rs1, QFPRegs:$rs2),
903 [(SPcmpfcc f128:$rs1, f128:$rs2)]>,
904 Requires<[HasHardQuad]>;
907 //===----------------------------------------------------------------------===//
908 // Instructions for Thread Local Storage(TLS).
909 //===----------------------------------------------------------------------===//
910 let isCodeGenOnly = 1, isAsmParserOnly = 1 in {
911 def TLS_ADDrr : F3_1<2, 0b000000,
913 (ins IntRegs:$rs1, IntRegs:$rs2, TLSSym:$sym),
914 "add $rs1, $rs2, $rd, $sym",
916 (tlsadd i32:$rs1, i32:$rs2, tglobaltlsaddr:$sym))]>;
919 def TLS_LDrr : F3_1<3, 0b000000,
920 (outs IntRegs:$dst), (ins MEMrr:$addr, TLSSym:$sym),
921 "ld [$addr], $dst, $sym",
923 (tlsld ADDRrr:$addr, tglobaltlsaddr:$sym))]>;
925 let Uses = [O6], isCall = 1, hasDelaySlot = 1 in
926 def TLS_CALL : InstSP<(outs),
927 (ins calltarget:$disp, TLSSym:$sym, variable_ops),
929 [(tlscall texternalsym:$disp, tglobaltlsaddr:$sym)]> {
932 let Inst{29-0} = disp;
936 //===----------------------------------------------------------------------===//
938 //===----------------------------------------------------------------------===//
940 // V9 Conditional Moves.
941 let Predicates = [HasV9], Constraints = "$f = $rd" in {
942 // Move Integer Register on Condition (MOVcc) p. 194 of the V9 manual.
943 let Uses = [ICC], intcc = 1, cc = 0b00 in {
945 : F4_1<0b101100, (outs IntRegs:$rd),
946 (ins IntRegs:$rs2, IntRegs:$f, CCOp:$cond),
947 "mov$cond %icc, $rs2, $rd",
948 [(set i32:$rd, (SPselecticc i32:$rs2, i32:$f, imm:$cond))]>;
951 : F4_2<0b101100, (outs IntRegs:$rd),
952 (ins i32imm:$simm11, IntRegs:$f, CCOp:$cond),
953 "mov$cond %icc, $simm11, $rd",
955 (SPselecticc simm11:$simm11, i32:$f, imm:$cond))]>;
958 let Uses = [FCC0], intcc = 0, cc = 0b00 in {
960 : F4_1<0b101100, (outs IntRegs:$rd),
961 (ins IntRegs:$rs2, IntRegs:$f, CCOp:$cond),
962 "mov$cond %fcc0, $rs2, $rd",
963 [(set i32:$rd, (SPselectfcc i32:$rs2, i32:$f, imm:$cond))]>;
965 : F4_2<0b101100, (outs IntRegs:$rd),
966 (ins i32imm:$simm11, IntRegs:$f, CCOp:$cond),
967 "mov$cond %fcc0, $simm11, $rd",
969 (SPselectfcc simm11:$simm11, i32:$f, imm:$cond))]>;
972 let Uses = [ICC], intcc = 1, opf_cc = 0b00 in {
974 : F4_3<0b110101, 0b000001, (outs FPRegs:$rd),
975 (ins FPRegs:$rs2, FPRegs:$f, CCOp:$cond),
976 "fmovs$cond %icc, $rs2, $rd",
977 [(set f32:$rd, (SPselecticc f32:$rs2, f32:$f, imm:$cond))]>;
979 : F4_3<0b110101, 0b000010, (outs DFPRegs:$rd),
980 (ins DFPRegs:$rs2, DFPRegs:$f, CCOp:$cond),
981 "fmovd$cond %icc, $rs2, $rd",
982 [(set f64:$rd, (SPselecticc f64:$rs2, f64:$f, imm:$cond))]>;
984 : F4_3<0b110101, 0b000011, (outs QFPRegs:$rd),
985 (ins QFPRegs:$rs2, QFPRegs:$f, CCOp:$cond),
986 "fmovq$cond %icc, $rs2, $rd",
987 [(set f128:$rd, (SPselecticc f128:$rs2, f128:$f, imm:$cond))]>,
988 Requires<[HasHardQuad]>;
991 let Uses = [FCC0], intcc = 0, opf_cc = 0b00 in {
993 : F4_3<0b110101, 0b000001, (outs FPRegs:$rd),
994 (ins FPRegs:$rs2, FPRegs:$f, CCOp:$cond),
995 "fmovs$cond %fcc0, $rs2, $rd",
996 [(set f32:$rd, (SPselectfcc f32:$rs2, f32:$f, imm:$cond))]>;
998 : F4_3<0b110101, 0b000010, (outs DFPRegs:$rd),
999 (ins DFPRegs:$rs2, DFPRegs:$f, CCOp:$cond),
1000 "fmovd$cond %fcc0, $rs2, $rd",
1001 [(set f64:$rd, (SPselectfcc f64:$rs2, f64:$f, imm:$cond))]>;
1003 : F4_3<0b110101, 0b000011, (outs QFPRegs:$rd),
1004 (ins QFPRegs:$rs2, QFPRegs:$f, CCOp:$cond),
1005 "fmovq$cond %fcc0, $rs2, $rd",
1006 [(set f128:$rd, (SPselectfcc f128:$rs2, f128:$f, imm:$cond))]>,
1007 Requires<[HasHardQuad]>;
1012 // Floating-Point Move Instructions, p. 164 of the V9 manual.
1013 let Predicates = [HasV9] in {
1014 def FMOVD : F3_3u<2, 0b110100, 0b000000010,
1015 (outs DFPRegs:$rd), (ins DFPRegs:$rs2),
1016 "fmovd $rs2, $rd", []>;
1017 def FMOVQ : F3_3u<2, 0b110100, 0b000000011,
1018 (outs QFPRegs:$rd), (ins QFPRegs:$rs2),
1019 "fmovq $rs2, $rd", []>,
1020 Requires<[HasHardQuad]>;
1021 def FNEGD : F3_3u<2, 0b110100, 0b000000110,
1022 (outs DFPRegs:$rd), (ins DFPRegs:$rs2),
1024 [(set f64:$rd, (fneg f64:$rs2))]>;
1025 def FNEGQ : F3_3u<2, 0b110100, 0b000000111,
1026 (outs QFPRegs:$rd), (ins QFPRegs:$rs2),
1028 [(set f128:$rd, (fneg f128:$rs2))]>,
1029 Requires<[HasHardQuad]>;
1030 def FABSD : F3_3u<2, 0b110100, 0b000001010,
1031 (outs DFPRegs:$rd), (ins DFPRegs:$rs2),
1033 [(set f64:$rd, (fabs f64:$rs2))]>;
1034 def FABSQ : F3_3u<2, 0b110100, 0b000001011,
1035 (outs QFPRegs:$rd), (ins QFPRegs:$rs2),
1037 [(set f128:$rd, (fabs f128:$rs2))]>,
1038 Requires<[HasHardQuad]>;
1041 // Floating-point compare instruction with %fcc0-%fcc3.
1042 def V9FCMPS : F3_3c<2, 0b110101, 0b001010001,
1043 (outs FCCRegs:$rd), (ins FPRegs:$rs1, FPRegs:$rs2),
1044 "fcmps $rd, $rs1, $rs2", []>;
1045 def V9FCMPD : F3_3c<2, 0b110101, 0b001010010,
1046 (outs FCCRegs:$rd), (ins DFPRegs:$rs1, DFPRegs:$rs2),
1047 "fcmpd $rd, $rs1, $rs2", []>;
1048 def V9FCMPQ : F3_3c<2, 0b110101, 0b001010011,
1049 (outs FCCRegs:$rd), (ins QFPRegs:$rs1, QFPRegs:$rs2),
1050 "fcmpq $rd, $rs1, $rs2", []>,
1051 Requires<[HasHardQuad]>;
1053 let hasSideEffects = 1 in {
1054 def V9FCMPES : F3_3c<2, 0b110101, 0b001010101,
1055 (outs FCCRegs:$rd), (ins FPRegs:$rs1, FPRegs:$rs2),
1056 "fcmpes $rd, $rs1, $rs2", []>;
1057 def V9FCMPED : F3_3c<2, 0b110101, 0b001010110,
1058 (outs FCCRegs:$rd), (ins DFPRegs:$rs1, DFPRegs:$rs2),
1059 "fcmped $rd, $rs1, $rs2", []>;
1060 def V9FCMPEQ : F3_3c<2, 0b110101, 0b001010111,
1061 (outs FCCRegs:$rd), (ins QFPRegs:$rs1, QFPRegs:$rs2),
1062 "fcmpeq $rd, $rs1, $rs2", []>,
1063 Requires<[HasHardQuad]>;
1066 // Floating point conditional move instrucitons with %fcc0-%fcc3.
1067 let Predicates = [HasV9] in {
1068 let Constraints = "$f = $rd", intcc = 0 in {
1070 : F4_1<0b101100, (outs IntRegs:$rd),
1071 (ins FCCRegs:$cc, IntRegs:$rs2, IntRegs:$f, CCOp:$cond),
1072 "mov$cond $cc, $rs2, $rd", []>;
1074 : F4_2<0b101100, (outs IntRegs:$rd),
1075 (ins FCCRegs:$cc, i32imm:$simm11, IntRegs:$f, CCOp:$cond),
1076 "mov$cond $cc, $simm11, $rd", []>;
1078 : F4_3<0b110101, 0b000001, (outs FPRegs:$rd),
1079 (ins FCCRegs:$opf_cc, FPRegs:$rs2, FPRegs:$f, CCOp:$cond),
1080 "fmovs$cond $opf_cc, $rs2, $rd", []>;
1082 : F4_3<0b110101, 0b000010, (outs DFPRegs:$rd),
1083 (ins FCCRegs:$opf_cc, DFPRegs:$rs2, DFPRegs:$f, CCOp:$cond),
1084 "fmovd$cond $opf_cc, $rs2, $rd", []>;
1086 : F4_3<0b110101, 0b000011, (outs QFPRegs:$rd),
1087 (ins FCCRegs:$opf_cc, QFPRegs:$rs2, QFPRegs:$f, CCOp:$cond),
1088 "fmovq$cond $opf_cc, $rs2, $rd", []>,
1089 Requires<[HasHardQuad]>;
1090 } // Constraints = "$f = $rd", ...
1091 } // let Predicates = [hasV9]
1094 // POPCrr - This does a ctpop of a 64-bit register. As such, we have to clear
1095 // the top 32-bits before using it. To do this clearing, we use a SRLri X,0.
1097 def POPCrr : F3_1<2, 0b101110,
1098 (outs IntRegs:$dst), (ins IntRegs:$src),
1099 "popc $src, $dst", []>, Requires<[HasV9]>;
1100 def : Pat<(ctpop i32:$src),
1101 (POPCrr (SRLri $src, 0))>;
1104 let hasSideEffects =1, rd = 0, rs1 = 0b01111, rs2 = 0 in
1105 def STBAR : F3_1<2, 0b101000, (outs), (ins), "stbar", []>;
1107 let Predicates = [HasV9], hasSideEffects = 1, rd = 0, rs1 = 0b01111 in
1108 def MEMBARi : F3_2<2, 0b101000, (outs), (ins simm13Op:$simm13),
1109 "membar $simm13", []>;
1111 let Constraints = "$val = $dst", DecoderMethod = "DecodeSWAP" in {
1112 def SWAPrr : F3_1<3, 0b001111,
1113 (outs IntRegs:$dst), (ins MEMrr:$addr, IntRegs:$val),
1114 "swap [$addr], $dst",
1115 [(set i32:$dst, (atomic_swap_32 ADDRrr:$addr, i32:$val))]>;
1116 def SWAPri : F3_2<3, 0b001111,
1117 (outs IntRegs:$dst), (ins MEMri:$addr, IntRegs:$val),
1118 "swap [$addr], $dst",
1119 [(set i32:$dst, (atomic_swap_32 ADDRri:$addr, i32:$val))]>;
1122 let Predicates = [HasV9], Constraints = "$swap = $rd" in
1123 def CASrr: F3_1_asi<3, 0b111100, 0b10000000,
1124 (outs IntRegs:$rd), (ins IntRegs:$rs1, IntRegs:$rs2,
1126 "cas [$rs1], $rs2, $rd",
1128 (atomic_cmp_swap iPTR:$rs1, i32:$rs2, i32:$swap))]>;
1130 let Defs = [ICC] in {
1131 defm TADDCC : F3_12np<"taddcc", 0b100000>;
1132 defm TSUBCC : F3_12np<"tsubcc", 0b100001>;
1134 let hasSideEffects = 1 in {
1135 defm TADDCCTV : F3_12np<"taddcctv", 0b100010>;
1136 defm TSUBCCTV : F3_12np<"tsubcctv", 0b100011>;
1140 multiclass TRAP<string regStr> {
1141 def rr : TRAPSPrr<0b111010, (outs), (ins IntRegs:$rs1, IntRegs:$rs2,
1143 !strconcat(!strconcat("t$cond ", regStr), ", $rs1 + $rs2"), []>;
1144 def ri : TRAPSPri<0b111010, (outs), (ins IntRegs:$rs1, i32imm:$imm,
1146 !strconcat(!strconcat("t$cond ", regStr), ", $rs1 + $imm"), []>;
1149 let hasSideEffects = 1, Uses = [ICC], cc = 0b00 in
1150 defm TICC : TRAP<"%icc">;
1152 //===----------------------------------------------------------------------===//
1153 // Non-Instruction Patterns
1154 //===----------------------------------------------------------------------===//
1156 // Small immediates.
1157 def : Pat<(i32 simm13:$val),
1158 (ORri (i32 G0), imm:$val)>;
1159 // Arbitrary immediates.
1160 def : Pat<(i32 imm:$val),
1161 (ORri (SETHIi (HI22 imm:$val)), (LO10 imm:$val))>;
1164 // Global addresses, constant pool entries
1165 let Predicates = [Is32Bit] in {
1167 def : Pat<(SPhi tglobaladdr:$in), (SETHIi tglobaladdr:$in)>;
1168 def : Pat<(SPlo tglobaladdr:$in), (ORri (i32 G0), tglobaladdr:$in)>;
1169 def : Pat<(SPhi tconstpool:$in), (SETHIi tconstpool:$in)>;
1170 def : Pat<(SPlo tconstpool:$in), (ORri (i32 G0), tconstpool:$in)>;
1172 // GlobalTLS addresses
1173 def : Pat<(SPhi tglobaltlsaddr:$in), (SETHIi tglobaltlsaddr:$in)>;
1174 def : Pat<(SPlo tglobaltlsaddr:$in), (ORri (i32 G0), tglobaltlsaddr:$in)>;
1175 def : Pat<(add (SPhi tglobaltlsaddr:$in1), (SPlo tglobaltlsaddr:$in2)),
1176 (ADDri (SETHIi tglobaltlsaddr:$in1), (tglobaltlsaddr:$in2))>;
1177 def : Pat<(xor (SPhi tglobaltlsaddr:$in1), (SPlo tglobaltlsaddr:$in2)),
1178 (XORri (SETHIi tglobaltlsaddr:$in1), (tglobaltlsaddr:$in2))>;
1181 def : Pat<(SPhi tblockaddress:$in), (SETHIi tblockaddress:$in)>;
1182 def : Pat<(SPlo tblockaddress:$in), (ORri (i32 G0), tblockaddress:$in)>;
1184 // Add reg, lo. This is used when taking the addr of a global/constpool entry.
1185 def : Pat<(add iPTR:$r, (SPlo tglobaladdr:$in)), (ADDri $r, tglobaladdr:$in)>;
1186 def : Pat<(add iPTR:$r, (SPlo tconstpool:$in)), (ADDri $r, tconstpool:$in)>;
1187 def : Pat<(add iPTR:$r, (SPlo tblockaddress:$in)),
1188 (ADDri $r, tblockaddress:$in)>;
1192 def : Pat<(call tglobaladdr:$dst),
1193 (CALL tglobaladdr:$dst)>;
1194 def : Pat<(call texternalsym:$dst),
1195 (CALL texternalsym:$dst)>;
1197 // Map integer extload's to zextloads.
1198 def : Pat<(i32 (extloadi1 ADDRrr:$src)), (LDUBrr ADDRrr:$src)>;
1199 def : Pat<(i32 (extloadi1 ADDRri:$src)), (LDUBri ADDRri:$src)>;
1200 def : Pat<(i32 (extloadi8 ADDRrr:$src)), (LDUBrr ADDRrr:$src)>;
1201 def : Pat<(i32 (extloadi8 ADDRri:$src)), (LDUBri ADDRri:$src)>;
1202 def : Pat<(i32 (extloadi16 ADDRrr:$src)), (LDUHrr ADDRrr:$src)>;
1203 def : Pat<(i32 (extloadi16 ADDRri:$src)), (LDUHri ADDRri:$src)>;
1205 // zextload bool -> zextload byte
1206 def : Pat<(i32 (zextloadi1 ADDRrr:$src)), (LDUBrr ADDRrr:$src)>;
1207 def : Pat<(i32 (zextloadi1 ADDRri:$src)), (LDUBri ADDRri:$src)>;
1209 // store 0, addr -> store %g0, addr
1210 def : Pat<(store (i32 0), ADDRrr:$dst), (STrr ADDRrr:$dst, (i32 G0))>;
1211 def : Pat<(store (i32 0), ADDRri:$dst), (STri ADDRri:$dst, (i32 G0))>;
1213 // store bar for all atomic_fence in V8.
1214 let Predicates = [HasNoV9] in
1215 def : Pat<(atomic_fence imm, imm), (STBAR)>;
1217 // atomic_load_32 addr -> load addr
1218 def : Pat<(i32 (atomic_load ADDRrr:$src)), (LDrr ADDRrr:$src)>;
1219 def : Pat<(i32 (atomic_load ADDRri:$src)), (LDri ADDRri:$src)>;
1221 // atomic_store_32 val, addr -> store val, addr
1222 def : Pat<(atomic_store ADDRrr:$dst, i32:$val), (STrr ADDRrr:$dst, $val)>;
1223 def : Pat<(atomic_store ADDRri:$dst, i32:$val), (STri ADDRri:$dst, $val)>;
1226 include "SparcInstr64Bit.td"
1227 include "SparcInstrVIS.td"
1228 include "SparcInstrAliases.td"