1 //===- SparcInstrInfo.td - Target Description for Sparc Target ------------===//
3 // The LLVM Compiler Infrastructure
5 // This file was developed by the LLVM research group and is distributed under
6 // the University of Illinois Open Source License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the Sparc instructions in TableGen format.
12 //===----------------------------------------------------------------------===//
14 //===----------------------------------------------------------------------===//
15 // Instruction format superclass
16 //===----------------------------------------------------------------------===//
18 include "SparcInstrFormats.td"
20 //===----------------------------------------------------------------------===//
21 // Feature predicates.
22 //===----------------------------------------------------------------------===//
24 // HasV9 - This predicate is true when the target processor supports V9
25 // instructions. Note that the machine may be running in 32-bit mode.
26 def HasV9 : Predicate<"Subtarget.isV9()">;
28 // HasNoV9 - This predicate is true when the target doesn't have V9
29 // instructions. Use of this is just a hack for the isel not having proper
30 // costs for V8 instructions that are more expensive than their V9 ones.
31 def HasNoV9 : Predicate<"!Subtarget.isV9()">;
33 // HasVIS - This is true when the target processor has VIS extensions.
34 def HasVIS : Predicate<"Subtarget.isVIS()">;
36 // UseDeprecatedInsts - This predicate is true when the target processor is a
37 // V8, or when it is V9 but the V8 deprecated instructions are efficient enough
38 // to use when appropriate. In either of these cases, the instruction selector
39 // will pick deprecated instructions.
40 def UseDeprecatedInsts : Predicate<"Subtarget.useDeprecatedV8Instructions()">;
42 //===----------------------------------------------------------------------===//
43 // Instruction Pattern Stuff
44 //===----------------------------------------------------------------------===//
46 def simm11 : PatLeaf<(imm), [{
47 // simm11 predicate - True if the imm fits in a 11-bit sign extended field.
48 return (((int)N->getValue() << (32-11)) >> (32-11)) == (int)N->getValue();
51 def simm13 : PatLeaf<(imm), [{
52 // simm13 predicate - True if the imm fits in a 13-bit sign extended field.
53 return (((int)N->getValue() << (32-13)) >> (32-13)) == (int)N->getValue();
56 def LO10 : SDNodeXForm<imm, [{
57 return CurDAG->getTargetConstant((unsigned)N->getValue() & 1023, MVT::i32);
60 def HI22 : SDNodeXForm<imm, [{
61 // Transformation function: shift the immediate value down into the low bits.
62 return CurDAG->getTargetConstant((unsigned)N->getValue() >> 10, MVT::i32);
65 def SETHIimm : PatLeaf<(imm), [{
66 return (((unsigned)N->getValue() >> 10) << 10) == (unsigned)N->getValue();
70 def ADDRrr : ComplexPattern<i32, 2, "SelectADDRrr", [], []>;
71 def ADDRri : ComplexPattern<i32, 2, "SelectADDRri", [frameindex], []>;
74 def MEMrr : Operand<i32> {
75 let PrintMethod = "printMemOperand";
76 let MIOperandInfo = (ops IntRegs, IntRegs);
78 def MEMri : Operand<i32> {
79 let PrintMethod = "printMemOperand";
80 let MIOperandInfo = (ops IntRegs, i32imm);
83 // Branch targets have OtherVT type.
84 def brtarget : Operand<OtherVT>;
85 def calltarget : Operand<i32>;
87 // Operand for printing out a condition code.
88 let PrintMethod = "printCCOperand" in
89 def CCOp : Operand<i32>;
92 SDTypeProfile<0, 2, [SDTCisFP<0>, SDTCisSameAs<0, 1>]>;
94 SDTypeProfile<0, 2, [SDTCisVT<0, OtherVT>, SDTCisVT<1, i32>]>;
96 SDTypeProfile<1, 3, [SDTCisSameAs<0, 1>, SDTCisSameAs<1, 2>, SDTCisVT<3, i32>]>;
98 SDTypeProfile<1, 1, [SDTCisVT<0, f32>, SDTCisFP<1>]>;
100 SDTypeProfile<1, 1, [SDTCisFP<0>, SDTCisVT<1, f32>]>;
102 def SPcmpicc : SDNode<"SPISD::CMPICC", SDTIntBinOp, [SDNPOutFlag]>;
103 def SPcmpfcc : SDNode<"SPISD::CMPFCC", SDTSPcmpfcc, [SDNPOutFlag]>;
104 def SPbricc : SDNode<"SPISD::BRICC", SDTSPbrcc, [SDNPHasChain, SDNPInFlag]>;
105 def SPbrfcc : SDNode<"SPISD::BRFCC", SDTSPbrcc, [SDNPHasChain, SDNPInFlag]>;
107 def SPhi : SDNode<"SPISD::Hi", SDTIntUnaryOp>;
108 def SPlo : SDNode<"SPISD::Lo", SDTIntUnaryOp>;
110 def SPftoi : SDNode<"SPISD::FTOI", SDTSPFTOI>;
111 def SPitof : SDNode<"SPISD::ITOF", SDTSPITOF>;
113 def SPselecticc : SDNode<"SPISD::SELECT_ICC", SDTSPselectcc, [SDNPInFlag]>;
114 def SPselectfcc : SDNode<"SPISD::SELECT_FCC", SDTSPselectcc, [SDNPInFlag]>;
116 // These are target-independent nodes, but have target-specific formats.
117 def SDT_SPCallSeq : SDTypeProfile<0, 1, [ SDTCisVT<0, i32> ]>;
118 def callseq_start : SDNode<"ISD::CALLSEQ_START", SDT_SPCallSeq,
119 [SDNPHasChain, SDNPOutFlag]>;
120 def callseq_end : SDNode<"ISD::CALLSEQ_END", SDT_SPCallSeq,
121 [SDNPHasChain, SDNPOutFlag]>;
123 def SDT_SPCall : SDTypeProfile<0, 1, [SDTCisVT<0, i32>]>;
124 def call : SDNode<"SPISD::CALL", SDT_SPCall,
125 [SDNPHasChain, SDNPOptInFlag, SDNPOutFlag]>;
127 def SDT_SPRetFlag : SDTypeProfile<0, 0, []>;
128 def retflag : SDNode<"SPISD::RET_FLAG", SDT_SPRetFlag,
129 [SDNPHasChain, SDNPOptInFlag]>;
131 //===----------------------------------------------------------------------===//
132 // SPARC Flag Conditions
133 //===----------------------------------------------------------------------===//
135 // Note that these values must be kept in sync with the CCOp::CondCode enum
137 class ICC_VAL<int N> : PatLeaf<(i32 N)>;
138 def ICC_NE : ICC_VAL< 9>; // Not Equal
139 def ICC_E : ICC_VAL< 1>; // Equal
140 def ICC_G : ICC_VAL<10>; // Greater
141 def ICC_LE : ICC_VAL< 2>; // Less or Equal
142 def ICC_GE : ICC_VAL<11>; // Greater or Equal
143 def ICC_L : ICC_VAL< 3>; // Less
144 def ICC_GU : ICC_VAL<12>; // Greater Unsigned
145 def ICC_LEU : ICC_VAL< 4>; // Less or Equal Unsigned
146 def ICC_CC : ICC_VAL<13>; // Carry Clear/Great or Equal Unsigned
147 def ICC_CS : ICC_VAL< 5>; // Carry Set/Less Unsigned
148 def ICC_POS : ICC_VAL<14>; // Positive
149 def ICC_NEG : ICC_VAL< 6>; // Negative
150 def ICC_VC : ICC_VAL<15>; // Overflow Clear
151 def ICC_VS : ICC_VAL< 7>; // Overflow Set
153 class FCC_VAL<int N> : PatLeaf<(i32 N)>;
154 def FCC_U : FCC_VAL<23>; // Unordered
155 def FCC_G : FCC_VAL<22>; // Greater
156 def FCC_UG : FCC_VAL<21>; // Unordered or Greater
157 def FCC_L : FCC_VAL<20>; // Less
158 def FCC_UL : FCC_VAL<19>; // Unordered or Less
159 def FCC_LG : FCC_VAL<18>; // Less or Greater
160 def FCC_NE : FCC_VAL<17>; // Not Equal
161 def FCC_E : FCC_VAL<25>; // Equal
162 def FCC_UE : FCC_VAL<24>; // Unordered or Equal
163 def FCC_GE : FCC_VAL<25>; // Greater or Equal
164 def FCC_UGE : FCC_VAL<26>; // Unordered or Greater or Equal
165 def FCC_LE : FCC_VAL<27>; // Less or Equal
166 def FCC_ULE : FCC_VAL<28>; // Unordered or Less or Equal
167 def FCC_O : FCC_VAL<29>; // Ordered
169 //===----------------------------------------------------------------------===//
170 // Instruction Class Templates
171 //===----------------------------------------------------------------------===//
173 /// F3_12 multiclass - Define a normal F3_1/F3_2 pattern in one shot.
174 multiclass F3_12<string OpcStr, bits<6> Op3Val, SDNode OpNode> {
175 def rr : F3_1<2, Op3Val,
176 (outs IntRegs:$dst), (ins IntRegs:$b, IntRegs:$c),
177 !strconcat(OpcStr, " $b, $c, $dst"),
178 [(set IntRegs:$dst, (OpNode IntRegs:$b, IntRegs:$c))]>;
179 def ri : F3_2<2, Op3Val,
180 (outs IntRegs:$dst), (ins IntRegs:$b, i32imm:$c),
181 !strconcat(OpcStr, " $b, $c, $dst"),
182 [(set IntRegs:$dst, (OpNode IntRegs:$b, simm13:$c))]>;
185 /// F3_12np multiclass - Define a normal F3_1/F3_2 pattern in one shot, with no
187 multiclass F3_12np<string OpcStr, bits<6> Op3Val> {
188 def rr : F3_1<2, Op3Val,
189 (outs IntRegs:$dst), (ins IntRegs:$b, IntRegs:$c),
190 !strconcat(OpcStr, " $b, $c, $dst"), []>;
191 def ri : F3_2<2, Op3Val,
192 (outs IntRegs:$dst), (ins IntRegs:$b, i32imm:$c),
193 !strconcat(OpcStr, " $b, $c, $dst"), []>;
196 //===----------------------------------------------------------------------===//
198 //===----------------------------------------------------------------------===//
200 // Pseudo instructions.
201 class Pseudo<dag outs, dag ins, string asmstr, list<dag> pattern>
202 : InstSP<outs, ins, asmstr, pattern>;
204 def ADJCALLSTACKDOWN : Pseudo<(outs), (ins i32imm:$amt),
205 "!ADJCALLSTACKDOWN $amt",
206 [(callseq_start imm:$amt)]>, Imp<[O6],[O6]>;
207 def ADJCALLSTACKUP : Pseudo<(outs), (ins i32imm:$amt),
208 "!ADJCALLSTACKUP $amt",
209 [(callseq_end imm:$amt)]>, Imp<[O6],[O6]>;
210 def IMPLICIT_DEF_Int : Pseudo<(outs IntRegs:$dst), (ins),
211 "!IMPLICIT_DEF $dst",
212 [(set IntRegs:$dst, (undef))]>;
213 def IMPLICIT_DEF_FP : Pseudo<(outs FPRegs:$dst), (ins), "!IMPLICIT_DEF $dst",
214 [(set FPRegs:$dst, (undef))]>;
215 def IMPLICIT_DEF_DFP : Pseudo<(outs DFPRegs:$dst), (ins), "!IMPLICIT_DEF $dst",
216 [(set DFPRegs:$dst, (undef))]>;
218 // FpMOVD/FpNEGD/FpABSD - These are lowered to single-precision ops by the
220 let Predicates = [HasNoV9] in { // Only emit these in V8 mode.
221 def FpMOVD : Pseudo<(outs DFPRegs:$dst), (ins DFPRegs:$src),
222 "!FpMOVD $src, $dst", []>;
223 def FpNEGD : Pseudo<(outs DFPRegs:$dst), (ins DFPRegs:$src),
224 "!FpNEGD $src, $dst",
225 [(set DFPRegs:$dst, (fneg DFPRegs:$src))]>;
226 def FpABSD : Pseudo<(outs DFPRegs:$dst), (ins DFPRegs:$src),
227 "!FpABSD $src, $dst",
228 [(set DFPRegs:$dst, (fabs DFPRegs:$src))]>;
231 // SELECT_CC_* - Used to implement the SELECT_CC DAG operation. Expanded by the
232 // scheduler into a branch sequence. This has to handle all permutations of
233 // selection between i32/f32/f64 on ICC and FCC.
234 let usesCustomDAGSchedInserter = 1 in { // Expanded by the scheduler.
235 def SELECT_CC_Int_ICC
236 : Pseudo<(outs IntRegs:$dst), (ins IntRegs:$T, IntRegs:$F, i32imm:$Cond),
237 "; SELECT_CC_Int_ICC PSEUDO!",
238 [(set IntRegs:$dst, (SPselecticc IntRegs:$T, IntRegs:$F,
240 def SELECT_CC_Int_FCC
241 : Pseudo<(outs IntRegs:$dst), (ins IntRegs:$T, IntRegs:$F, i32imm:$Cond),
242 "; SELECT_CC_Int_FCC PSEUDO!",
243 [(set IntRegs:$dst, (SPselectfcc IntRegs:$T, IntRegs:$F,
246 : Pseudo<(outs FPRegs:$dst), (ins FPRegs:$T, FPRegs:$F, i32imm:$Cond),
247 "; SELECT_CC_FP_ICC PSEUDO!",
248 [(set FPRegs:$dst, (SPselecticc FPRegs:$T, FPRegs:$F,
251 : Pseudo<(outs FPRegs:$dst), (ins FPRegs:$T, FPRegs:$F, i32imm:$Cond),
252 "; SELECT_CC_FP_FCC PSEUDO!",
253 [(set FPRegs:$dst, (SPselectfcc FPRegs:$T, FPRegs:$F,
255 def SELECT_CC_DFP_ICC
256 : Pseudo<(outs DFPRegs:$dst), (ins DFPRegs:$T, DFPRegs:$F, i32imm:$Cond),
257 "; SELECT_CC_DFP_ICC PSEUDO!",
258 [(set DFPRegs:$dst, (SPselecticc DFPRegs:$T, DFPRegs:$F,
260 def SELECT_CC_DFP_FCC
261 : Pseudo<(outs DFPRegs:$dst), (ins DFPRegs:$T, DFPRegs:$F, i32imm:$Cond),
262 "; SELECT_CC_DFP_FCC PSEUDO!",
263 [(set DFPRegs:$dst, (SPselectfcc DFPRegs:$T, DFPRegs:$F,
268 // Section A.3 - Synthetic Instructions, p. 85
269 // special cases of JMPL:
270 let isReturn = 1, isTerminator = 1, hasDelaySlot = 1 in {
271 let rd = O7.Num, rs1 = G0.Num, simm13 = 8 in
272 def RETL: F3_2<2, 0b111000, (outs), (ins), "retl", [(retflag)]>;
275 // Section B.1 - Load Integer Instructions, p. 90
276 def LDSBrr : F3_1<3, 0b001001,
277 (outs IntRegs:$dst), (ins MEMrr:$addr),
278 "ldsb [$addr], $dst",
279 [(set IntRegs:$dst, (sextloadi8 ADDRrr:$addr))]>;
280 def LDSBri : F3_2<3, 0b001001,
281 (outs IntRegs:$dst), (ins MEMri:$addr),
282 "ldsb [$addr], $dst",
283 [(set IntRegs:$dst, (sextloadi8 ADDRri:$addr))]>;
284 def LDSHrr : F3_1<3, 0b001010,
285 (outs IntRegs:$dst), (ins MEMrr:$addr),
286 "ldsh [$addr], $dst",
287 [(set IntRegs:$dst, (sextloadi16 ADDRrr:$addr))]>;
288 def LDSHri : F3_2<3, 0b001010,
289 (outs IntRegs:$dst), (ins MEMri:$addr),
290 "ldsh [$addr], $dst",
291 [(set IntRegs:$dst, (sextloadi16 ADDRri:$addr))]>;
292 def LDUBrr : F3_1<3, 0b000001,
293 (outs IntRegs:$dst), (ins MEMrr:$addr),
294 "ldub [$addr], $dst",
295 [(set IntRegs:$dst, (zextloadi8 ADDRrr:$addr))]>;
296 def LDUBri : F3_2<3, 0b000001,
297 (outs IntRegs:$dst), (ins MEMri:$addr),
298 "ldub [$addr], $dst",
299 [(set IntRegs:$dst, (zextloadi8 ADDRri:$addr))]>;
300 def LDUHrr : F3_1<3, 0b000010,
301 (outs IntRegs:$dst), (ins MEMrr:$addr),
302 "lduh [$addr], $dst",
303 [(set IntRegs:$dst, (zextloadi16 ADDRrr:$addr))]>;
304 def LDUHri : F3_2<3, 0b000010,
305 (outs IntRegs:$dst), (ins MEMri:$addr),
306 "lduh [$addr], $dst",
307 [(set IntRegs:$dst, (zextloadi16 ADDRri:$addr))]>;
308 def LDrr : F3_1<3, 0b000000,
309 (outs IntRegs:$dst), (ins MEMrr:$addr),
311 [(set IntRegs:$dst, (load ADDRrr:$addr))]>;
312 def LDri : F3_2<3, 0b000000,
313 (outs IntRegs:$dst), (ins MEMri:$addr),
315 [(set IntRegs:$dst, (load ADDRri:$addr))]>;
317 // Section B.2 - Load Floating-point Instructions, p. 92
318 def LDFrr : F3_1<3, 0b100000,
319 (outs FPRegs:$dst), (ins MEMrr:$addr),
321 [(set FPRegs:$dst, (load ADDRrr:$addr))]>;
322 def LDFri : F3_2<3, 0b100000,
323 (outs FPRegs:$dst), (ins MEMri:$addr),
325 [(set FPRegs:$dst, (load ADDRri:$addr))]>;
326 def LDDFrr : F3_1<3, 0b100011,
327 (outs DFPRegs:$dst), (ins MEMrr:$addr),
329 [(set DFPRegs:$dst, (load ADDRrr:$addr))]>;
330 def LDDFri : F3_2<3, 0b100011,
331 (outs DFPRegs:$dst), (ins MEMri:$addr),
333 [(set DFPRegs:$dst, (load ADDRri:$addr))]>;
335 // Section B.4 - Store Integer Instructions, p. 95
336 def STBrr : F3_1<3, 0b000101,
337 (outs), (ins MEMrr:$addr, IntRegs:$src),
339 [(truncstorei8 IntRegs:$src, ADDRrr:$addr)]>;
340 def STBri : F3_2<3, 0b000101,
341 (outs), (ins MEMri:$addr, IntRegs:$src),
343 [(truncstorei8 IntRegs:$src, ADDRri:$addr)]>;
344 def STHrr : F3_1<3, 0b000110,
345 (outs), (ins MEMrr:$addr, IntRegs:$src),
347 [(truncstorei16 IntRegs:$src, ADDRrr:$addr)]>;
348 def STHri : F3_2<3, 0b000110,
349 (outs), (ins MEMri:$addr, IntRegs:$src),
351 [(truncstorei16 IntRegs:$src, ADDRri:$addr)]>;
352 def STrr : F3_1<3, 0b000100,
353 (outs), (ins MEMrr:$addr, IntRegs:$src),
355 [(store IntRegs:$src, ADDRrr:$addr)]>;
356 def STri : F3_2<3, 0b000100,
357 (outs), (ins MEMri:$addr, IntRegs:$src),
359 [(store IntRegs:$src, ADDRri:$addr)]>;
361 // Section B.5 - Store Floating-point Instructions, p. 97
362 def STFrr : F3_1<3, 0b100100,
363 (outs), (ins MEMrr:$addr, FPRegs:$src),
365 [(store FPRegs:$src, ADDRrr:$addr)]>;
366 def STFri : F3_2<3, 0b100100,
367 (outs), (ins MEMri:$addr, FPRegs:$src),
369 [(store FPRegs:$src, ADDRri:$addr)]>;
370 def STDFrr : F3_1<3, 0b100111,
371 (outs), (ins MEMrr:$addr, DFPRegs:$src),
373 [(store DFPRegs:$src, ADDRrr:$addr)]>;
374 def STDFri : F3_2<3, 0b100111,
375 (outs), (ins MEMri:$addr, DFPRegs:$src),
377 [(store DFPRegs:$src, ADDRri:$addr)]>;
379 // Section B.9 - SETHI Instruction, p. 104
380 def SETHIi: F2_1<0b100,
381 (outs IntRegs:$dst), (ins i32imm:$src),
383 [(set IntRegs:$dst, SETHIimm:$src)]>;
385 // Section B.10 - NOP Instruction, p. 105
386 // (It's a special case of SETHI)
387 let rd = 0, imm22 = 0 in
388 def NOP : F2_1<0b100, (outs), (ins), "nop", []>;
390 // Section B.11 - Logical Instructions, p. 106
391 defm AND : F3_12<"and", 0b000001, and>;
393 def ANDNrr : F3_1<2, 0b000101,
394 (outs IntRegs:$dst), (ins IntRegs:$b, IntRegs:$c),
396 [(set IntRegs:$dst, (and IntRegs:$b, (not IntRegs:$c)))]>;
397 def ANDNri : F3_2<2, 0b000101,
398 (outs IntRegs:$dst), (ins IntRegs:$b, i32imm:$c),
399 "andn $b, $c, $dst", []>;
401 defm OR : F3_12<"or", 0b000010, or>;
403 def ORNrr : F3_1<2, 0b000110,
404 (outs IntRegs:$dst), (ins IntRegs:$b, IntRegs:$c),
406 [(set IntRegs:$dst, (or IntRegs:$b, (not IntRegs:$c)))]>;
407 def ORNri : F3_2<2, 0b000110,
408 (outs IntRegs:$dst), (ins IntRegs:$b, i32imm:$c),
409 "orn $b, $c, $dst", []>;
410 defm XOR : F3_12<"xor", 0b000011, xor>;
412 def XNORrr : F3_1<2, 0b000111,
413 (outs IntRegs:$dst), (ins IntRegs:$b, IntRegs:$c),
415 [(set IntRegs:$dst, (not (xor IntRegs:$b, IntRegs:$c)))]>;
416 def XNORri : F3_2<2, 0b000111,
417 (outs IntRegs:$dst), (ins IntRegs:$b, i32imm:$c),
418 "xnor $b, $c, $dst", []>;
420 // Section B.12 - Shift Instructions, p. 107
421 defm SLL : F3_12<"sll", 0b100101, shl>;
422 defm SRL : F3_12<"srl", 0b100110, srl>;
423 defm SRA : F3_12<"sra", 0b100111, sra>;
425 // Section B.13 - Add Instructions, p. 108
426 defm ADD : F3_12<"add", 0b000000, add>;
428 // "LEA" forms of add (patterns to make tblgen happy)
429 def LEA_ADDri : F3_2<2, 0b000000,
430 (outs IntRegs:$dst), (ins MEMri:$addr),
431 "add ${addr:arith}, $dst",
432 [(set IntRegs:$dst, ADDRri:$addr)]>;
434 defm ADDCC : F3_12<"addcc", 0b010000, addc>;
435 defm ADDX : F3_12<"addx", 0b001000, adde>;
437 // Section B.15 - Subtract Instructions, p. 110
438 defm SUB : F3_12 <"sub" , 0b000100, sub>;
439 defm SUBX : F3_12 <"subx" , 0b001100, sube>;
440 defm SUBCC : F3_12 <"subcc", 0b010100, SPcmpicc>;
442 def SUBXCCrr: F3_1<2, 0b011100,
443 (outs IntRegs:$dst), (ins IntRegs:$b, IntRegs:$c),
444 "subxcc $b, $c, $dst", []>;
446 // Section B.18 - Multiply Instructions, p. 113
447 defm UMUL : F3_12np<"umul", 0b001010>;
448 defm SMUL : F3_12 <"smul", 0b001011, mul>;
451 // Section B.19 - Divide Instructions, p. 115
452 defm UDIV : F3_12np<"udiv", 0b001110>;
453 defm SDIV : F3_12np<"sdiv", 0b001111>;
455 // Section B.20 - SAVE and RESTORE, p. 117
456 defm SAVE : F3_12np<"save" , 0b111100>;
457 defm RESTORE : F3_12np<"restore", 0b111101>;
459 // Section B.21 - Branch on Integer Condition Codes Instructions, p. 119
461 // conditional branch class:
462 class BranchSP<bits<4> cc, dag ins, string asmstr, list<dag> pattern>
463 : F2_2<cc, 0b010, (outs), ins, asmstr, pattern> {
465 let isTerminator = 1;
466 let hasDelaySlot = 1;
470 def BA : BranchSP<0b1000, (ins brtarget:$dst),
474 // FIXME: the encoding for the JIT should look at the condition field.
475 def BCOND : BranchSP<0, (ins brtarget:$dst, CCOp:$cc),
477 [(SPbricc bb:$dst, imm:$cc)]>;
480 // Section B.22 - Branch on Floating-point Condition Codes Instructions, p. 121
482 // floating-point conditional branch class:
483 class FPBranchSP<bits<4> cc, dag ins, string asmstr, list<dag> pattern>
484 : F2_2<cc, 0b110, (outs), ins, asmstr, pattern> {
486 let isTerminator = 1;
487 let hasDelaySlot = 1;
490 // FIXME: the encoding for the JIT should look at the condition field.
491 def FBCOND : FPBranchSP<0, (ins brtarget:$dst, CCOp:$cc),
493 [(SPbrfcc bb:$dst, imm:$cc)]>;
496 // Section B.24 - Call and Link Instruction, p. 125
497 // This is the only Format 1 instruction
498 let Uses = [O0, O1, O2, O3, O4, O5],
499 hasDelaySlot = 1, isCall = 1,
500 Defs = [O0, O1, O2, O3, O4, O5, O7, G1, G2, G3, G4, G5, G6, G7,
501 D0, D1, D2, D3, D4, D5, D6, D7, D8, D9, D10, D11, D12, D13, D14, D15] in {
502 def CALL : InstSP<(outs), (ins calltarget:$dst),
506 let Inst{29-0} = disp;
510 def JMPLrr : F3_1<2, 0b111000,
511 (outs), (ins MEMrr:$ptr),
513 [(call ADDRrr:$ptr)]>;
514 def JMPLri : F3_2<2, 0b111000,
515 (outs), (ins MEMri:$ptr),
517 [(call ADDRri:$ptr)]>;
520 // Section B.28 - Read State Register Instructions
521 def RDY : F3_1<2, 0b101000,
522 (outs IntRegs:$dst), (ins),
525 // Section B.29 - Write State Register Instructions
526 def WRYrr : F3_1<2, 0b110000,
527 (outs), (ins IntRegs:$b, IntRegs:$c),
528 "wr $b, $c, %y", []>;
529 def WRYri : F3_2<2, 0b110000,
530 (outs), (ins IntRegs:$b, i32imm:$c),
531 "wr $b, $c, %y", []>;
533 // Convert Integer to Floating-point Instructions, p. 141
534 def FITOS : F3_3<2, 0b110100, 0b011000100,
535 (outs FPRegs:$dst), (ins FPRegs:$src),
537 [(set FPRegs:$dst, (SPitof FPRegs:$src))]>;
538 def FITOD : F3_3<2, 0b110100, 0b011001000,
539 (outs DFPRegs:$dst), (ins FPRegs:$src),
541 [(set DFPRegs:$dst, (SPitof FPRegs:$src))]>;
543 // Convert Floating-point to Integer Instructions, p. 142
544 def FSTOI : F3_3<2, 0b110100, 0b011010001,
545 (outs FPRegs:$dst), (ins FPRegs:$src),
547 [(set FPRegs:$dst, (SPftoi FPRegs:$src))]>;
548 def FDTOI : F3_3<2, 0b110100, 0b011010010,
549 (outs FPRegs:$dst), (ins DFPRegs:$src),
551 [(set FPRegs:$dst, (SPftoi DFPRegs:$src))]>;
553 // Convert between Floating-point Formats Instructions, p. 143
554 def FSTOD : F3_3<2, 0b110100, 0b011001001,
555 (outs DFPRegs:$dst), (ins FPRegs:$src),
557 [(set DFPRegs:$dst, (fextend FPRegs:$src))]>;
558 def FDTOS : F3_3<2, 0b110100, 0b011000110,
559 (outs FPRegs:$dst), (ins DFPRegs:$src),
561 [(set FPRegs:$dst, (fround DFPRegs:$src))]>;
563 // Floating-point Move Instructions, p. 144
564 def FMOVS : F3_3<2, 0b110100, 0b000000001,
565 (outs FPRegs:$dst), (ins FPRegs:$src),
566 "fmovs $src, $dst", []>;
567 def FNEGS : F3_3<2, 0b110100, 0b000000101,
568 (outs FPRegs:$dst), (ins FPRegs:$src),
570 [(set FPRegs:$dst, (fneg FPRegs:$src))]>;
571 def FABSS : F3_3<2, 0b110100, 0b000001001,
572 (outs FPRegs:$dst), (ins FPRegs:$src),
574 [(set FPRegs:$dst, (fabs FPRegs:$src))]>;
577 // Floating-point Square Root Instructions, p.145
578 def FSQRTS : F3_3<2, 0b110100, 0b000101001,
579 (outs FPRegs:$dst), (ins FPRegs:$src),
581 [(set FPRegs:$dst, (fsqrt FPRegs:$src))]>;
582 def FSQRTD : F3_3<2, 0b110100, 0b000101010,
583 (outs DFPRegs:$dst), (ins DFPRegs:$src),
585 [(set DFPRegs:$dst, (fsqrt DFPRegs:$src))]>;
589 // Floating-point Add and Subtract Instructions, p. 146
590 def FADDS : F3_3<2, 0b110100, 0b001000001,
591 (outs FPRegs:$dst), (ins FPRegs:$src1, FPRegs:$src2),
592 "fadds $src1, $src2, $dst",
593 [(set FPRegs:$dst, (fadd FPRegs:$src1, FPRegs:$src2))]>;
594 def FADDD : F3_3<2, 0b110100, 0b001000010,
595 (outs DFPRegs:$dst), (ins DFPRegs:$src1, DFPRegs:$src2),
596 "faddd $src1, $src2, $dst",
597 [(set DFPRegs:$dst, (fadd DFPRegs:$src1, DFPRegs:$src2))]>;
598 def FSUBS : F3_3<2, 0b110100, 0b001000101,
599 (outs FPRegs:$dst), (ins FPRegs:$src1, FPRegs:$src2),
600 "fsubs $src1, $src2, $dst",
601 [(set FPRegs:$dst, (fsub FPRegs:$src1, FPRegs:$src2))]>;
602 def FSUBD : F3_3<2, 0b110100, 0b001000110,
603 (outs DFPRegs:$dst), (ins DFPRegs:$src1, DFPRegs:$src2),
604 "fsubd $src1, $src2, $dst",
605 [(set DFPRegs:$dst, (fsub DFPRegs:$src1, DFPRegs:$src2))]>;
607 // Floating-point Multiply and Divide Instructions, p. 147
608 def FMULS : F3_3<2, 0b110100, 0b001001001,
609 (outs FPRegs:$dst), (ins FPRegs:$src1, FPRegs:$src2),
610 "fmuls $src1, $src2, $dst",
611 [(set FPRegs:$dst, (fmul FPRegs:$src1, FPRegs:$src2))]>;
612 def FMULD : F3_3<2, 0b110100, 0b001001010,
613 (outs DFPRegs:$dst), (ins DFPRegs:$src1, DFPRegs:$src2),
614 "fmuld $src1, $src2, $dst",
615 [(set DFPRegs:$dst, (fmul DFPRegs:$src1, DFPRegs:$src2))]>;
616 def FSMULD : F3_3<2, 0b110100, 0b001101001,
617 (outs DFPRegs:$dst), (ins FPRegs:$src1, FPRegs:$src2),
618 "fsmuld $src1, $src2, $dst",
619 [(set DFPRegs:$dst, (fmul (fextend FPRegs:$src1),
620 (fextend FPRegs:$src2)))]>;
621 def FDIVS : F3_3<2, 0b110100, 0b001001101,
622 (outs FPRegs:$dst), (ins FPRegs:$src1, FPRegs:$src2),
623 "fdivs $src1, $src2, $dst",
624 [(set FPRegs:$dst, (fdiv FPRegs:$src1, FPRegs:$src2))]>;
625 def FDIVD : F3_3<2, 0b110100, 0b001001110,
626 (outs DFPRegs:$dst), (ins DFPRegs:$src1, DFPRegs:$src2),
627 "fdivd $src1, $src2, $dst",
628 [(set DFPRegs:$dst, (fdiv DFPRegs:$src1, DFPRegs:$src2))]>;
630 // Floating-point Compare Instructions, p. 148
631 // Note: the 2nd template arg is different for these guys.
632 // Note 2: the result of a FCMP is not available until the 2nd cycle
633 // after the instr is retired, but there is no interlock. This behavior
634 // is modelled with a forced noop after the instruction.
635 def FCMPS : F3_3<2, 0b110101, 0b001010001,
636 (outs), (ins FPRegs:$src1, FPRegs:$src2),
637 "fcmps $src1, $src2\n\tnop",
638 [(SPcmpfcc FPRegs:$src1, FPRegs:$src2)]>;
639 def FCMPD : F3_3<2, 0b110101, 0b001010010,
640 (outs), (ins DFPRegs:$src1, DFPRegs:$src2),
641 "fcmpd $src1, $src2\n\tnop",
642 [(SPcmpfcc DFPRegs:$src1, DFPRegs:$src2)]>;
645 //===----------------------------------------------------------------------===//
647 //===----------------------------------------------------------------------===//
649 // V9 Conditional Moves.
650 let Predicates = [HasV9], isTwoAddress = 1 in {
651 // Move Integer Register on Condition (MOVcc) p. 194 of the V9 manual.
652 // FIXME: Add instruction encodings for the JIT some day.
654 : Pseudo<(outs IntRegs:$dst), (ins IntRegs:$T, IntRegs:$F, CCOp:$cc),
655 "mov$cc %icc, $F, $dst",
657 (SPselecticc IntRegs:$F, IntRegs:$T, imm:$cc))]>;
659 : Pseudo<(outs IntRegs:$dst), (ins IntRegs:$T, i32imm:$F, CCOp:$cc),
660 "mov$cc %icc, $F, $dst",
662 (SPselecticc simm11:$F, IntRegs:$T, imm:$cc))]>;
665 : Pseudo<(outs IntRegs:$dst), (ins IntRegs:$T, IntRegs:$F, CCOp:$cc),
666 "mov$cc %fcc0, $F, $dst",
668 (SPselectfcc IntRegs:$F, IntRegs:$T, imm:$cc))]>;
670 : Pseudo<(outs IntRegs:$dst), (ins IntRegs:$T, i32imm:$F, CCOp:$cc),
671 "mov$cc %fcc0, $F, $dst",
673 (SPselectfcc simm11:$F, IntRegs:$T, imm:$cc))]>;
676 : Pseudo<(outs FPRegs:$dst), (ins FPRegs:$T, FPRegs:$F, CCOp:$cc),
677 "fmovs$cc %icc, $F, $dst",
679 (SPselecticc FPRegs:$F, FPRegs:$T, imm:$cc))]>;
681 : Pseudo<(outs DFPRegs:$dst), (ins DFPRegs:$T, DFPRegs:$F, CCOp:$cc),
682 "fmovd$cc %icc, $F, $dst",
684 (SPselecticc DFPRegs:$F, DFPRegs:$T, imm:$cc))]>;
686 : Pseudo<(outs FPRegs:$dst), (ins FPRegs:$T, FPRegs:$F, CCOp:$cc),
687 "fmovs$cc %fcc0, $F, $dst",
689 (SPselectfcc FPRegs:$F, FPRegs:$T, imm:$cc))]>;
691 : Pseudo<(outs DFPRegs:$dst), (ins DFPRegs:$T, DFPRegs:$F, CCOp:$cc),
692 "fmovd$cc %fcc0, $F, $dst",
694 (SPselectfcc DFPRegs:$F, DFPRegs:$T, imm:$cc))]>;
698 // Floating-Point Move Instructions, p. 164 of the V9 manual.
699 let Predicates = [HasV9] in {
700 def FMOVD : F3_3<2, 0b110100, 0b000000010,
701 (outs DFPRegs:$dst), (ins DFPRegs:$src),
702 "fmovd $src, $dst", []>;
703 def FNEGD : F3_3<2, 0b110100, 0b000000110,
704 (outs DFPRegs:$dst), (ins DFPRegs:$src),
706 [(set DFPRegs:$dst, (fneg DFPRegs:$src))]>;
707 def FABSD : F3_3<2, 0b110100, 0b000001010,
708 (outs DFPRegs:$dst), (ins DFPRegs:$src),
710 [(set DFPRegs:$dst, (fabs DFPRegs:$src))]>;
713 // POPCrr - This does a ctpop of a 64-bit register. As such, we have to clear
714 // the top 32-bits before using it. To do this clearing, we use a SLLri X,0.
715 def POPCrr : F3_1<2, 0b101110,
716 (outs IntRegs:$dst), (ins IntRegs:$src),
717 "popc $src, $dst", []>, Requires<[HasV9]>;
718 def : Pat<(ctpop IntRegs:$src),
719 (POPCrr (SLLri IntRegs:$src, 0))>;
721 //===----------------------------------------------------------------------===//
722 // Non-Instruction Patterns
723 //===----------------------------------------------------------------------===//
726 def : Pat<(i32 simm13:$val),
727 (ORri G0, imm:$val)>;
728 // Arbitrary immediates.
729 def : Pat<(i32 imm:$val),
730 (ORri (SETHIi (HI22 imm:$val)), (LO10 imm:$val))>;
733 def : Pat<(subc IntRegs:$b, IntRegs:$c),
734 (SUBCCrr IntRegs:$b, IntRegs:$c)>;
735 def : Pat<(subc IntRegs:$b, simm13:$val),
736 (SUBCCri IntRegs:$b, imm:$val)>;
738 // Global addresses, constant pool entries
739 def : Pat<(SPhi tglobaladdr:$in), (SETHIi tglobaladdr:$in)>;
740 def : Pat<(SPlo tglobaladdr:$in), (ORri G0, tglobaladdr:$in)>;
741 def : Pat<(SPhi tconstpool:$in), (SETHIi tconstpool:$in)>;
742 def : Pat<(SPlo tconstpool:$in), (ORri G0, tconstpool:$in)>;
744 // Add reg, lo. This is used when taking the addr of a global/constpool entry.
745 def : Pat<(add IntRegs:$r, (SPlo tglobaladdr:$in)),
746 (ADDri IntRegs:$r, tglobaladdr:$in)>;
747 def : Pat<(add IntRegs:$r, (SPlo tconstpool:$in)),
748 (ADDri IntRegs:$r, tconstpool:$in)>;
751 def : Pat<(call tglobaladdr:$dst),
752 (CALL tglobaladdr:$dst)>;
753 def : Pat<(call texternalsym:$dst),
754 (CALL texternalsym:$dst)>;
756 def : Pat<(ret), (RETL)>;
758 // Map integer extload's to zextloads.
759 def : Pat<(i32 (extloadi1 ADDRrr:$src)), (LDUBrr ADDRrr:$src)>;
760 def : Pat<(i32 (extloadi1 ADDRri:$src)), (LDUBri ADDRri:$src)>;
761 def : Pat<(i32 (extloadi8 ADDRrr:$src)), (LDUBrr ADDRrr:$src)>;
762 def : Pat<(i32 (extloadi8 ADDRri:$src)), (LDUBri ADDRri:$src)>;
763 def : Pat<(i32 (extloadi16 ADDRrr:$src)), (LDUHrr ADDRrr:$src)>;
764 def : Pat<(i32 (extloadi16 ADDRri:$src)), (LDUHri ADDRri:$src)>;
766 // zextload bool -> zextload byte
767 def : Pat<(i32 (zextloadi1 ADDRrr:$src)), (LDUBrr ADDRrr:$src)>;
768 def : Pat<(i32 (zextloadi1 ADDRri:$src)), (LDUBri ADDRri:$src)>;
770 // truncstore bool -> truncstore byte.
771 def : Pat<(truncstorei1 IntRegs:$src, ADDRrr:$addr),
772 (STBrr ADDRrr:$addr, IntRegs:$src)>;
773 def : Pat<(truncstorei1 IntRegs:$src, ADDRri:$addr),
774 (STBri ADDRri:$addr, IntRegs:$src)>;