1 //===-- SparcInstrInfo.td - Target Description for Sparc Target -----------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the Sparc instructions in TableGen format.
12 //===----------------------------------------------------------------------===//
14 //===----------------------------------------------------------------------===//
15 // Instruction format superclass
16 //===----------------------------------------------------------------------===//
18 include "SparcInstrFormats.td"
20 //===----------------------------------------------------------------------===//
21 // Feature predicates.
22 //===----------------------------------------------------------------------===//
24 // True when generating 32-bit code.
25 def Is32Bit : Predicate<"!Subtarget.is64Bit()">;
27 // True when generating 64-bit code. This also implies HasV9.
28 def Is64Bit : Predicate<"Subtarget.is64Bit()">;
30 // HasV9 - This predicate is true when the target processor supports V9
31 // instructions. Note that the machine may be running in 32-bit mode.
32 def HasV9 : Predicate<"Subtarget.isV9()">;
34 // HasNoV9 - This predicate is true when the target doesn't have V9
35 // instructions. Use of this is just a hack for the isel not having proper
36 // costs for V8 instructions that are more expensive than their V9 ones.
37 def HasNoV9 : Predicate<"!Subtarget.isV9()">;
39 // HasVIS - This is true when the target processor has VIS extensions.
40 def HasVIS : Predicate<"Subtarget.isVIS()">;
42 // HasHardQuad - This is true when the target processor supports quad floating
43 // point instructions.
44 def HasHardQuad : Predicate<"Subtarget.hasHardQuad()">;
46 // UseDeprecatedInsts - This predicate is true when the target processor is a
47 // V8, or when it is V9 but the V8 deprecated instructions are efficient enough
48 // to use when appropriate. In either of these cases, the instruction selector
49 // will pick deprecated instructions.
50 def UseDeprecatedInsts : Predicate<"Subtarget.useDeprecatedV8Instructions()">;
52 //===----------------------------------------------------------------------===//
53 // Instruction Pattern Stuff
54 //===----------------------------------------------------------------------===//
56 def simm11 : PatLeaf<(imm), [{ return isInt<11>(N->getSExtValue()); }]>;
58 def simm13 : PatLeaf<(imm), [{ return isInt<13>(N->getSExtValue()); }]>;
60 def LO10 : SDNodeXForm<imm, [{
61 return CurDAG->getTargetConstant((unsigned)N->getZExtValue() & 1023,
65 def HI22 : SDNodeXForm<imm, [{
66 // Transformation function: shift the immediate value down into the low bits.
67 return CurDAG->getTargetConstant((unsigned)N->getZExtValue() >> 10, MVT::i32);
70 def SETHIimm : PatLeaf<(imm), [{
71 return isShiftedUInt<22, 10>(N->getZExtValue());
75 def ADDRrr : ComplexPattern<iPTR, 2, "SelectADDRrr", [], []>;
76 def ADDRri : ComplexPattern<iPTR, 2, "SelectADDRri", [frameindex], []>;
79 def MEMrr : Operand<iPTR> {
80 let PrintMethod = "printMemOperand";
81 let MIOperandInfo = (ops ptr_rc, ptr_rc);
83 def MEMri : Operand<iPTR> {
84 let PrintMethod = "printMemOperand";
85 let MIOperandInfo = (ops ptr_rc, i32imm);
88 def TLSSym : Operand<iPTR>;
90 // Branch targets have OtherVT type.
91 def brtarget : Operand<OtherVT>;
92 def calltarget : Operand<i32>;
94 // Operand for printing out a condition code.
95 let PrintMethod = "printCCOperand" in
96 def CCOp : Operand<i32>;
99 SDTypeProfile<0, 2, [SDTCisInt<0>, SDTCisSameAs<0, 1>]>;
101 SDTypeProfile<0, 2, [SDTCisFP<0>, SDTCisSameAs<0, 1>]>;
103 SDTypeProfile<0, 2, [SDTCisVT<0, OtherVT>, SDTCisVT<1, i32>]>;
105 SDTypeProfile<1, 3, [SDTCisSameAs<0, 1>, SDTCisSameAs<1, 2>, SDTCisVT<3, i32>]>;
107 SDTypeProfile<1, 1, [SDTCisVT<0, f32>, SDTCisFP<1>]>;
109 SDTypeProfile<1, 1, [SDTCisFP<0>, SDTCisVT<1, f32>]>;
111 SDTypeProfile<1, 1, [SDTCisVT<0, f64>, SDTCisFP<1>]>;
113 SDTypeProfile<1, 1, [SDTCisFP<0>, SDTCisVT<1, f64>]>;
116 SDTypeProfile<1, 3, [SDTCisInt<0>, SDTCisSameAs<0, 1>, SDTCisPtrTy<2>]>;
118 SDTypeProfile<1, 2, [SDTCisPtrTy<0>, SDTCisPtrTy<1>]>;
120 def SPcmpicc : SDNode<"SPISD::CMPICC", SDTSPcmpicc, [SDNPOutGlue]>;
121 def SPcmpfcc : SDNode<"SPISD::CMPFCC", SDTSPcmpfcc, [SDNPOutGlue]>;
122 def SPbricc : SDNode<"SPISD::BRICC", SDTSPbrcc, [SDNPHasChain, SDNPInGlue]>;
123 def SPbrxcc : SDNode<"SPISD::BRXCC", SDTSPbrcc, [SDNPHasChain, SDNPInGlue]>;
124 def SPbrfcc : SDNode<"SPISD::BRFCC", SDTSPbrcc, [SDNPHasChain, SDNPInGlue]>;
126 def SPhi : SDNode<"SPISD::Hi", SDTIntUnaryOp>;
127 def SPlo : SDNode<"SPISD::Lo", SDTIntUnaryOp>;
129 def SPftoi : SDNode<"SPISD::FTOI", SDTSPFTOI>;
130 def SPitof : SDNode<"SPISD::ITOF", SDTSPITOF>;
131 def SPftox : SDNode<"SPISD::FTOX", SDTSPFTOX>;
132 def SPxtof : SDNode<"SPISD::XTOF", SDTSPXTOF>;
134 def SPselecticc : SDNode<"SPISD::SELECT_ICC", SDTSPselectcc, [SDNPInGlue]>;
135 def SPselectxcc : SDNode<"SPISD::SELECT_XCC", SDTSPselectcc, [SDNPInGlue]>;
136 def SPselectfcc : SDNode<"SPISD::SELECT_FCC", SDTSPselectcc, [SDNPInGlue]>;
138 // These are target-independent nodes, but have target-specific formats.
139 def SDT_SPCallSeqStart : SDCallSeqStart<[ SDTCisVT<0, i32> ]>;
140 def SDT_SPCallSeqEnd : SDCallSeqEnd<[ SDTCisVT<0, i32>,
143 def callseq_start : SDNode<"ISD::CALLSEQ_START", SDT_SPCallSeqStart,
144 [SDNPHasChain, SDNPOutGlue]>;
145 def callseq_end : SDNode<"ISD::CALLSEQ_END", SDT_SPCallSeqEnd,
146 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]>;
148 def SDT_SPCall : SDTypeProfile<0, -1, [SDTCisVT<0, i32>]>;
149 def call : SDNode<"SPISD::CALL", SDT_SPCall,
150 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue,
153 def SDT_SPRet : SDTypeProfile<0, 1, [SDTCisVT<0, i32>]>;
154 def retflag : SDNode<"SPISD::RET_FLAG", SDT_SPRet,
155 [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>;
157 def flushw : SDNode<"SPISD::FLUSHW", SDTNone,
158 [SDNPHasChain, SDNPSideEffect, SDNPMayStore]>;
160 def tlsadd : SDNode<"SPISD::TLS_ADD", SDTSPtlsadd>;
161 def tlsld : SDNode<"SPISD::TLS_LD", SDTSPtlsld>;
162 def tlscall : SDNode<"SPISD::TLS_CALL", SDT_SPCall,
163 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue,
166 def getPCX : Operand<i32> {
167 let PrintMethod = "printGetPCX";
170 //===----------------------------------------------------------------------===//
171 // SPARC Flag Conditions
172 //===----------------------------------------------------------------------===//
174 // Note that these values must be kept in sync with the CCOp::CondCode enum
176 class ICC_VAL<int N> : PatLeaf<(i32 N)>;
177 def ICC_NE : ICC_VAL< 9>; // Not Equal
178 def ICC_E : ICC_VAL< 1>; // Equal
179 def ICC_G : ICC_VAL<10>; // Greater
180 def ICC_LE : ICC_VAL< 2>; // Less or Equal
181 def ICC_GE : ICC_VAL<11>; // Greater or Equal
182 def ICC_L : ICC_VAL< 3>; // Less
183 def ICC_GU : ICC_VAL<12>; // Greater Unsigned
184 def ICC_LEU : ICC_VAL< 4>; // Less or Equal Unsigned
185 def ICC_CC : ICC_VAL<13>; // Carry Clear/Great or Equal Unsigned
186 def ICC_CS : ICC_VAL< 5>; // Carry Set/Less Unsigned
187 def ICC_POS : ICC_VAL<14>; // Positive
188 def ICC_NEG : ICC_VAL< 6>; // Negative
189 def ICC_VC : ICC_VAL<15>; // Overflow Clear
190 def ICC_VS : ICC_VAL< 7>; // Overflow Set
192 class FCC_VAL<int N> : PatLeaf<(i32 N)>;
193 def FCC_U : FCC_VAL<23>; // Unordered
194 def FCC_G : FCC_VAL<22>; // Greater
195 def FCC_UG : FCC_VAL<21>; // Unordered or Greater
196 def FCC_L : FCC_VAL<20>; // Less
197 def FCC_UL : FCC_VAL<19>; // Unordered or Less
198 def FCC_LG : FCC_VAL<18>; // Less or Greater
199 def FCC_NE : FCC_VAL<17>; // Not Equal
200 def FCC_E : FCC_VAL<25>; // Equal
201 def FCC_UE : FCC_VAL<24>; // Unordered or Equal
202 def FCC_GE : FCC_VAL<25>; // Greater or Equal
203 def FCC_UGE : FCC_VAL<26>; // Unordered or Greater or Equal
204 def FCC_LE : FCC_VAL<27>; // Less or Equal
205 def FCC_ULE : FCC_VAL<28>; // Unordered or Less or Equal
206 def FCC_O : FCC_VAL<29>; // Ordered
208 //===----------------------------------------------------------------------===//
209 // Instruction Class Templates
210 //===----------------------------------------------------------------------===//
212 /// F3_12 multiclass - Define a normal F3_1/F3_2 pattern in one shot.
213 multiclass F3_12<string OpcStr, bits<6> Op3Val, SDNode OpNode,
214 RegisterClass RC, ValueType Ty, Operand immOp> {
215 def rr : F3_1<2, Op3Val,
216 (outs RC:$dst), (ins RC:$b, RC:$c),
217 !strconcat(OpcStr, " $b, $c, $dst"),
218 [(set Ty:$dst, (OpNode Ty:$b, Ty:$c))]>;
219 def ri : F3_2<2, Op3Val,
220 (outs RC:$dst), (ins RC:$b, immOp:$c),
221 !strconcat(OpcStr, " $b, $c, $dst"),
222 [(set Ty:$dst, (OpNode Ty:$b, (Ty simm13:$c)))]>;
225 /// F3_12np multiclass - Define a normal F3_1/F3_2 pattern in one shot, with no
227 multiclass F3_12np<string OpcStr, bits<6> Op3Val> {
228 def rr : F3_1<2, Op3Val,
229 (outs IntRegs:$dst), (ins IntRegs:$b, IntRegs:$c),
230 !strconcat(OpcStr, " $b, $c, $dst"), []>;
231 def ri : F3_2<2, Op3Val,
232 (outs IntRegs:$dst), (ins IntRegs:$b, i32imm:$c),
233 !strconcat(OpcStr, " $b, $c, $dst"), []>;
236 //===----------------------------------------------------------------------===//
238 //===----------------------------------------------------------------------===//
240 // Pseudo instructions.
241 class Pseudo<dag outs, dag ins, string asmstr, list<dag> pattern>
242 : InstSP<outs, ins, asmstr, pattern>;
246 def GETPCX : Pseudo<(outs getPCX:$getpcseq), (ins), "$getpcseq", [] >;
249 let Defs = [O6], Uses = [O6] in {
250 def ADJCALLSTACKDOWN : Pseudo<(outs), (ins i32imm:$amt),
251 "!ADJCALLSTACKDOWN $amt",
252 [(callseq_start timm:$amt)]>;
253 def ADJCALLSTACKUP : Pseudo<(outs), (ins i32imm:$amt1, i32imm:$amt2),
254 "!ADJCALLSTACKUP $amt1",
255 [(callseq_end timm:$amt1, timm:$amt2)]>;
258 let hasSideEffects = 1, mayStore = 1 in {
259 let rd = 0, rs1 = 0, rs2 = 0 in
260 def FLUSHW : F3_1<0b10, 0b101011, (outs), (ins),
262 [(flushw)]>, Requires<[HasV9]>;
263 let rd = 0, rs1 = 1, simm13 = 3 in
264 def TA3 : F3_2<0b10, 0b111010, (outs), (ins),
270 def UNIMP : F2_1<0b000, (outs), (ins i32imm:$val),
273 // SELECT_CC_* - Used to implement the SELECT_CC DAG operation. Expanded after
274 // instruction selection into a branch sequence. This has to handle all
275 // permutations of selection between i32/f32/f64 on ICC and FCC.
276 // Expanded after instruction selection.
277 let Uses = [ICC], usesCustomInserter = 1 in {
278 def SELECT_CC_Int_ICC
279 : Pseudo<(outs IntRegs:$dst), (ins IntRegs:$T, IntRegs:$F, i32imm:$Cond),
280 "; SELECT_CC_Int_ICC PSEUDO!",
281 [(set i32:$dst, (SPselecticc i32:$T, i32:$F, imm:$Cond))]>;
283 : Pseudo<(outs FPRegs:$dst), (ins FPRegs:$T, FPRegs:$F, i32imm:$Cond),
284 "; SELECT_CC_FP_ICC PSEUDO!",
285 [(set f32:$dst, (SPselecticc f32:$T, f32:$F, imm:$Cond))]>;
287 def SELECT_CC_DFP_ICC
288 : Pseudo<(outs DFPRegs:$dst), (ins DFPRegs:$T, DFPRegs:$F, i32imm:$Cond),
289 "; SELECT_CC_DFP_ICC PSEUDO!",
290 [(set f64:$dst, (SPselecticc f64:$T, f64:$F, imm:$Cond))]>;
292 def SELECT_CC_QFP_ICC
293 : Pseudo<(outs QFPRegs:$dst), (ins QFPRegs:$T, QFPRegs:$F, i32imm:$Cond),
294 "; SELECT_CC_QFP_ICC PSEUDO!",
295 [(set f128:$dst, (SPselecticc f128:$T, f128:$F, imm:$Cond))]>;
298 let usesCustomInserter = 1, Uses = [FCC] in {
300 def SELECT_CC_Int_FCC
301 : Pseudo<(outs IntRegs:$dst), (ins IntRegs:$T, IntRegs:$F, i32imm:$Cond),
302 "; SELECT_CC_Int_FCC PSEUDO!",
303 [(set i32:$dst, (SPselectfcc i32:$T, i32:$F, imm:$Cond))]>;
306 : Pseudo<(outs FPRegs:$dst), (ins FPRegs:$T, FPRegs:$F, i32imm:$Cond),
307 "; SELECT_CC_FP_FCC PSEUDO!",
308 [(set f32:$dst, (SPselectfcc f32:$T, f32:$F, imm:$Cond))]>;
309 def SELECT_CC_DFP_FCC
310 : Pseudo<(outs DFPRegs:$dst), (ins DFPRegs:$T, DFPRegs:$F, i32imm:$Cond),
311 "; SELECT_CC_DFP_FCC PSEUDO!",
312 [(set f64:$dst, (SPselectfcc f64:$T, f64:$F, imm:$Cond))]>;
313 def SELECT_CC_QFP_FCC
314 : Pseudo<(outs QFPRegs:$dst), (ins QFPRegs:$T, QFPRegs:$F, i32imm:$Cond),
315 "; SELECT_CC_QFP_FCC PSEUDO!",
316 [(set f128:$dst, (SPselectfcc f128:$T, f128:$F, imm:$Cond))]>;
320 // Section A.3 - Synthetic Instructions, p. 85
321 // special cases of JMPL:
322 let isReturn = 1, isTerminator = 1, hasDelaySlot = 1, isBarrier = 1 in {
323 let rd = 0, rs1 = 15 in
324 def RETL: F3_2<2, 0b111000, (outs), (ins i32imm:$val),
325 "jmp %o7+$val", [(retflag simm13:$val)]>;
327 let rd = 0, rs1 = 31 in
328 def RET: F3_2<2, 0b111000, (outs), (ins i32imm:$val),
332 // Section B.1 - Load Integer Instructions, p. 90
333 def LDSBrr : F3_1<3, 0b001001,
334 (outs IntRegs:$dst), (ins MEMrr:$addr),
335 "ldsb [$addr], $dst",
336 [(set i32:$dst, (sextloadi8 ADDRrr:$addr))]>;
337 def LDSBri : F3_2<3, 0b001001,
338 (outs IntRegs:$dst), (ins MEMri:$addr),
339 "ldsb [$addr], $dst",
340 [(set i32:$dst, (sextloadi8 ADDRri:$addr))]>;
341 def LDSHrr : F3_1<3, 0b001010,
342 (outs IntRegs:$dst), (ins MEMrr:$addr),
343 "ldsh [$addr], $dst",
344 [(set i32:$dst, (sextloadi16 ADDRrr:$addr))]>;
345 def LDSHri : F3_2<3, 0b001010,
346 (outs IntRegs:$dst), (ins MEMri:$addr),
347 "ldsh [$addr], $dst",
348 [(set i32:$dst, (sextloadi16 ADDRri:$addr))]>;
349 def LDUBrr : F3_1<3, 0b000001,
350 (outs IntRegs:$dst), (ins MEMrr:$addr),
351 "ldub [$addr], $dst",
352 [(set i32:$dst, (zextloadi8 ADDRrr:$addr))]>;
353 def LDUBri : F3_2<3, 0b000001,
354 (outs IntRegs:$dst), (ins MEMri:$addr),
355 "ldub [$addr], $dst",
356 [(set i32:$dst, (zextloadi8 ADDRri:$addr))]>;
357 def LDUHrr : F3_1<3, 0b000010,
358 (outs IntRegs:$dst), (ins MEMrr:$addr),
359 "lduh [$addr], $dst",
360 [(set i32:$dst, (zextloadi16 ADDRrr:$addr))]>;
361 def LDUHri : F3_2<3, 0b000010,
362 (outs IntRegs:$dst), (ins MEMri:$addr),
363 "lduh [$addr], $dst",
364 [(set i32:$dst, (zextloadi16 ADDRri:$addr))]>;
365 def LDrr : F3_1<3, 0b000000,
366 (outs IntRegs:$dst), (ins MEMrr:$addr),
368 [(set i32:$dst, (load ADDRrr:$addr))]>;
369 def LDri : F3_2<3, 0b000000,
370 (outs IntRegs:$dst), (ins MEMri:$addr),
372 [(set i32:$dst, (load ADDRri:$addr))]>;
374 // Section B.2 - Load Floating-point Instructions, p. 92
375 def LDFrr : F3_1<3, 0b100000,
376 (outs FPRegs:$dst), (ins MEMrr:$addr),
378 [(set f32:$dst, (load ADDRrr:$addr))]>;
379 def LDFri : F3_2<3, 0b100000,
380 (outs FPRegs:$dst), (ins MEMri:$addr),
382 [(set f32:$dst, (load ADDRri:$addr))]>;
383 def LDDFrr : F3_1<3, 0b100011,
384 (outs DFPRegs:$dst), (ins MEMrr:$addr),
386 [(set f64:$dst, (load ADDRrr:$addr))]>;
387 def LDDFri : F3_2<3, 0b100011,
388 (outs DFPRegs:$dst), (ins MEMri:$addr),
390 [(set f64:$dst, (load ADDRri:$addr))]>;
391 def LDQFrr : F3_1<3, 0b100010,
392 (outs QFPRegs:$dst), (ins MEMrr:$addr),
394 [(set f128:$dst, (load ADDRrr:$addr))]>,
395 Requires<[HasV9, HasHardQuad]>;
396 def LDQFri : F3_2<3, 0b100010,
397 (outs QFPRegs:$dst), (ins MEMri:$addr),
399 [(set f128:$dst, (load ADDRri:$addr))]>,
400 Requires<[HasV9, HasHardQuad]>;
402 // Section B.4 - Store Integer Instructions, p. 95
403 def STBrr : F3_1<3, 0b000101,
404 (outs), (ins MEMrr:$addr, IntRegs:$rd),
406 [(truncstorei8 i32:$rd, ADDRrr:$addr)]>;
407 def STBri : F3_2<3, 0b000101,
408 (outs), (ins MEMri:$addr, IntRegs:$rd),
410 [(truncstorei8 i32:$rd, ADDRri:$addr)]>;
411 def STHrr : F3_1<3, 0b000110,
412 (outs), (ins MEMrr:$addr, IntRegs:$rd),
414 [(truncstorei16 i32:$rd, ADDRrr:$addr)]>;
415 def STHri : F3_2<3, 0b000110,
416 (outs), (ins MEMri:$addr, IntRegs:$rd),
418 [(truncstorei16 i32:$rd, ADDRri:$addr)]>;
419 def STrr : F3_1<3, 0b000100,
420 (outs), (ins MEMrr:$addr, IntRegs:$rd),
422 [(store i32:$rd, ADDRrr:$addr)]>;
423 def STri : F3_2<3, 0b000100,
424 (outs), (ins MEMri:$addr, IntRegs:$rd),
426 [(store i32:$rd, ADDRri:$addr)]>;
428 // Section B.5 - Store Floating-point Instructions, p. 97
429 def STFrr : F3_1<3, 0b100100,
430 (outs), (ins MEMrr:$addr, FPRegs:$rd),
432 [(store f32:$rd, ADDRrr:$addr)]>;
433 def STFri : F3_2<3, 0b100100,
434 (outs), (ins MEMri:$addr, FPRegs:$rd),
436 [(store f32:$rd, ADDRri:$addr)]>;
437 def STDFrr : F3_1<3, 0b100111,
438 (outs), (ins MEMrr:$addr, DFPRegs:$rd),
440 [(store f64:$rd, ADDRrr:$addr)]>;
441 def STDFri : F3_2<3, 0b100111,
442 (outs), (ins MEMri:$addr, DFPRegs:$rd),
444 [(store f64:$rd, ADDRri:$addr)]>;
445 def STQFrr : F3_1<3, 0b100110,
446 (outs), (ins MEMrr:$addr, QFPRegs:$rd),
448 [(store f128:$rd, ADDRrr:$addr)]>,
449 Requires<[HasV9, HasHardQuad]>;
450 def STQFri : F3_2<3, 0b100110,
451 (outs), (ins MEMri:$addr, QFPRegs:$rd),
453 [(store f128:$rd, ADDRri:$addr)]>,
454 Requires<[HasV9, HasHardQuad]>;
456 // Section B.9 - SETHI Instruction, p. 104
457 def SETHIi: F2_1<0b100,
458 (outs IntRegs:$rd), (ins i32imm:$imm22),
460 [(set i32:$rd, SETHIimm:$imm22)]>;
462 // Section B.10 - NOP Instruction, p. 105
463 // (It's a special case of SETHI)
464 let rd = 0, imm22 = 0 in
465 def NOP : F2_1<0b100, (outs), (ins), "nop", []>;
467 // Section B.11 - Logical Instructions, p. 106
468 defm AND : F3_12<"and", 0b000001, and, IntRegs, i32, i32imm>;
470 def ANDNrr : F3_1<2, 0b000101,
471 (outs IntRegs:$dst), (ins IntRegs:$b, IntRegs:$c),
473 [(set i32:$dst, (and i32:$b, (not i32:$c)))]>;
474 def ANDNri : F3_2<2, 0b000101,
475 (outs IntRegs:$dst), (ins IntRegs:$b, i32imm:$c),
476 "andn $b, $c, $dst", []>;
478 defm OR : F3_12<"or", 0b000010, or, IntRegs, i32, i32imm>;
480 def ORNrr : F3_1<2, 0b000110,
481 (outs IntRegs:$dst), (ins IntRegs:$b, IntRegs:$c),
483 [(set i32:$dst, (or i32:$b, (not i32:$c)))]>;
484 def ORNri : F3_2<2, 0b000110,
485 (outs IntRegs:$dst), (ins IntRegs:$b, i32imm:$c),
486 "orn $b, $c, $dst", []>;
487 defm XOR : F3_12<"xor", 0b000011, xor, IntRegs, i32, i32imm>;
489 def XNORrr : F3_1<2, 0b000111,
490 (outs IntRegs:$dst), (ins IntRegs:$b, IntRegs:$c),
492 [(set i32:$dst, (not (xor i32:$b, i32:$c)))]>;
493 def XNORri : F3_2<2, 0b000111,
494 (outs IntRegs:$dst), (ins IntRegs:$b, i32imm:$c),
495 "xnor $b, $c, $dst", []>;
497 // Section B.12 - Shift Instructions, p. 107
498 defm SLL : F3_12<"sll", 0b100101, shl, IntRegs, i32, i32imm>;
499 defm SRL : F3_12<"srl", 0b100110, srl, IntRegs, i32, i32imm>;
500 defm SRA : F3_12<"sra", 0b100111, sra, IntRegs, i32, i32imm>;
502 // Section B.13 - Add Instructions, p. 108
503 defm ADD : F3_12<"add", 0b000000, add, IntRegs, i32, i32imm>;
505 // "LEA" forms of add (patterns to make tblgen happy)
506 let Predicates = [Is32Bit] in
507 def LEA_ADDri : F3_2<2, 0b000000,
508 (outs IntRegs:$dst), (ins MEMri:$addr),
509 "add ${addr:arith}, $dst",
510 [(set iPTR:$dst, ADDRri:$addr)]>;
513 defm ADDCC : F3_12<"addcc", 0b010000, addc, IntRegs, i32, i32imm>;
515 let Uses = [ICC], Defs = [ICC] in
516 defm ADDE : F3_12<"addxcc", 0b011000, adde, IntRegs, i32, i32imm>;
518 // Section B.15 - Subtract Instructions, p. 110
519 defm SUB : F3_12 <"sub" , 0b000100, sub, IntRegs, i32, i32imm>;
520 let Uses = [ICC], Defs = [ICC] in
521 defm SUBE : F3_12 <"subxcc" , 0b011100, sube, IntRegs, i32, i32imm>;
524 defm SUBCC : F3_12 <"subcc", 0b010100, subc, IntRegs, i32, i32imm>;
526 let Defs = [ICC], rd = 0 in {
527 def CMPrr : F3_1<2, 0b010100,
528 (outs), (ins IntRegs:$b, IntRegs:$c),
530 [(SPcmpicc i32:$b, i32:$c)]>;
531 def CMPri : F3_2<2, 0b010100,
532 (outs), (ins IntRegs:$b, i32imm:$c),
534 [(SPcmpicc i32:$b, (i32 simm13:$c))]>;
537 let Uses = [ICC], Defs = [ICC] in
538 def SUBXCCrr: F3_1<2, 0b011100,
539 (outs IntRegs:$dst), (ins IntRegs:$b, IntRegs:$c),
540 "subxcc $b, $c, $dst", []>;
543 // Section B.18 - Multiply Instructions, p. 113
545 defm UMUL : F3_12np<"umul", 0b001010>;
546 defm SMUL : F3_12 <"smul", 0b001011, mul, IntRegs, i32, i32imm>;
549 // Section B.19 - Divide Instructions, p. 115
551 defm UDIV : F3_12np<"udiv", 0b001110>;
552 defm SDIV : F3_12np<"sdiv", 0b001111>;
555 // Section B.20 - SAVE and RESTORE, p. 117
556 defm SAVE : F3_12np<"save" , 0b111100>;
557 defm RESTORE : F3_12np<"restore", 0b111101>;
559 // Section B.21 - Branch on Integer Condition Codes Instructions, p. 119
561 // unconditional branch class.
562 class BranchAlways<dag ins, string asmstr, list<dag> pattern>
563 : F2_2<0b010, (outs), ins, asmstr, pattern> {
565 let isTerminator = 1;
566 let hasDelaySlot = 1;
571 def BA : BranchAlways<(ins brtarget:$imm22), "ba $imm22", [(br bb:$imm22)]>;
573 // conditional branch class:
574 class BranchSP<dag ins, string asmstr, list<dag> pattern>
575 : F2_2<0b010, (outs), ins, asmstr, pattern> {
577 let isTerminator = 1;
578 let hasDelaySlot = 1;
581 // Indirect branch instructions.
582 let isTerminator = 1, isBarrier = 1,
583 hasDelaySlot = 1, isBranch =1,
584 isIndirectBranch = 1, rd = 0 in {
585 def BINDrr : F3_1<2, 0b111000,
586 (outs), (ins MEMrr:$ptr),
588 [(brind ADDRrr:$ptr)]>;
589 def BINDri : F3_2<2, 0b111000,
590 (outs), (ins MEMri:$ptr),
592 [(brind ADDRri:$ptr)]>;
596 def BCOND : BranchSP<(ins brtarget:$imm22, CCOp:$cond),
598 [(SPbricc bb:$imm22, imm:$cond)]>;
600 // Section B.22 - Branch on Floating-point Condition Codes Instructions, p. 121
602 // floating-point conditional branch class:
603 class FPBranchSP<dag ins, string asmstr, list<dag> pattern>
604 : F2_2<0b110, (outs), ins, asmstr, pattern> {
606 let isTerminator = 1;
607 let hasDelaySlot = 1;
611 def FBCOND : FPBranchSP<(ins brtarget:$imm22, CCOp:$cond),
613 [(SPbrfcc bb:$imm22, imm:$cond)]>;
616 // Section B.24 - Call and Link Instruction, p. 125
617 // This is the only Format 1 instruction
619 hasDelaySlot = 1, isCall = 1 in {
620 def CALL : InstSP<(outs), (ins calltarget:$dst, variable_ops),
624 let Inst{29-0} = disp;
628 def JMPLrr : F3_1<2, 0b111000,
629 (outs), (ins MEMrr:$ptr, variable_ops),
631 [(call ADDRrr:$ptr)]> { let rd = 15; }
632 def JMPLri : F3_2<2, 0b111000,
633 (outs), (ins MEMri:$ptr, variable_ops),
635 [(call ADDRri:$ptr)]> { let rd = 15; }
638 // Section B.28 - Read State Register Instructions
639 let Uses = [Y], rs1 = 0, rs2 = 0 in
640 def RDY : F3_1<2, 0b101000,
641 (outs IntRegs:$dst), (ins),
644 // Section B.29 - Write State Register Instructions
645 let Defs = [Y], rd = 0 in {
646 def WRYrr : F3_1<2, 0b110000,
647 (outs), (ins IntRegs:$b, IntRegs:$c),
648 "wr $b, $c, %y", []>;
649 def WRYri : F3_2<2, 0b110000,
650 (outs), (ins IntRegs:$b, i32imm:$c),
651 "wr $b, $c, %y", []>;
653 // Convert Integer to Floating-point Instructions, p. 141
654 def FITOS : F3_3u<2, 0b110100, 0b011000100,
655 (outs FPRegs:$dst), (ins FPRegs:$src),
657 [(set FPRegs:$dst, (SPitof FPRegs:$src))]>;
658 def FITOD : F3_3u<2, 0b110100, 0b011001000,
659 (outs DFPRegs:$dst), (ins FPRegs:$src),
661 [(set DFPRegs:$dst, (SPitof FPRegs:$src))]>;
662 def FITOQ : F3_3u<2, 0b110100, 0b011001100,
663 (outs QFPRegs:$dst), (ins FPRegs:$src),
665 [(set QFPRegs:$dst, (SPitof FPRegs:$src))]>,
666 Requires<[HasHardQuad]>;
668 // Convert Floating-point to Integer Instructions, p. 142
669 def FSTOI : F3_3u<2, 0b110100, 0b011010001,
670 (outs FPRegs:$dst), (ins FPRegs:$src),
672 [(set FPRegs:$dst, (SPftoi FPRegs:$src))]>;
673 def FDTOI : F3_3u<2, 0b110100, 0b011010010,
674 (outs FPRegs:$dst), (ins DFPRegs:$src),
676 [(set FPRegs:$dst, (SPftoi DFPRegs:$src))]>;
677 def FQTOI : F3_3u<2, 0b110100, 0b011010011,
678 (outs FPRegs:$dst), (ins QFPRegs:$src),
680 [(set FPRegs:$dst, (SPftoi QFPRegs:$src))]>,
681 Requires<[HasHardQuad]>;
683 // Convert between Floating-point Formats Instructions, p. 143
684 def FSTOD : F3_3u<2, 0b110100, 0b011001001,
685 (outs DFPRegs:$dst), (ins FPRegs:$src),
687 [(set f64:$dst, (fextend f32:$src))]>;
688 def FSTOQ : F3_3u<2, 0b110100, 0b011001101,
689 (outs QFPRegs:$dst), (ins FPRegs:$src),
691 [(set f128:$dst, (fextend f32:$src))]>,
692 Requires<[HasHardQuad]>;
693 def FDTOS : F3_3u<2, 0b110100, 0b011000110,
694 (outs FPRegs:$dst), (ins DFPRegs:$src),
696 [(set f32:$dst, (fround f64:$src))]>;
697 def FDTOQ : F3_3u<2, 0b110100, 0b01101110,
698 (outs QFPRegs:$dst), (ins DFPRegs:$src),
700 [(set f128:$dst, (fextend f64:$src))]>,
701 Requires<[HasHardQuad]>;
702 def FQTOS : F3_3u<2, 0b110100, 0b011000111,
703 (outs FPRegs:$dst), (ins QFPRegs:$src),
705 [(set f32:$dst, (fround f128:$src))]>,
706 Requires<[HasHardQuad]>;
707 def FQTOD : F3_3u<2, 0b110100, 0b011001011,
708 (outs DFPRegs:$dst), (ins QFPRegs:$src),
710 [(set f64:$dst, (fround f128:$src))]>,
711 Requires<[HasHardQuad]>;
713 // Floating-point Move Instructions, p. 144
714 def FMOVS : F3_3u<2, 0b110100, 0b000000001,
715 (outs FPRegs:$dst), (ins FPRegs:$src),
716 "fmovs $src, $dst", []>;
717 def FNEGS : F3_3u<2, 0b110100, 0b000000101,
718 (outs FPRegs:$dst), (ins FPRegs:$src),
720 [(set f32:$dst, (fneg f32:$src))]>;
721 def FABSS : F3_3u<2, 0b110100, 0b000001001,
722 (outs FPRegs:$dst), (ins FPRegs:$src),
724 [(set f32:$dst, (fabs f32:$src))]>;
727 // Floating-point Square Root Instructions, p.145
728 def FSQRTS : F3_3u<2, 0b110100, 0b000101001,
729 (outs FPRegs:$dst), (ins FPRegs:$src),
731 [(set f32:$dst, (fsqrt f32:$src))]>;
732 def FSQRTD : F3_3u<2, 0b110100, 0b000101010,
733 (outs DFPRegs:$dst), (ins DFPRegs:$src),
735 [(set f64:$dst, (fsqrt f64:$src))]>;
736 def FSQRTQ : F3_3u<2, 0b110100, 0b000101011,
737 (outs QFPRegs:$dst), (ins QFPRegs:$src),
739 [(set f128:$dst, (fsqrt f128:$src))]>,
740 Requires<[HasHardQuad]>;
744 // Floating-point Add and Subtract Instructions, p. 146
745 def FADDS : F3_3<2, 0b110100, 0b001000001,
746 (outs FPRegs:$dst), (ins FPRegs:$src1, FPRegs:$src2),
747 "fadds $src1, $src2, $dst",
748 [(set f32:$dst, (fadd f32:$src1, f32:$src2))]>;
749 def FADDD : F3_3<2, 0b110100, 0b001000010,
750 (outs DFPRegs:$dst), (ins DFPRegs:$src1, DFPRegs:$src2),
751 "faddd $src1, $src2, $dst",
752 [(set f64:$dst, (fadd f64:$src1, f64:$src2))]>;
753 def FADDQ : F3_3<2, 0b110100, 0b001000011,
754 (outs QFPRegs:$dst), (ins QFPRegs:$src1, QFPRegs:$src2),
755 "faddq $src1, $src2, $dst",
756 [(set f128:$dst, (fadd f128:$src1, f128:$src2))]>,
757 Requires<[HasHardQuad]>;
759 def FSUBS : F3_3<2, 0b110100, 0b001000101,
760 (outs FPRegs:$dst), (ins FPRegs:$src1, FPRegs:$src2),
761 "fsubs $src1, $src2, $dst",
762 [(set f32:$dst, (fsub f32:$src1, f32:$src2))]>;
763 def FSUBD : F3_3<2, 0b110100, 0b001000110,
764 (outs DFPRegs:$dst), (ins DFPRegs:$src1, DFPRegs:$src2),
765 "fsubd $src1, $src2, $dst",
766 [(set f64:$dst, (fsub f64:$src1, f64:$src2))]>;
767 def FSUBQ : F3_3<2, 0b110100, 0b001000111,
768 (outs QFPRegs:$dst), (ins QFPRegs:$src1, QFPRegs:$src2),
769 "fsubq $src1, $src2, $dst",
770 [(set f128:$dst, (fsub f128:$src1, f128:$src2))]>,
771 Requires<[HasHardQuad]>;
774 // Floating-point Multiply and Divide Instructions, p. 147
775 def FMULS : F3_3<2, 0b110100, 0b001001001,
776 (outs FPRegs:$dst), (ins FPRegs:$src1, FPRegs:$src2),
777 "fmuls $src1, $src2, $dst",
778 [(set f32:$dst, (fmul f32:$src1, f32:$src2))]>;
779 def FMULD : F3_3<2, 0b110100, 0b001001010,
780 (outs DFPRegs:$dst), (ins DFPRegs:$src1, DFPRegs:$src2),
781 "fmuld $src1, $src2, $dst",
782 [(set f64:$dst, (fmul f64:$src1, f64:$src2))]>;
783 def FMULQ : F3_3<2, 0b110100, 0b001001011,
784 (outs QFPRegs:$dst), (ins QFPRegs:$src1, QFPRegs:$src2),
785 "fmulq $src1, $src2, $dst",
786 [(set f128:$dst, (fmul f128:$src1, f128:$src2))]>,
787 Requires<[HasHardQuad]>;
789 def FSMULD : F3_3<2, 0b110100, 0b001101001,
790 (outs DFPRegs:$dst), (ins FPRegs:$src1, FPRegs:$src2),
791 "fsmuld $src1, $src2, $dst",
792 [(set f64:$dst, (fmul (fextend f32:$src1),
793 (fextend f32:$src2)))]>;
794 def FDMULQ : F3_3<2, 0b110100, 0b001101110,
795 (outs QFPRegs:$dst), (ins DFPRegs:$src1, DFPRegs:$src2),
796 "fdmulq $src1, $src2, $dst",
797 [(set f128:$dst, (fmul (fextend f64:$src1),
798 (fextend f64:$src2)))]>,
799 Requires<[HasHardQuad]>;
801 def FDIVS : F3_3<2, 0b110100, 0b001001101,
802 (outs FPRegs:$dst), (ins FPRegs:$src1, FPRegs:$src2),
803 "fdivs $src1, $src2, $dst",
804 [(set f32:$dst, (fdiv f32:$src1, f32:$src2))]>;
805 def FDIVD : F3_3<2, 0b110100, 0b001001110,
806 (outs DFPRegs:$dst), (ins DFPRegs:$src1, DFPRegs:$src2),
807 "fdivd $src1, $src2, $dst",
808 [(set f64:$dst, (fdiv f64:$src1, f64:$src2))]>;
809 def FDIVQ : F3_3<2, 0b110100, 0b001001111,
810 (outs QFPRegs:$dst), (ins QFPRegs:$src1, QFPRegs:$src2),
811 "fdivq $src1, $src2, $dst",
812 [(set f128:$dst, (fdiv f128:$src1, f128:$src2))]>,
813 Requires<[HasHardQuad]>;
815 // Floating-point Compare Instructions, p. 148
816 // Note: the 2nd template arg is different for these guys.
817 // Note 2: the result of a FCMP is not available until the 2nd cycle
818 // after the instr is retired, but there is no interlock in Sparc V8.
819 // This behavior is modeled with a forced noop after the instruction in
822 let Defs = [FCC] in {
823 def FCMPS : F3_3c<2, 0b110101, 0b001010001,
824 (outs), (ins FPRegs:$src1, FPRegs:$src2),
825 "fcmps $src1, $src2",
826 [(SPcmpfcc f32:$src1, f32:$src2)]>;
827 def FCMPD : F3_3c<2, 0b110101, 0b001010010,
828 (outs), (ins DFPRegs:$src1, DFPRegs:$src2),
829 "fcmpd $src1, $src2",
830 [(SPcmpfcc f64:$src1, f64:$src2)]>;
831 def FCMPQ : F3_3c<2, 0b110101, 0b001010011,
832 (outs), (ins QFPRegs:$src1, QFPRegs:$src2),
833 "fcmpq $src1, $src2",
834 [(SPcmpfcc f128:$src1, f128:$src2)]>,
835 Requires<[HasHardQuad]>;
838 //===----------------------------------------------------------------------===//
839 // Instructions for Thread Local Storage(TLS).
840 //===----------------------------------------------------------------------===//
842 def TLS_ADDrr : F3_1<2, 0b000000,
844 (ins IntRegs:$rs1, IntRegs:$rs2, TLSSym:$sym),
845 "add $rs1, $rs2, $rd, $sym",
847 (tlsadd i32:$rs1, i32:$rs2, tglobaltlsaddr:$sym))]>;
850 def TLS_LDrr : F3_1<3, 0b000000,
851 (outs IntRegs:$dst), (ins MEMrr:$addr, TLSSym:$sym),
852 "ld [$addr], $dst, $sym",
854 (tlsld ADDRrr:$addr, tglobaltlsaddr:$sym))]>;
856 let Uses = [O6], isCall = 1, hasDelaySlot = 1 in
857 def TLS_CALL : InstSP<(outs),
858 (ins calltarget:$disp, TLSSym:$sym, variable_ops),
860 [(tlscall texternalsym:$disp, tglobaltlsaddr:$sym)]> {
863 let Inst{29-0} = disp;
866 //===----------------------------------------------------------------------===//
868 //===----------------------------------------------------------------------===//
870 // V9 Conditional Moves.
871 let Predicates = [HasV9], Constraints = "$f = $rd" in {
872 // Move Integer Register on Condition (MOVcc) p. 194 of the V9 manual.
873 let Uses = [ICC], cc = 0b100 in {
875 : F4_1<0b101100, (outs IntRegs:$rd),
876 (ins IntRegs:$rs2, IntRegs:$f, CCOp:$cond),
877 "mov$cond %icc, $rs2, $rd",
878 [(set i32:$rd, (SPselecticc i32:$rs2, i32:$f, imm:$cond))]>;
881 : F4_2<0b101100, (outs IntRegs:$rd),
882 (ins i32imm:$simm11, IntRegs:$f, CCOp:$cond),
883 "mov$cond %icc, $simm11, $rd",
885 (SPselecticc simm11:$simm11, i32:$f, imm:$cond))]>;
888 let Uses = [FCC], cc = 0b000 in {
890 : F4_1<0b101100, (outs IntRegs:$rd),
891 (ins IntRegs:$rs2, IntRegs:$f, CCOp:$cond),
892 "mov$cond %fcc0, $rs2, $rd",
893 [(set i32:$rd, (SPselectfcc i32:$rs2, i32:$f, imm:$cond))]>;
895 : F4_2<0b101100, (outs IntRegs:$rd),
896 (ins i32imm:$simm11, IntRegs:$f, CCOp:$cond),
897 "mov$cond %fcc0, $simm11, $rd",
899 (SPselectfcc simm11:$simm11, i32:$f, imm:$cond))]>;
902 let Uses = [ICC], opf_cc = 0b100 in {
904 : F4_3<0b110101, 0b000001, (outs FPRegs:$rd),
905 (ins FPRegs:$rs2, FPRegs:$f, CCOp:$cond),
906 "fmovs$cond %icc, $rs2, $rd",
907 [(set f32:$rd, (SPselecticc f32:$rs2, f32:$f, imm:$cond))]>;
909 : F4_3<0b110101, 0b000010, (outs DFPRegs:$rd),
910 (ins DFPRegs:$rs2, DFPRegs:$f, CCOp:$cond),
911 "fmovd$cond %icc, $rs2, $rd",
912 [(set f64:$rd, (SPselecticc f64:$rs2, f64:$f, imm:$cond))]>;
914 : F4_3<0b110101, 0b000011, (outs QFPRegs:$rd),
915 (ins QFPRegs:$rs2, QFPRegs:$f, CCOp:$cond),
916 "fmovd$cond %icc, $rs2, $rd",
917 [(set f128:$rd, (SPselecticc f128:$rs2, f128:$f, imm:$cond))]>;
920 let Uses = [FCC], opf_cc = 0b000 in {
922 : F4_3<0b110101, 0b000001, (outs FPRegs:$rd),
923 (ins FPRegs:$rs2, FPRegs:$f, CCOp:$cond),
924 "fmovs$cond %fcc0, $rs2, $rd",
925 [(set f32:$rd, (SPselectfcc f32:$rs2, f32:$f, imm:$cond))]>;
927 : F4_3<0b110101, 0b000010, (outs DFPRegs:$rd),
928 (ins DFPRegs:$rs2, DFPRegs:$f, CCOp:$cond),
929 "fmovd$cond %fcc0, $rs2, $rd",
930 [(set f64:$rd, (SPselectfcc f64:$rs2, f64:$f, imm:$cond))]>;
932 : F4_3<0b110101, 0b000011, (outs QFPRegs:$rd),
933 (ins QFPRegs:$rs2, QFPRegs:$f, CCOp:$cond),
934 "fmovd$cond %fcc0, $rs2, $rd",
935 [(set f128:$rd, (SPselectfcc f128:$rs2, f128:$f, imm:$cond))]>;
940 // Floating-Point Move Instructions, p. 164 of the V9 manual.
941 let Predicates = [HasV9] in {
942 def FMOVD : F3_3u<2, 0b110100, 0b000000010,
943 (outs DFPRegs:$dst), (ins DFPRegs:$src),
944 "fmovd $src, $dst", []>;
945 def FMOVQ : F3_3u<2, 0b110100, 0b000000011,
946 (outs QFPRegs:$dst), (ins QFPRegs:$src),
947 "fmovq $src, $dst", []>,
948 Requires<[HasHardQuad]>;
949 def FNEGD : F3_3u<2, 0b110100, 0b000000110,
950 (outs DFPRegs:$dst), (ins DFPRegs:$src),
952 [(set f64:$dst, (fneg f64:$src))]>;
953 def FNEGQ : F3_3u<2, 0b110100, 0b000000111,
954 (outs QFPRegs:$dst), (ins QFPRegs:$src),
956 [(set f128:$dst, (fneg f128:$src))]>,
957 Requires<[HasHardQuad]>;
958 def FABSD : F3_3u<2, 0b110100, 0b000001010,
959 (outs DFPRegs:$dst), (ins DFPRegs:$src),
961 [(set f64:$dst, (fabs f64:$src))]>;
962 def FABSQ : F3_3u<2, 0b110100, 0b000001011,
963 (outs QFPRegs:$dst), (ins QFPRegs:$src),
965 [(set f128:$dst, (fabs f128:$src))]>,
966 Requires<[HasHardQuad]>;
969 // POPCrr - This does a ctpop of a 64-bit register. As such, we have to clear
970 // the top 32-bits before using it. To do this clearing, we use a SRLri X,0.
972 def POPCrr : F3_1<2, 0b101110,
973 (outs IntRegs:$dst), (ins IntRegs:$src),
974 "popc $src, $dst", []>, Requires<[HasV9]>;
975 def : Pat<(ctpop i32:$src),
976 (POPCrr (SRLri $src, 0))>;
979 let hasSideEffects =1, rd = 0, rs1 = 0b01111, rs2 = 0 in
980 def STBAR : F3_1<2, 0b101000, (outs), (ins), "stbar", []>;
982 let Predicates = [HasV9], hasSideEffects = 1, rd = 0, rs1 = 0b01111 in
983 def MEMBARi : F3_2<2, 0b101000, (outs), (ins i32imm:$simm13),
984 "membar $simm13", []>;
986 let Constraints = "$val = $rd" in {
987 def SWAPrr : F3_1<3, 0b001111,
988 (outs IntRegs:$rd), (ins IntRegs:$val, MEMrr:$addr),
990 [(set i32:$rd, (atomic_swap_32 ADDRrr:$addr, i32:$val))]>;
991 def SWAPri : F3_2<3, 0b001111,
992 (outs IntRegs:$rd), (ins IntRegs:$val, MEMri:$addr),
994 [(set i32:$rd, (atomic_swap_32 ADDRri:$addr, i32:$val))]>;
997 let Predicates = [HasV9], Constraints = "$swap = $rd" in
998 def CASrr: F3_1<3, 0b111100,
999 (outs IntRegs:$rd), (ins IntRegs:$rs1, IntRegs:$rs2,
1001 "cas [$rs1], $rs2, $rd",
1003 (atomic_cmp_swap iPTR:$rs1, i32:$rs2, i32:$swap))]>;
1005 //===----------------------------------------------------------------------===//
1006 // Non-Instruction Patterns
1007 //===----------------------------------------------------------------------===//
1009 // Small immediates.
1010 def : Pat<(i32 simm13:$val),
1011 (ORri (i32 G0), imm:$val)>;
1012 // Arbitrary immediates.
1013 def : Pat<(i32 imm:$val),
1014 (ORri (SETHIi (HI22 imm:$val)), (LO10 imm:$val))>;
1017 // Global addresses, constant pool entries
1018 let Predicates = [Is32Bit] in {
1020 def : Pat<(SPhi tglobaladdr:$in), (SETHIi tglobaladdr:$in)>;
1021 def : Pat<(SPlo tglobaladdr:$in), (ORri (i32 G0), tglobaladdr:$in)>;
1022 def : Pat<(SPhi tconstpool:$in), (SETHIi tconstpool:$in)>;
1023 def : Pat<(SPlo tconstpool:$in), (ORri (i32 G0), tconstpool:$in)>;
1025 // GlobalTLS addresses
1026 def : Pat<(SPhi tglobaltlsaddr:$in), (SETHIi tglobaltlsaddr:$in)>;
1027 def : Pat<(SPlo tglobaltlsaddr:$in), (ORri (i32 G0), tglobaltlsaddr:$in)>;
1028 def : Pat<(add (SPhi tglobaltlsaddr:$in1), (SPlo tglobaltlsaddr:$in2)),
1029 (ADDri (SETHIi tglobaltlsaddr:$in1), (tglobaltlsaddr:$in2))>;
1030 def : Pat<(xor (SPhi tglobaltlsaddr:$in1), (SPlo tglobaltlsaddr:$in2)),
1031 (XORri (SETHIi tglobaltlsaddr:$in1), (tglobaltlsaddr:$in2))>;
1034 def : Pat<(SPhi tblockaddress:$in), (SETHIi tblockaddress:$in)>;
1035 def : Pat<(SPlo tblockaddress:$in), (ORri (i32 G0), tblockaddress:$in)>;
1037 // Add reg, lo. This is used when taking the addr of a global/constpool entry.
1038 def : Pat<(add iPTR:$r, (SPlo tglobaladdr:$in)), (ADDri $r, tglobaladdr:$in)>;
1039 def : Pat<(add iPTR:$r, (SPlo tconstpool:$in)), (ADDri $r, tconstpool:$in)>;
1040 def : Pat<(add iPTR:$r, (SPlo tblockaddress:$in)),
1041 (ADDri $r, tblockaddress:$in)>;
1045 def : Pat<(call tglobaladdr:$dst),
1046 (CALL tglobaladdr:$dst)>;
1047 def : Pat<(call texternalsym:$dst),
1048 (CALL texternalsym:$dst)>;
1050 // Map integer extload's to zextloads.
1051 def : Pat<(i32 (extloadi1 ADDRrr:$src)), (LDUBrr ADDRrr:$src)>;
1052 def : Pat<(i32 (extloadi1 ADDRri:$src)), (LDUBri ADDRri:$src)>;
1053 def : Pat<(i32 (extloadi8 ADDRrr:$src)), (LDUBrr ADDRrr:$src)>;
1054 def : Pat<(i32 (extloadi8 ADDRri:$src)), (LDUBri ADDRri:$src)>;
1055 def : Pat<(i32 (extloadi16 ADDRrr:$src)), (LDUHrr ADDRrr:$src)>;
1056 def : Pat<(i32 (extloadi16 ADDRri:$src)), (LDUHri ADDRri:$src)>;
1058 // zextload bool -> zextload byte
1059 def : Pat<(i32 (zextloadi1 ADDRrr:$src)), (LDUBrr ADDRrr:$src)>;
1060 def : Pat<(i32 (zextloadi1 ADDRri:$src)), (LDUBri ADDRri:$src)>;
1062 // store 0, addr -> store %g0, addr
1063 def : Pat<(store (i32 0), ADDRrr:$dst), (STrr ADDRrr:$dst, (i32 G0))>;
1064 def : Pat<(store (i32 0), ADDRri:$dst), (STri ADDRri:$dst, (i32 G0))>;
1066 // store bar for all atomic_fence in V8.
1067 let Predicates = [HasNoV9] in
1068 def : Pat<(atomic_fence imm, imm), (STBAR)>;
1070 // atomic_load_32 addr -> load addr
1071 def : Pat<(i32 (atomic_load ADDRrr:$src)), (LDrr ADDRrr:$src)>;
1072 def : Pat<(i32 (atomic_load ADDRri:$src)), (LDri ADDRri:$src)>;
1074 // atomic_store_32 val, addr -> store val, addr
1075 def : Pat<(atomic_store ADDRrr:$dst, i32:$val), (STrr ADDRrr:$dst, $val)>;
1076 def : Pat<(atomic_store ADDRri:$dst, i32:$val), (STri ADDRri:$dst, $val)>;
1079 include "SparcInstr64Bit.td"