1 //===-- SparcInstrInfo.td - Target Description for Sparc Target -----------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the Sparc instructions in TableGen format.
12 //===----------------------------------------------------------------------===//
14 //===----------------------------------------------------------------------===//
15 // Instruction format superclass
16 //===----------------------------------------------------------------------===//
18 include "SparcInstrFormats.td"
20 //===----------------------------------------------------------------------===//
21 // Feature predicates.
22 //===----------------------------------------------------------------------===//
24 // True when generating 32-bit code.
25 def Is32Bit : Predicate<"!Subtarget.is64Bit()">;
27 // True when generating 64-bit code. This also implies HasV9.
28 def Is64Bit : Predicate<"Subtarget.is64Bit()">;
30 // HasV9 - This predicate is true when the target processor supports V9
31 // instructions. Note that the machine may be running in 32-bit mode.
32 def HasV9 : Predicate<"Subtarget.isV9()">;
34 // HasNoV9 - This predicate is true when the target doesn't have V9
35 // instructions. Use of this is just a hack for the isel not having proper
36 // costs for V8 instructions that are more expensive than their V9 ones.
37 def HasNoV9 : Predicate<"!Subtarget.isV9()">;
39 // HasVIS - This is true when the target processor has VIS extensions.
40 def HasVIS : Predicate<"Subtarget.isVIS()">;
42 // HasHardQuad - This is true when the target processor supports quad floating
43 // point instructions.
44 def HasHardQuad : Predicate<"Subtarget.hasHardQuad()">;
46 // UseDeprecatedInsts - This predicate is true when the target processor is a
47 // V8, or when it is V9 but the V8 deprecated instructions are efficient enough
48 // to use when appropriate. In either of these cases, the instruction selector
49 // will pick deprecated instructions.
50 def UseDeprecatedInsts : Predicate<"Subtarget.useDeprecatedV8Instructions()">;
52 //===----------------------------------------------------------------------===//
53 // Instruction Pattern Stuff
54 //===----------------------------------------------------------------------===//
56 def simm11 : PatLeaf<(imm), [{ return isInt<11>(N->getSExtValue()); }]>;
58 def simm13 : PatLeaf<(imm), [{ return isInt<13>(N->getSExtValue()); }]>;
60 def LO10 : SDNodeXForm<imm, [{
61 return CurDAG->getTargetConstant((unsigned)N->getZExtValue() & 1023,
65 def HI22 : SDNodeXForm<imm, [{
66 // Transformation function: shift the immediate value down into the low bits.
67 return CurDAG->getTargetConstant((unsigned)N->getZExtValue() >> 10, MVT::i32);
70 def SETHIimm : PatLeaf<(imm), [{
71 return isShiftedUInt<22, 10>(N->getZExtValue());
75 def ADDRrr : ComplexPattern<iPTR, 2, "SelectADDRrr", [], []>;
76 def ADDRri : ComplexPattern<iPTR, 2, "SelectADDRri", [frameindex], []>;
79 def SparcMEMrrAsmOperand : AsmOperandClass {
81 let ParserMethod = "parseMEMOperand";
84 def SparcMEMriAsmOperand : AsmOperandClass {
86 let ParserMethod = "parseMEMOperand";
89 def MEMrr : Operand<iPTR> {
90 let PrintMethod = "printMemOperand";
91 let MIOperandInfo = (ops ptr_rc, ptr_rc);
92 let ParserMatchClass = SparcMEMrrAsmOperand;
94 def MEMri : Operand<iPTR> {
95 let PrintMethod = "printMemOperand";
96 let MIOperandInfo = (ops ptr_rc, i32imm);
97 let ParserMatchClass = SparcMEMriAsmOperand;
100 def TLSSym : Operand<iPTR>;
102 // Branch targets have OtherVT type.
103 def brtarget : Operand<OtherVT> {
104 let EncoderMethod = "getBranchTargetOpValue";
107 def calltarget : Operand<i32> {
108 let EncoderMethod = "getCallTargetOpValue";
111 // Operand for printing out a condition code.
112 let PrintMethod = "printCCOperand" in
113 def CCOp : Operand<i32>;
116 SDTypeProfile<0, 2, [SDTCisInt<0>, SDTCisSameAs<0, 1>]>;
118 SDTypeProfile<0, 2, [SDTCisFP<0>, SDTCisSameAs<0, 1>]>;
120 SDTypeProfile<0, 2, [SDTCisVT<0, OtherVT>, SDTCisVT<1, i32>]>;
122 SDTypeProfile<1, 3, [SDTCisSameAs<0, 1>, SDTCisSameAs<1, 2>, SDTCisVT<3, i32>]>;
124 SDTypeProfile<1, 1, [SDTCisVT<0, f32>, SDTCisFP<1>]>;
126 SDTypeProfile<1, 1, [SDTCisFP<0>, SDTCisVT<1, f32>]>;
128 SDTypeProfile<1, 1, [SDTCisVT<0, f64>, SDTCisFP<1>]>;
130 SDTypeProfile<1, 1, [SDTCisFP<0>, SDTCisVT<1, f64>]>;
133 SDTypeProfile<1, 3, [SDTCisInt<0>, SDTCisSameAs<0, 1>, SDTCisPtrTy<2>]>;
135 SDTypeProfile<1, 2, [SDTCisPtrTy<0>, SDTCisPtrTy<1>]>;
137 def SPcmpicc : SDNode<"SPISD::CMPICC", SDTSPcmpicc, [SDNPOutGlue]>;
138 def SPcmpfcc : SDNode<"SPISD::CMPFCC", SDTSPcmpfcc, [SDNPOutGlue]>;
139 def SPbricc : SDNode<"SPISD::BRICC", SDTSPbrcc, [SDNPHasChain, SDNPInGlue]>;
140 def SPbrxcc : SDNode<"SPISD::BRXCC", SDTSPbrcc, [SDNPHasChain, SDNPInGlue]>;
141 def SPbrfcc : SDNode<"SPISD::BRFCC", SDTSPbrcc, [SDNPHasChain, SDNPInGlue]>;
143 def SPhi : SDNode<"SPISD::Hi", SDTIntUnaryOp>;
144 def SPlo : SDNode<"SPISD::Lo", SDTIntUnaryOp>;
146 def SPftoi : SDNode<"SPISD::FTOI", SDTSPFTOI>;
147 def SPitof : SDNode<"SPISD::ITOF", SDTSPITOF>;
148 def SPftox : SDNode<"SPISD::FTOX", SDTSPFTOX>;
149 def SPxtof : SDNode<"SPISD::XTOF", SDTSPXTOF>;
151 def SPselecticc : SDNode<"SPISD::SELECT_ICC", SDTSPselectcc, [SDNPInGlue]>;
152 def SPselectxcc : SDNode<"SPISD::SELECT_XCC", SDTSPselectcc, [SDNPInGlue]>;
153 def SPselectfcc : SDNode<"SPISD::SELECT_FCC", SDTSPselectcc, [SDNPInGlue]>;
155 // These are target-independent nodes, but have target-specific formats.
156 def SDT_SPCallSeqStart : SDCallSeqStart<[ SDTCisVT<0, i32> ]>;
157 def SDT_SPCallSeqEnd : SDCallSeqEnd<[ SDTCisVT<0, i32>,
160 def callseq_start : SDNode<"ISD::CALLSEQ_START", SDT_SPCallSeqStart,
161 [SDNPHasChain, SDNPOutGlue]>;
162 def callseq_end : SDNode<"ISD::CALLSEQ_END", SDT_SPCallSeqEnd,
163 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]>;
165 def SDT_SPCall : SDTypeProfile<0, -1, [SDTCisVT<0, i32>]>;
166 def call : SDNode<"SPISD::CALL", SDT_SPCall,
167 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue,
170 def SDT_SPRet : SDTypeProfile<0, 1, [SDTCisVT<0, i32>]>;
171 def retflag : SDNode<"SPISD::RET_FLAG", SDT_SPRet,
172 [SDNPHasChain, SDNPOptInGlue, SDNPVariadic]>;
174 def flushw : SDNode<"SPISD::FLUSHW", SDTNone,
175 [SDNPHasChain, SDNPSideEffect, SDNPMayStore]>;
177 def tlsadd : SDNode<"SPISD::TLS_ADD", SDTSPtlsadd>;
178 def tlsld : SDNode<"SPISD::TLS_LD", SDTSPtlsld>;
179 def tlscall : SDNode<"SPISD::TLS_CALL", SDT_SPCall,
180 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue,
183 def getPCX : Operand<i32> {
184 let PrintMethod = "printGetPCX";
187 //===----------------------------------------------------------------------===//
188 // SPARC Flag Conditions
189 //===----------------------------------------------------------------------===//
191 // Note that these values must be kept in sync with the CCOp::CondCode enum
193 class ICC_VAL<int N> : PatLeaf<(i32 N)>;
194 def ICC_NE : ICC_VAL< 9>; // Not Equal
195 def ICC_E : ICC_VAL< 1>; // Equal
196 def ICC_G : ICC_VAL<10>; // Greater
197 def ICC_LE : ICC_VAL< 2>; // Less or Equal
198 def ICC_GE : ICC_VAL<11>; // Greater or Equal
199 def ICC_L : ICC_VAL< 3>; // Less
200 def ICC_GU : ICC_VAL<12>; // Greater Unsigned
201 def ICC_LEU : ICC_VAL< 4>; // Less or Equal Unsigned
202 def ICC_CC : ICC_VAL<13>; // Carry Clear/Great or Equal Unsigned
203 def ICC_CS : ICC_VAL< 5>; // Carry Set/Less Unsigned
204 def ICC_POS : ICC_VAL<14>; // Positive
205 def ICC_NEG : ICC_VAL< 6>; // Negative
206 def ICC_VC : ICC_VAL<15>; // Overflow Clear
207 def ICC_VS : ICC_VAL< 7>; // Overflow Set
209 class FCC_VAL<int N> : PatLeaf<(i32 N)>;
210 def FCC_U : FCC_VAL<23>; // Unordered
211 def FCC_G : FCC_VAL<22>; // Greater
212 def FCC_UG : FCC_VAL<21>; // Unordered or Greater
213 def FCC_L : FCC_VAL<20>; // Less
214 def FCC_UL : FCC_VAL<19>; // Unordered or Less
215 def FCC_LG : FCC_VAL<18>; // Less or Greater
216 def FCC_NE : FCC_VAL<17>; // Not Equal
217 def FCC_E : FCC_VAL<25>; // Equal
218 def FCC_UE : FCC_VAL<24>; // Unordered or Equal
219 def FCC_GE : FCC_VAL<25>; // Greater or Equal
220 def FCC_UGE : FCC_VAL<26>; // Unordered or Greater or Equal
221 def FCC_LE : FCC_VAL<27>; // Less or Equal
222 def FCC_ULE : FCC_VAL<28>; // Unordered or Less or Equal
223 def FCC_O : FCC_VAL<29>; // Ordered
225 //===----------------------------------------------------------------------===//
226 // Instruction Class Templates
227 //===----------------------------------------------------------------------===//
229 /// F3_12 multiclass - Define a normal F3_1/F3_2 pattern in one shot.
230 multiclass F3_12<string OpcStr, bits<6> Op3Val, SDNode OpNode,
231 RegisterClass RC, ValueType Ty, Operand immOp> {
232 def rr : F3_1<2, Op3Val,
233 (outs RC:$rd), (ins RC:$rs1, RC:$rs2),
234 !strconcat(OpcStr, " $rs1, $rs2, $rd"),
235 [(set Ty:$rd, (OpNode Ty:$rs1, Ty:$rs2))]>;
236 def ri : F3_2<2, Op3Val,
237 (outs RC:$rd), (ins RC:$rs1, immOp:$simm13),
238 !strconcat(OpcStr, " $rs1, $simm13, $rd"),
239 [(set Ty:$rd, (OpNode Ty:$rs1, (Ty simm13:$simm13)))]>;
242 /// F3_12np multiclass - Define a normal F3_1/F3_2 pattern in one shot, with no
244 multiclass F3_12np<string OpcStr, bits<6> Op3Val> {
245 def rr : F3_1<2, Op3Val,
246 (outs IntRegs:$rd), (ins IntRegs:$rs1, IntRegs:$rs2),
247 !strconcat(OpcStr, " $rs1, $rs2, $rd"), []>;
248 def ri : F3_2<2, Op3Val,
249 (outs IntRegs:$rd), (ins IntRegs:$rs1, i32imm:$simm13),
250 !strconcat(OpcStr, " $rs1, $simm13, $rd"), []>;
253 // Load multiclass - Define both Reg+Reg/Reg+Imm patterns in one shot.
254 multiclass Load<string OpcStr, bits<6> Op3Val, SDPatternOperator OpNode,
255 RegisterClass RC, ValueType Ty> {
256 def rr : F3_1<3, Op3Val,
257 (outs RC:$dst), (ins MEMrr:$addr),
258 !strconcat(OpcStr, " [$addr], $dst"),
259 [(set Ty:$dst, (OpNode ADDRrr:$addr))]>;
260 def ri : F3_2<3, Op3Val,
261 (outs RC:$dst), (ins MEMri:$addr),
262 !strconcat(OpcStr, " [$addr], $dst"),
263 [(set Ty:$dst, (OpNode ADDRri:$addr))]>;
266 // Store multiclass - Define both Reg+Reg/Reg+Imm patterns in one shot.
267 multiclass Store<string OpcStr, bits<6> Op3Val, SDPatternOperator OpNode,
268 RegisterClass RC, ValueType Ty> {
269 def rr : F3_1<3, Op3Val,
270 (outs), (ins MEMrr:$addr, RC:$rd),
271 !strconcat(OpcStr, " $rd, [$addr]"),
272 [(OpNode Ty:$rd, ADDRrr:$addr)]>;
273 def ri : F3_2<3, Op3Val,
274 (outs), (ins MEMri:$addr, RC:$rd),
275 !strconcat(OpcStr, " $rd, [$addr]"),
276 [(OpNode Ty:$rd, ADDRri:$addr)]>;
279 //===----------------------------------------------------------------------===//
281 //===----------------------------------------------------------------------===//
283 // Pseudo instructions.
284 class Pseudo<dag outs, dag ins, string asmstr, list<dag> pattern>
285 : InstSP<outs, ins, asmstr, pattern> {
286 let isCodeGenOnly = 1;
292 def GETPCX : Pseudo<(outs getPCX:$getpcseq), (ins), "$getpcseq", [] >;
295 let Defs = [O6], Uses = [O6] in {
296 def ADJCALLSTACKDOWN : Pseudo<(outs), (ins i32imm:$amt),
297 "!ADJCALLSTACKDOWN $amt",
298 [(callseq_start timm:$amt)]>;
299 def ADJCALLSTACKUP : Pseudo<(outs), (ins i32imm:$amt1, i32imm:$amt2),
300 "!ADJCALLSTACKUP $amt1",
301 [(callseq_end timm:$amt1, timm:$amt2)]>;
304 let hasSideEffects = 1, mayStore = 1 in {
305 let rd = 0, rs1 = 0, rs2 = 0 in
306 def FLUSHW : F3_1<0b10, 0b101011, (outs), (ins),
308 [(flushw)]>, Requires<[HasV9]>;
309 let rd = 0, rs1 = 1, simm13 = 3 in
310 def TA3 : F3_2<0b10, 0b111010, (outs), (ins),
316 def UNIMP : F2_1<0b000, (outs), (ins i32imm:$val),
319 // SELECT_CC_* - Used to implement the SELECT_CC DAG operation. Expanded after
320 // instruction selection into a branch sequence. This has to handle all
321 // permutations of selection between i32/f32/f64 on ICC and FCC.
322 // Expanded after instruction selection.
323 let Uses = [ICC], usesCustomInserter = 1 in {
324 def SELECT_CC_Int_ICC
325 : Pseudo<(outs IntRegs:$dst), (ins IntRegs:$T, IntRegs:$F, i32imm:$Cond),
326 "; SELECT_CC_Int_ICC PSEUDO!",
327 [(set i32:$dst, (SPselecticc i32:$T, i32:$F, imm:$Cond))]>;
329 : Pseudo<(outs FPRegs:$dst), (ins FPRegs:$T, FPRegs:$F, i32imm:$Cond),
330 "; SELECT_CC_FP_ICC PSEUDO!",
331 [(set f32:$dst, (SPselecticc f32:$T, f32:$F, imm:$Cond))]>;
333 def SELECT_CC_DFP_ICC
334 : Pseudo<(outs DFPRegs:$dst), (ins DFPRegs:$T, DFPRegs:$F, i32imm:$Cond),
335 "; SELECT_CC_DFP_ICC PSEUDO!",
336 [(set f64:$dst, (SPselecticc f64:$T, f64:$F, imm:$Cond))]>;
338 def SELECT_CC_QFP_ICC
339 : Pseudo<(outs QFPRegs:$dst), (ins QFPRegs:$T, QFPRegs:$F, i32imm:$Cond),
340 "; SELECT_CC_QFP_ICC PSEUDO!",
341 [(set f128:$dst, (SPselecticc f128:$T, f128:$F, imm:$Cond))]>;
344 let usesCustomInserter = 1, Uses = [FCC] in {
346 def SELECT_CC_Int_FCC
347 : Pseudo<(outs IntRegs:$dst), (ins IntRegs:$T, IntRegs:$F, i32imm:$Cond),
348 "; SELECT_CC_Int_FCC PSEUDO!",
349 [(set i32:$dst, (SPselectfcc i32:$T, i32:$F, imm:$Cond))]>;
352 : Pseudo<(outs FPRegs:$dst), (ins FPRegs:$T, FPRegs:$F, i32imm:$Cond),
353 "; SELECT_CC_FP_FCC PSEUDO!",
354 [(set f32:$dst, (SPselectfcc f32:$T, f32:$F, imm:$Cond))]>;
355 def SELECT_CC_DFP_FCC
356 : Pseudo<(outs DFPRegs:$dst), (ins DFPRegs:$T, DFPRegs:$F, i32imm:$Cond),
357 "; SELECT_CC_DFP_FCC PSEUDO!",
358 [(set f64:$dst, (SPselectfcc f64:$T, f64:$F, imm:$Cond))]>;
359 def SELECT_CC_QFP_FCC
360 : Pseudo<(outs QFPRegs:$dst), (ins QFPRegs:$T, QFPRegs:$F, i32imm:$Cond),
361 "; SELECT_CC_QFP_FCC PSEUDO!",
362 [(set f128:$dst, (SPselectfcc f128:$T, f128:$F, imm:$Cond))]>;
366 let isTerminator = 1, hasDelaySlot = 1, isBarrier = 1 in {
367 def JMPLrr: F3_1<2, 0b111000, (outs IntRegs:$dst), (ins MEMrr:$addr),
368 "jmpl $addr, $dst", []>;
369 def JMPLri: F3_2<2, 0b111000, (outs IntRegs:$dst), (ins MEMri:$addr),
370 "jmpl $addr, $dst", []>;
373 // Section A.3 - Synthetic Instructions, p. 85
374 // special cases of JMPL:
375 let isReturn = 1, isTerminator = 1, hasDelaySlot = 1, isBarrier = 1,
376 isCodeGenOnly = 1 in {
377 let rd = 0, rs1 = 15 in
378 def RETL: F3_2<2, 0b111000, (outs), (ins i32imm:$val),
379 "jmp %o7+$val", [(retflag simm13:$val)]>;
381 let rd = 0, rs1 = 31 in
382 def RET: F3_2<2, 0b111000, (outs), (ins i32imm:$val),
386 // Section B.1 - Load Integer Instructions, p. 90
387 defm LDSB : Load<"ldsb", 0b001001, sextloadi8, IntRegs, i32>;
388 defm LDSH : Load<"ldsh", 0b001010, sextloadi16, IntRegs, i32>;
389 defm LDUB : Load<"ldub", 0b000001, zextloadi8, IntRegs, i32>;
390 defm LDUH : Load<"lduh", 0b000010, zextloadi16, IntRegs, i32>;
391 defm LD : Load<"ld", 0b000000, load, IntRegs, i32>;
393 // Section B.2 - Load Floating-point Instructions, p. 92
394 defm LDF : Load<"ld", 0b100000, load, FPRegs, f32>;
395 defm LDDF : Load<"ldd", 0b100011, load, DFPRegs, f64>;
396 defm LDQF : Load<"ldq", 0b100010, load, QFPRegs, f128>,
397 Requires<[HasV9, HasHardQuad]>;
399 // Section B.4 - Store Integer Instructions, p. 95
400 defm STB : Store<"stb", 0b000101, truncstorei8, IntRegs, i32>;
401 defm STH : Store<"sth", 0b000110, truncstorei16, IntRegs, i32>;
402 defm ST : Store<"st", 0b000100, store, IntRegs, i32>;
404 // Section B.5 - Store Floating-point Instructions, p. 97
405 defm STF : Store<"st", 0b100100, store, FPRegs, f32>;
406 defm STDF : Store<"std", 0b100111, store, DFPRegs, f64>;
407 defm STQF : Store<"stq", 0b100110, store, QFPRegs, f128>,
408 Requires<[HasV9, HasHardQuad]>;
410 // Section B.9 - SETHI Instruction, p. 104
411 def SETHIi: F2_1<0b100,
412 (outs IntRegs:$rd), (ins i32imm:$imm22),
414 [(set i32:$rd, SETHIimm:$imm22)]>;
416 // Section B.10 - NOP Instruction, p. 105
417 // (It's a special case of SETHI)
418 let rd = 0, imm22 = 0 in
419 def NOP : F2_1<0b100, (outs), (ins), "nop", []>;
421 // Section B.11 - Logical Instructions, p. 106
422 defm AND : F3_12<"and", 0b000001, and, IntRegs, i32, i32imm>;
424 def ANDNrr : F3_1<2, 0b000101,
425 (outs IntRegs:$rd), (ins IntRegs:$rs1, IntRegs:$rs2),
426 "andn $rs1, $rs2, $rd",
427 [(set i32:$rd, (and i32:$rs1, (not i32:$rs2)))]>;
428 def ANDNri : F3_2<2, 0b000101,
429 (outs IntRegs:$rd), (ins IntRegs:$rs1, i32imm:$simm13),
430 "andn $rs1, $simm13, $rd", []>;
432 defm OR : F3_12<"or", 0b000010, or, IntRegs, i32, i32imm>;
434 def ORNrr : F3_1<2, 0b000110,
435 (outs IntRegs:$rd), (ins IntRegs:$rs1, IntRegs:$rs2),
436 "orn $rs1, $rs2, $rd",
437 [(set i32:$rd, (or i32:$rs1, (not i32:$rs2)))]>;
438 def ORNri : F3_2<2, 0b000110,
439 (outs IntRegs:$rd), (ins IntRegs:$rs1, i32imm:$simm13),
440 "orn $rs1, $simm13, $rd", []>;
441 defm XOR : F3_12<"xor", 0b000011, xor, IntRegs, i32, i32imm>;
443 def XNORrr : F3_1<2, 0b000111,
444 (outs IntRegs:$rd), (ins IntRegs:$rs1, IntRegs:$rs2),
445 "xnor $rs1, $rs2, $rd",
446 [(set i32:$rd, (not (xor i32:$rs1, i32:$rs2)))]>;
447 def XNORri : F3_2<2, 0b000111,
448 (outs IntRegs:$rd), (ins IntRegs:$rs1, i32imm:$simm13),
449 "xnor $rs1, $simm13, $rd", []>;
451 // Section B.12 - Shift Instructions, p. 107
452 defm SLL : F3_12<"sll", 0b100101, shl, IntRegs, i32, i32imm>;
453 defm SRL : F3_12<"srl", 0b100110, srl, IntRegs, i32, i32imm>;
454 defm SRA : F3_12<"sra", 0b100111, sra, IntRegs, i32, i32imm>;
456 // Section B.13 - Add Instructions, p. 108
457 defm ADD : F3_12<"add", 0b000000, add, IntRegs, i32, i32imm>;
459 // "LEA" forms of add (patterns to make tblgen happy)
460 let Predicates = [Is32Bit], isCodeGenOnly = 1 in
461 def LEA_ADDri : F3_2<2, 0b000000,
462 (outs IntRegs:$dst), (ins MEMri:$addr),
463 "add ${addr:arith}, $dst",
464 [(set iPTR:$dst, ADDRri:$addr)]>;
467 defm ADDCC : F3_12<"addcc", 0b010000, addc, IntRegs, i32, i32imm>;
469 let Uses = [ICC], Defs = [ICC] in
470 defm ADDE : F3_12<"addxcc", 0b011000, adde, IntRegs, i32, i32imm>;
472 // Section B.15 - Subtract Instructions, p. 110
473 defm SUB : F3_12 <"sub" , 0b000100, sub, IntRegs, i32, i32imm>;
474 let Uses = [ICC], Defs = [ICC] in
475 defm SUBE : F3_12 <"subxcc" , 0b011100, sube, IntRegs, i32, i32imm>;
478 defm SUBCC : F3_12 <"subcc", 0b010100, subc, IntRegs, i32, i32imm>;
480 let Defs = [ICC], rd = 0 in {
481 def CMPrr : F3_1<2, 0b010100,
482 (outs), (ins IntRegs:$rs1, IntRegs:$rs2),
484 [(SPcmpicc i32:$rs1, i32:$rs2)]>;
485 def CMPri : F3_2<2, 0b010100,
486 (outs), (ins IntRegs:$rs1, i32imm:$simm13),
488 [(SPcmpicc i32:$rs1, (i32 simm13:$simm13))]>;
491 // Section B.18 - Multiply Instructions, p. 113
493 defm UMUL : F3_12np<"umul", 0b001010>;
494 defm SMUL : F3_12 <"smul", 0b001011, mul, IntRegs, i32, i32imm>;
497 // Section B.19 - Divide Instructions, p. 115
499 defm UDIV : F3_12np<"udiv", 0b001110>;
500 defm SDIV : F3_12np<"sdiv", 0b001111>;
503 // Section B.20 - SAVE and RESTORE, p. 117
504 defm SAVE : F3_12np<"save" , 0b111100>;
505 defm RESTORE : F3_12np<"restore", 0b111101>;
507 // Section B.21 - Branch on Integer Condition Codes Instructions, p. 119
509 // unconditional branch class.
510 class BranchAlways<dag ins, string asmstr, list<dag> pattern>
511 : F2_2<0b010, (outs), ins, asmstr, pattern> {
513 let isTerminator = 1;
514 let hasDelaySlot = 1;
519 def BA : BranchAlways<(ins brtarget:$imm22), "ba $imm22", [(br bb:$imm22)]>;
521 // conditional branch class:
522 class BranchSP<dag ins, string asmstr, list<dag> pattern>
523 : F2_2<0b010, (outs), ins, asmstr, pattern> {
525 let isTerminator = 1;
526 let hasDelaySlot = 1;
529 // Indirect branch instructions.
530 let isTerminator = 1, isBarrier = 1, hasDelaySlot = 1, isBranch =1,
531 isIndirectBranch = 1, rd = 0, isCodeGenOnly = 1 in {
532 def BINDrr : F3_1<2, 0b111000,
533 (outs), (ins MEMrr:$ptr),
535 [(brind ADDRrr:$ptr)]>;
536 def BINDri : F3_2<2, 0b111000,
537 (outs), (ins MEMri:$ptr),
539 [(brind ADDRri:$ptr)]>;
543 def BCOND : BranchSP<(ins brtarget:$imm22, CCOp:$cond),
545 [(SPbricc bb:$imm22, imm:$cond)]>;
547 // Section B.22 - Branch on Floating-point Condition Codes Instructions, p. 121
549 // floating-point conditional branch class:
550 class FPBranchSP<dag ins, string asmstr, list<dag> pattern>
551 : F2_2<0b110, (outs), ins, asmstr, pattern> {
553 let isTerminator = 1;
554 let hasDelaySlot = 1;
558 def FBCOND : FPBranchSP<(ins brtarget:$imm22, CCOp:$cond),
560 [(SPbrfcc bb:$imm22, imm:$cond)]>;
563 // Section B.24 - Call and Link Instruction, p. 125
564 // This is the only Format 1 instruction
566 hasDelaySlot = 1, isCall = 1 in {
567 def CALL : InstSP<(outs), (ins calltarget:$dst, variable_ops),
571 let Inst{29-0} = disp;
574 // indirect calls: special cases of JMPL.
575 let isCodeGenOnly = 1, rd = 15 in {
576 def CALLrr : F3_1<2, 0b111000,
577 (outs), (ins MEMrr:$ptr, variable_ops),
579 [(call ADDRrr:$ptr)]>;
580 def CALLri : F3_2<2, 0b111000,
581 (outs), (ins MEMri:$ptr, variable_ops),
583 [(call ADDRri:$ptr)]>;
587 // Section B.28 - Read State Register Instructions
588 let Uses = [Y], rs1 = 0, rs2 = 0 in
589 def RDY : F3_1<2, 0b101000,
590 (outs IntRegs:$dst), (ins),
593 // Section B.29 - Write State Register Instructions
594 let Defs = [Y], rd = 0 in {
595 def WRYrr : F3_1<2, 0b110000,
596 (outs), (ins IntRegs:$b, IntRegs:$c),
597 "wr $b, $c, %y", []>;
598 def WRYri : F3_2<2, 0b110000,
599 (outs), (ins IntRegs:$b, i32imm:$c),
600 "wr $b, $c, %y", []>;
602 // Convert Integer to Floating-point Instructions, p. 141
603 def FITOS : F3_3u<2, 0b110100, 0b011000100,
604 (outs FPRegs:$dst), (ins FPRegs:$src),
606 [(set FPRegs:$dst, (SPitof FPRegs:$src))]>;
607 def FITOD : F3_3u<2, 0b110100, 0b011001000,
608 (outs DFPRegs:$dst), (ins FPRegs:$src),
610 [(set DFPRegs:$dst, (SPitof FPRegs:$src))]>;
611 def FITOQ : F3_3u<2, 0b110100, 0b011001100,
612 (outs QFPRegs:$dst), (ins FPRegs:$src),
614 [(set QFPRegs:$dst, (SPitof FPRegs:$src))]>,
615 Requires<[HasHardQuad]>;
617 // Convert Floating-point to Integer Instructions, p. 142
618 def FSTOI : F3_3u<2, 0b110100, 0b011010001,
619 (outs FPRegs:$dst), (ins FPRegs:$src),
621 [(set FPRegs:$dst, (SPftoi FPRegs:$src))]>;
622 def FDTOI : F3_3u<2, 0b110100, 0b011010010,
623 (outs FPRegs:$dst), (ins DFPRegs:$src),
625 [(set FPRegs:$dst, (SPftoi DFPRegs:$src))]>;
626 def FQTOI : F3_3u<2, 0b110100, 0b011010011,
627 (outs FPRegs:$dst), (ins QFPRegs:$src),
629 [(set FPRegs:$dst, (SPftoi QFPRegs:$src))]>,
630 Requires<[HasHardQuad]>;
632 // Convert between Floating-point Formats Instructions, p. 143
633 def FSTOD : F3_3u<2, 0b110100, 0b011001001,
634 (outs DFPRegs:$dst), (ins FPRegs:$src),
636 [(set f64:$dst, (fextend f32:$src))]>;
637 def FSTOQ : F3_3u<2, 0b110100, 0b011001101,
638 (outs QFPRegs:$dst), (ins FPRegs:$src),
640 [(set f128:$dst, (fextend f32:$src))]>,
641 Requires<[HasHardQuad]>;
642 def FDTOS : F3_3u<2, 0b110100, 0b011000110,
643 (outs FPRegs:$dst), (ins DFPRegs:$src),
645 [(set f32:$dst, (fround f64:$src))]>;
646 def FDTOQ : F3_3u<2, 0b110100, 0b01101110,
647 (outs QFPRegs:$dst), (ins DFPRegs:$src),
649 [(set f128:$dst, (fextend f64:$src))]>,
650 Requires<[HasHardQuad]>;
651 def FQTOS : F3_3u<2, 0b110100, 0b011000111,
652 (outs FPRegs:$dst), (ins QFPRegs:$src),
654 [(set f32:$dst, (fround f128:$src))]>,
655 Requires<[HasHardQuad]>;
656 def FQTOD : F3_3u<2, 0b110100, 0b011001011,
657 (outs DFPRegs:$dst), (ins QFPRegs:$src),
659 [(set f64:$dst, (fround f128:$src))]>,
660 Requires<[HasHardQuad]>;
662 // Floating-point Move Instructions, p. 144
663 def FMOVS : F3_3u<2, 0b110100, 0b000000001,
664 (outs FPRegs:$dst), (ins FPRegs:$src),
665 "fmovs $src, $dst", []>;
666 def FNEGS : F3_3u<2, 0b110100, 0b000000101,
667 (outs FPRegs:$dst), (ins FPRegs:$src),
669 [(set f32:$dst, (fneg f32:$src))]>;
670 def FABSS : F3_3u<2, 0b110100, 0b000001001,
671 (outs FPRegs:$dst), (ins FPRegs:$src),
673 [(set f32:$dst, (fabs f32:$src))]>;
676 // Floating-point Square Root Instructions, p.145
677 def FSQRTS : F3_3u<2, 0b110100, 0b000101001,
678 (outs FPRegs:$dst), (ins FPRegs:$src),
680 [(set f32:$dst, (fsqrt f32:$src))]>;
681 def FSQRTD : F3_3u<2, 0b110100, 0b000101010,
682 (outs DFPRegs:$dst), (ins DFPRegs:$src),
684 [(set f64:$dst, (fsqrt f64:$src))]>;
685 def FSQRTQ : F3_3u<2, 0b110100, 0b000101011,
686 (outs QFPRegs:$dst), (ins QFPRegs:$src),
688 [(set f128:$dst, (fsqrt f128:$src))]>,
689 Requires<[HasHardQuad]>;
693 // Floating-point Add and Subtract Instructions, p. 146
694 def FADDS : F3_3<2, 0b110100, 0b001000001,
695 (outs FPRegs:$dst), (ins FPRegs:$src1, FPRegs:$src2),
696 "fadds $src1, $src2, $dst",
697 [(set f32:$dst, (fadd f32:$src1, f32:$src2))]>;
698 def FADDD : F3_3<2, 0b110100, 0b001000010,
699 (outs DFPRegs:$dst), (ins DFPRegs:$src1, DFPRegs:$src2),
700 "faddd $src1, $src2, $dst",
701 [(set f64:$dst, (fadd f64:$src1, f64:$src2))]>;
702 def FADDQ : F3_3<2, 0b110100, 0b001000011,
703 (outs QFPRegs:$dst), (ins QFPRegs:$src1, QFPRegs:$src2),
704 "faddq $src1, $src2, $dst",
705 [(set f128:$dst, (fadd f128:$src1, f128:$src2))]>,
706 Requires<[HasHardQuad]>;
708 def FSUBS : F3_3<2, 0b110100, 0b001000101,
709 (outs FPRegs:$dst), (ins FPRegs:$src1, FPRegs:$src2),
710 "fsubs $src1, $src2, $dst",
711 [(set f32:$dst, (fsub f32:$src1, f32:$src2))]>;
712 def FSUBD : F3_3<2, 0b110100, 0b001000110,
713 (outs DFPRegs:$dst), (ins DFPRegs:$src1, DFPRegs:$src2),
714 "fsubd $src1, $src2, $dst",
715 [(set f64:$dst, (fsub f64:$src1, f64:$src2))]>;
716 def FSUBQ : F3_3<2, 0b110100, 0b001000111,
717 (outs QFPRegs:$dst), (ins QFPRegs:$src1, QFPRegs:$src2),
718 "fsubq $src1, $src2, $dst",
719 [(set f128:$dst, (fsub f128:$src1, f128:$src2))]>,
720 Requires<[HasHardQuad]>;
723 // Floating-point Multiply and Divide Instructions, p. 147
724 def FMULS : F3_3<2, 0b110100, 0b001001001,
725 (outs FPRegs:$dst), (ins FPRegs:$src1, FPRegs:$src2),
726 "fmuls $src1, $src2, $dst",
727 [(set f32:$dst, (fmul f32:$src1, f32:$src2))]>;
728 def FMULD : F3_3<2, 0b110100, 0b001001010,
729 (outs DFPRegs:$dst), (ins DFPRegs:$src1, DFPRegs:$src2),
730 "fmuld $src1, $src2, $dst",
731 [(set f64:$dst, (fmul f64:$src1, f64:$src2))]>;
732 def FMULQ : F3_3<2, 0b110100, 0b001001011,
733 (outs QFPRegs:$dst), (ins QFPRegs:$src1, QFPRegs:$src2),
734 "fmulq $src1, $src2, $dst",
735 [(set f128:$dst, (fmul f128:$src1, f128:$src2))]>,
736 Requires<[HasHardQuad]>;
738 def FSMULD : F3_3<2, 0b110100, 0b001101001,
739 (outs DFPRegs:$dst), (ins FPRegs:$src1, FPRegs:$src2),
740 "fsmuld $src1, $src2, $dst",
741 [(set f64:$dst, (fmul (fextend f32:$src1),
742 (fextend f32:$src2)))]>;
743 def FDMULQ : F3_3<2, 0b110100, 0b001101110,
744 (outs QFPRegs:$dst), (ins DFPRegs:$src1, DFPRegs:$src2),
745 "fdmulq $src1, $src2, $dst",
746 [(set f128:$dst, (fmul (fextend f64:$src1),
747 (fextend f64:$src2)))]>,
748 Requires<[HasHardQuad]>;
750 def FDIVS : F3_3<2, 0b110100, 0b001001101,
751 (outs FPRegs:$dst), (ins FPRegs:$src1, FPRegs:$src2),
752 "fdivs $src1, $src2, $dst",
753 [(set f32:$dst, (fdiv f32:$src1, f32:$src2))]>;
754 def FDIVD : F3_3<2, 0b110100, 0b001001110,
755 (outs DFPRegs:$dst), (ins DFPRegs:$src1, DFPRegs:$src2),
756 "fdivd $src1, $src2, $dst",
757 [(set f64:$dst, (fdiv f64:$src1, f64:$src2))]>;
758 def FDIVQ : F3_3<2, 0b110100, 0b001001111,
759 (outs QFPRegs:$dst), (ins QFPRegs:$src1, QFPRegs:$src2),
760 "fdivq $src1, $src2, $dst",
761 [(set f128:$dst, (fdiv f128:$src1, f128:$src2))]>,
762 Requires<[HasHardQuad]>;
764 // Floating-point Compare Instructions, p. 148
765 // Note: the 2nd template arg is different for these guys.
766 // Note 2: the result of a FCMP is not available until the 2nd cycle
767 // after the instr is retired, but there is no interlock in Sparc V8.
768 // This behavior is modeled with a forced noop after the instruction in
771 let Defs = [FCC] in {
772 def FCMPS : F3_3c<2, 0b110101, 0b001010001,
773 (outs), (ins FPRegs:$src1, FPRegs:$src2),
774 "fcmps $src1, $src2",
775 [(SPcmpfcc f32:$src1, f32:$src2)]>;
776 def FCMPD : F3_3c<2, 0b110101, 0b001010010,
777 (outs), (ins DFPRegs:$src1, DFPRegs:$src2),
778 "fcmpd $src1, $src2",
779 [(SPcmpfcc f64:$src1, f64:$src2)]>;
780 def FCMPQ : F3_3c<2, 0b110101, 0b001010011,
781 (outs), (ins QFPRegs:$src1, QFPRegs:$src2),
782 "fcmpq $src1, $src2",
783 [(SPcmpfcc f128:$src1, f128:$src2)]>,
784 Requires<[HasHardQuad]>;
787 //===----------------------------------------------------------------------===//
788 // Instructions for Thread Local Storage(TLS).
789 //===----------------------------------------------------------------------===//
790 let isCodeGenOnly = 1, isAsmParserOnly = 1 in {
791 def TLS_ADDrr : F3_1<2, 0b000000,
793 (ins IntRegs:$rs1, IntRegs:$rs2, TLSSym:$sym),
794 "add $rs1, $rs2, $rd, $sym",
796 (tlsadd i32:$rs1, i32:$rs2, tglobaltlsaddr:$sym))]>;
799 def TLS_LDrr : F3_1<3, 0b000000,
800 (outs IntRegs:$dst), (ins MEMrr:$addr, TLSSym:$sym),
801 "ld [$addr], $dst, $sym",
803 (tlsld ADDRrr:$addr, tglobaltlsaddr:$sym))]>;
805 let Uses = [O6], isCall = 1, hasDelaySlot = 1 in
806 def TLS_CALL : InstSP<(outs),
807 (ins calltarget:$disp, TLSSym:$sym, variable_ops),
809 [(tlscall texternalsym:$disp, tglobaltlsaddr:$sym)]> {
812 let Inst{29-0} = disp;
816 //===----------------------------------------------------------------------===//
818 //===----------------------------------------------------------------------===//
820 // V9 Conditional Moves.
821 let Predicates = [HasV9], Constraints = "$f = $rd" in {
822 // Move Integer Register on Condition (MOVcc) p. 194 of the V9 manual.
823 let Uses = [ICC], cc = 0b100 in {
825 : F4_1<0b101100, (outs IntRegs:$rd),
826 (ins IntRegs:$rs2, IntRegs:$f, CCOp:$cond),
827 "mov$cond %icc, $rs2, $rd",
828 [(set i32:$rd, (SPselecticc i32:$rs2, i32:$f, imm:$cond))]>;
831 : F4_2<0b101100, (outs IntRegs:$rd),
832 (ins i32imm:$simm11, IntRegs:$f, CCOp:$cond),
833 "mov$cond %icc, $simm11, $rd",
835 (SPselecticc simm11:$simm11, i32:$f, imm:$cond))]>;
838 let Uses = [FCC], cc = 0b000 in {
840 : F4_1<0b101100, (outs IntRegs:$rd),
841 (ins IntRegs:$rs2, IntRegs:$f, CCOp:$cond),
842 "mov$cond %fcc0, $rs2, $rd",
843 [(set i32:$rd, (SPselectfcc i32:$rs2, i32:$f, imm:$cond))]>;
845 : F4_2<0b101100, (outs IntRegs:$rd),
846 (ins i32imm:$simm11, IntRegs:$f, CCOp:$cond),
847 "mov$cond %fcc0, $simm11, $rd",
849 (SPselectfcc simm11:$simm11, i32:$f, imm:$cond))]>;
852 let Uses = [ICC], opf_cc = 0b100 in {
854 : F4_3<0b110101, 0b000001, (outs FPRegs:$rd),
855 (ins FPRegs:$rs2, FPRegs:$f, CCOp:$cond),
856 "fmovs$cond %icc, $rs2, $rd",
857 [(set f32:$rd, (SPselecticc f32:$rs2, f32:$f, imm:$cond))]>;
859 : F4_3<0b110101, 0b000010, (outs DFPRegs:$rd),
860 (ins DFPRegs:$rs2, DFPRegs:$f, CCOp:$cond),
861 "fmovd$cond %icc, $rs2, $rd",
862 [(set f64:$rd, (SPselecticc f64:$rs2, f64:$f, imm:$cond))]>;
864 : F4_3<0b110101, 0b000011, (outs QFPRegs:$rd),
865 (ins QFPRegs:$rs2, QFPRegs:$f, CCOp:$cond),
866 "fmovq$cond %icc, $rs2, $rd",
867 [(set f128:$rd, (SPselecticc f128:$rs2, f128:$f, imm:$cond))]>,
868 Requires<[HasHardQuad]>;
871 let Uses = [FCC], opf_cc = 0b000 in {
873 : F4_3<0b110101, 0b000001, (outs FPRegs:$rd),
874 (ins FPRegs:$rs2, FPRegs:$f, CCOp:$cond),
875 "fmovs$cond %fcc0, $rs2, $rd",
876 [(set f32:$rd, (SPselectfcc f32:$rs2, f32:$f, imm:$cond))]>;
878 : F4_3<0b110101, 0b000010, (outs DFPRegs:$rd),
879 (ins DFPRegs:$rs2, DFPRegs:$f, CCOp:$cond),
880 "fmovd$cond %fcc0, $rs2, $rd",
881 [(set f64:$rd, (SPselectfcc f64:$rs2, f64:$f, imm:$cond))]>;
883 : F4_3<0b110101, 0b000011, (outs QFPRegs:$rd),
884 (ins QFPRegs:$rs2, QFPRegs:$f, CCOp:$cond),
885 "fmovq$cond %fcc0, $rs2, $rd",
886 [(set f128:$rd, (SPselectfcc f128:$rs2, f128:$f, imm:$cond))]>,
887 Requires<[HasHardQuad]>;
892 // Floating-Point Move Instructions, p. 164 of the V9 manual.
893 let Predicates = [HasV9] in {
894 def FMOVD : F3_3u<2, 0b110100, 0b000000010,
895 (outs DFPRegs:$dst), (ins DFPRegs:$src),
896 "fmovd $src, $dst", []>;
897 def FMOVQ : F3_3u<2, 0b110100, 0b000000011,
898 (outs QFPRegs:$dst), (ins QFPRegs:$src),
899 "fmovq $src, $dst", []>,
900 Requires<[HasHardQuad]>;
901 def FNEGD : F3_3u<2, 0b110100, 0b000000110,
902 (outs DFPRegs:$dst), (ins DFPRegs:$src),
904 [(set f64:$dst, (fneg f64:$src))]>;
905 def FNEGQ : F3_3u<2, 0b110100, 0b000000111,
906 (outs QFPRegs:$dst), (ins QFPRegs:$src),
908 [(set f128:$dst, (fneg f128:$src))]>,
909 Requires<[HasHardQuad]>;
910 def FABSD : F3_3u<2, 0b110100, 0b000001010,
911 (outs DFPRegs:$dst), (ins DFPRegs:$src),
913 [(set f64:$dst, (fabs f64:$src))]>;
914 def FABSQ : F3_3u<2, 0b110100, 0b000001011,
915 (outs QFPRegs:$dst), (ins QFPRegs:$src),
917 [(set f128:$dst, (fabs f128:$src))]>,
918 Requires<[HasHardQuad]>;
921 // POPCrr - This does a ctpop of a 64-bit register. As such, we have to clear
922 // the top 32-bits before using it. To do this clearing, we use a SRLri X,0.
924 def POPCrr : F3_1<2, 0b101110,
925 (outs IntRegs:$dst), (ins IntRegs:$src),
926 "popc $src, $dst", []>, Requires<[HasV9]>;
927 def : Pat<(ctpop i32:$src),
928 (POPCrr (SRLri $src, 0))>;
931 let hasSideEffects =1, rd = 0, rs1 = 0b01111, rs2 = 0 in
932 def STBAR : F3_1<2, 0b101000, (outs), (ins), "stbar", []>;
934 let Predicates = [HasV9], hasSideEffects = 1, rd = 0, rs1 = 0b01111 in
935 def MEMBARi : F3_2<2, 0b101000, (outs), (ins i32imm:$simm13),
936 "membar $simm13", []>;
938 let Constraints = "$val = $rd" in {
939 def SWAPrr : F3_1<3, 0b001111,
940 (outs IntRegs:$rd), (ins IntRegs:$val, MEMrr:$addr),
942 [(set i32:$rd, (atomic_swap_32 ADDRrr:$addr, i32:$val))]>;
943 def SWAPri : F3_2<3, 0b001111,
944 (outs IntRegs:$rd), (ins IntRegs:$val, MEMri:$addr),
946 [(set i32:$rd, (atomic_swap_32 ADDRri:$addr, i32:$val))]>;
949 let Predicates = [HasV9], Constraints = "$swap = $rd" in
950 def CASrr: F3_1<3, 0b111100,
951 (outs IntRegs:$rd), (ins IntRegs:$rs1, IntRegs:$rs2,
953 "cas [$rs1], $rs2, $rd",
955 (atomic_cmp_swap iPTR:$rs1, i32:$rs2, i32:$swap))]>;
957 //===----------------------------------------------------------------------===//
958 // Non-Instruction Patterns
959 //===----------------------------------------------------------------------===//
962 def : Pat<(i32 simm13:$val),
963 (ORri (i32 G0), imm:$val)>;
964 // Arbitrary immediates.
965 def : Pat<(i32 imm:$val),
966 (ORri (SETHIi (HI22 imm:$val)), (LO10 imm:$val))>;
969 // Global addresses, constant pool entries
970 let Predicates = [Is32Bit] in {
972 def : Pat<(SPhi tglobaladdr:$in), (SETHIi tglobaladdr:$in)>;
973 def : Pat<(SPlo tglobaladdr:$in), (ORri (i32 G0), tglobaladdr:$in)>;
974 def : Pat<(SPhi tconstpool:$in), (SETHIi tconstpool:$in)>;
975 def : Pat<(SPlo tconstpool:$in), (ORri (i32 G0), tconstpool:$in)>;
977 // GlobalTLS addresses
978 def : Pat<(SPhi tglobaltlsaddr:$in), (SETHIi tglobaltlsaddr:$in)>;
979 def : Pat<(SPlo tglobaltlsaddr:$in), (ORri (i32 G0), tglobaltlsaddr:$in)>;
980 def : Pat<(add (SPhi tglobaltlsaddr:$in1), (SPlo tglobaltlsaddr:$in2)),
981 (ADDri (SETHIi tglobaltlsaddr:$in1), (tglobaltlsaddr:$in2))>;
982 def : Pat<(xor (SPhi tglobaltlsaddr:$in1), (SPlo tglobaltlsaddr:$in2)),
983 (XORri (SETHIi tglobaltlsaddr:$in1), (tglobaltlsaddr:$in2))>;
986 def : Pat<(SPhi tblockaddress:$in), (SETHIi tblockaddress:$in)>;
987 def : Pat<(SPlo tblockaddress:$in), (ORri (i32 G0), tblockaddress:$in)>;
989 // Add reg, lo. This is used when taking the addr of a global/constpool entry.
990 def : Pat<(add iPTR:$r, (SPlo tglobaladdr:$in)), (ADDri $r, tglobaladdr:$in)>;
991 def : Pat<(add iPTR:$r, (SPlo tconstpool:$in)), (ADDri $r, tconstpool:$in)>;
992 def : Pat<(add iPTR:$r, (SPlo tblockaddress:$in)),
993 (ADDri $r, tblockaddress:$in)>;
997 def : Pat<(call tglobaladdr:$dst),
998 (CALL tglobaladdr:$dst)>;
999 def : Pat<(call texternalsym:$dst),
1000 (CALL texternalsym:$dst)>;
1002 // Map integer extload's to zextloads.
1003 def : Pat<(i32 (extloadi1 ADDRrr:$src)), (LDUBrr ADDRrr:$src)>;
1004 def : Pat<(i32 (extloadi1 ADDRri:$src)), (LDUBri ADDRri:$src)>;
1005 def : Pat<(i32 (extloadi8 ADDRrr:$src)), (LDUBrr ADDRrr:$src)>;
1006 def : Pat<(i32 (extloadi8 ADDRri:$src)), (LDUBri ADDRri:$src)>;
1007 def : Pat<(i32 (extloadi16 ADDRrr:$src)), (LDUHrr ADDRrr:$src)>;
1008 def : Pat<(i32 (extloadi16 ADDRri:$src)), (LDUHri ADDRri:$src)>;
1010 // zextload bool -> zextload byte
1011 def : Pat<(i32 (zextloadi1 ADDRrr:$src)), (LDUBrr ADDRrr:$src)>;
1012 def : Pat<(i32 (zextloadi1 ADDRri:$src)), (LDUBri ADDRri:$src)>;
1014 // store 0, addr -> store %g0, addr
1015 def : Pat<(store (i32 0), ADDRrr:$dst), (STrr ADDRrr:$dst, (i32 G0))>;
1016 def : Pat<(store (i32 0), ADDRri:$dst), (STri ADDRri:$dst, (i32 G0))>;
1018 // store bar for all atomic_fence in V8.
1019 let Predicates = [HasNoV9] in
1020 def : Pat<(atomic_fence imm, imm), (STBAR)>;
1022 // atomic_load_32 addr -> load addr
1023 def : Pat<(i32 (atomic_load ADDRrr:$src)), (LDrr ADDRrr:$src)>;
1024 def : Pat<(i32 (atomic_load ADDRri:$src)), (LDri ADDRri:$src)>;
1026 // atomic_store_32 val, addr -> store val, addr
1027 def : Pat<(atomic_store ADDRrr:$dst, i32:$val), (STrr ADDRrr:$dst, $val)>;
1028 def : Pat<(atomic_store ADDRri:$dst, i32:$val), (STri ADDRri:$dst, $val)>;
1031 include "SparcInstr64Bit.td"
1032 include "SparcInstrAliases.td"