1 //===- SparcInstrInfo.td - Target Description for Sparc Target ------------===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file describes the Sparc instructions in TableGen format.
12 //===----------------------------------------------------------------------===//
14 //===----------------------------------------------------------------------===//
15 // Instruction format superclass
16 //===----------------------------------------------------------------------===//
18 include "SparcInstrFormats.td"
20 //===----------------------------------------------------------------------===//
21 // Feature predicates.
22 //===----------------------------------------------------------------------===//
24 // HasV9 - This predicate is true when the target processor supports V9
25 // instructions. Note that the machine may be running in 32-bit mode.
26 def HasV9 : Predicate<"Subtarget.isV9()">;
28 // HasNoV9 - This predicate is true when the target doesn't have V9
29 // instructions. Use of this is just a hack for the isel not having proper
30 // costs for V8 instructions that are more expensive than their V9 ones.
31 def HasNoV9 : Predicate<"!Subtarget.isV9()">;
33 // HasVIS - This is true when the target processor has VIS extensions.
34 def HasVIS : Predicate<"Subtarget.isVIS()">;
36 // UseDeprecatedInsts - This predicate is true when the target processor is a
37 // V8, or when it is V9 but the V8 deprecated instructions are efficient enough
38 // to use when appropriate. In either of these cases, the instruction selector
39 // will pick deprecated instructions.
40 def UseDeprecatedInsts : Predicate<"Subtarget.useDeprecatedV8Instructions()">;
42 //===----------------------------------------------------------------------===//
43 // Instruction Pattern Stuff
44 //===----------------------------------------------------------------------===//
46 def simm11 : PatLeaf<(imm), [{ return isInt<11>(N->getSExtValue()); }]>;
48 def simm13 : PatLeaf<(imm), [{ return isInt<13>(N->getSExtValue()); }]>;
50 def LO10 : SDNodeXForm<imm, [{
51 return CurDAG->getTargetConstant((unsigned)N->getZExtValue() & 1023,
55 def HI22 : SDNodeXForm<imm, [{
56 // Transformation function: shift the immediate value down into the low bits.
57 return CurDAG->getTargetConstant((unsigned)N->getZExtValue() >> 10, MVT::i32);
60 def SETHIimm : PatLeaf<(imm), [{
61 return (((unsigned)N->getZExtValue() >> 10) << 10) ==
62 (unsigned)N->getZExtValue();
66 def ADDRrr : ComplexPattern<i32, 2, "SelectADDRrr", [], []>;
67 def ADDRri : ComplexPattern<i32, 2, "SelectADDRri", [frameindex], []>;
70 def MEMrr : Operand<i32> {
71 let PrintMethod = "printMemOperand";
72 let MIOperandInfo = (ops IntRegs, IntRegs);
74 def MEMri : Operand<i32> {
75 let PrintMethod = "printMemOperand";
76 let MIOperandInfo = (ops IntRegs, i32imm);
79 // Branch targets have OtherVT type.
80 def brtarget : Operand<OtherVT>;
81 def calltarget : Operand<i32>;
83 // Operand for printing out a condition code.
84 let PrintMethod = "printCCOperand" in
85 def CCOp : Operand<i32>;
88 SDTypeProfile<0, 2, [SDTCisFP<0>, SDTCisSameAs<0, 1>]>;
90 SDTypeProfile<0, 2, [SDTCisVT<0, OtherVT>, SDTCisVT<1, i32>]>;
92 SDTypeProfile<1, 3, [SDTCisSameAs<0, 1>, SDTCisSameAs<1, 2>, SDTCisVT<3, i32>]>;
94 SDTypeProfile<1, 1, [SDTCisVT<0, f32>, SDTCisFP<1>]>;
96 SDTypeProfile<1, 1, [SDTCisFP<0>, SDTCisVT<1, f32>]>;
98 def SPcmpicc : SDNode<"SPISD::CMPICC", SDTIntBinOp, [SDNPOutGlue]>;
99 def SPcmpfcc : SDNode<"SPISD::CMPFCC", SDTSPcmpfcc, [SDNPOutGlue]>;
100 def SPbricc : SDNode<"SPISD::BRICC", SDTSPbrcc, [SDNPHasChain, SDNPInGlue]>;
101 def SPbrfcc : SDNode<"SPISD::BRFCC", SDTSPbrcc, [SDNPHasChain, SDNPInGlue]>;
103 def SPhi : SDNode<"SPISD::Hi", SDTIntUnaryOp>;
104 def SPlo : SDNode<"SPISD::Lo", SDTIntUnaryOp>;
106 def SPftoi : SDNode<"SPISD::FTOI", SDTSPFTOI>;
107 def SPitof : SDNode<"SPISD::ITOF", SDTSPITOF>;
109 def SPselecticc : SDNode<"SPISD::SELECT_ICC", SDTSPselectcc, [SDNPInGlue]>;
110 def SPselectfcc : SDNode<"SPISD::SELECT_FCC", SDTSPselectcc, [SDNPInGlue]>;
112 // These are target-independent nodes, but have target-specific formats.
113 def SDT_SPCallSeqStart : SDCallSeqStart<[ SDTCisVT<0, i32> ]>;
114 def SDT_SPCallSeqEnd : SDCallSeqEnd<[ SDTCisVT<0, i32>,
117 def callseq_start : SDNode<"ISD::CALLSEQ_START", SDT_SPCallSeqStart,
118 [SDNPHasChain, SDNPOutGlue]>;
119 def callseq_end : SDNode<"ISD::CALLSEQ_END", SDT_SPCallSeqEnd,
120 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]>;
122 def SDT_SPCall : SDTypeProfile<0, 1, [SDTCisVT<0, i32>]>;
123 def call : SDNode<"SPISD::CALL", SDT_SPCall,
124 [SDNPHasChain, SDNPOptInGlue, SDNPOutGlue]>;
126 def retflag : SDNode<"SPISD::RET_FLAG", SDTNone,
127 [SDNPHasChain, SDNPOptInGlue]>;
129 def getPCX : Operand<i32> {
130 let PrintMethod = "printGetPCX";
133 //===----------------------------------------------------------------------===//
134 // SPARC Flag Conditions
135 //===----------------------------------------------------------------------===//
137 // Note that these values must be kept in sync with the CCOp::CondCode enum
139 class ICC_VAL<int N> : PatLeaf<(i32 N)>;
140 def ICC_NE : ICC_VAL< 9>; // Not Equal
141 def ICC_E : ICC_VAL< 1>; // Equal
142 def ICC_G : ICC_VAL<10>; // Greater
143 def ICC_LE : ICC_VAL< 2>; // Less or Equal
144 def ICC_GE : ICC_VAL<11>; // Greater or Equal
145 def ICC_L : ICC_VAL< 3>; // Less
146 def ICC_GU : ICC_VAL<12>; // Greater Unsigned
147 def ICC_LEU : ICC_VAL< 4>; // Less or Equal Unsigned
148 def ICC_CC : ICC_VAL<13>; // Carry Clear/Great or Equal Unsigned
149 def ICC_CS : ICC_VAL< 5>; // Carry Set/Less Unsigned
150 def ICC_POS : ICC_VAL<14>; // Positive
151 def ICC_NEG : ICC_VAL< 6>; // Negative
152 def ICC_VC : ICC_VAL<15>; // Overflow Clear
153 def ICC_VS : ICC_VAL< 7>; // Overflow Set
155 class FCC_VAL<int N> : PatLeaf<(i32 N)>;
156 def FCC_U : FCC_VAL<23>; // Unordered
157 def FCC_G : FCC_VAL<22>; // Greater
158 def FCC_UG : FCC_VAL<21>; // Unordered or Greater
159 def FCC_L : FCC_VAL<20>; // Less
160 def FCC_UL : FCC_VAL<19>; // Unordered or Less
161 def FCC_LG : FCC_VAL<18>; // Less or Greater
162 def FCC_NE : FCC_VAL<17>; // Not Equal
163 def FCC_E : FCC_VAL<25>; // Equal
164 def FCC_UE : FCC_VAL<24>; // Unordered or Equal
165 def FCC_GE : FCC_VAL<25>; // Greater or Equal
166 def FCC_UGE : FCC_VAL<26>; // Unordered or Greater or Equal
167 def FCC_LE : FCC_VAL<27>; // Less or Equal
168 def FCC_ULE : FCC_VAL<28>; // Unordered or Less or Equal
169 def FCC_O : FCC_VAL<29>; // Ordered
171 //===----------------------------------------------------------------------===//
172 // Instruction Class Templates
173 //===----------------------------------------------------------------------===//
175 /// F3_12 multiclass - Define a normal F3_1/F3_2 pattern in one shot.
176 multiclass F3_12<string OpcStr, bits<6> Op3Val, SDNode OpNode> {
177 def rr : F3_1<2, Op3Val,
178 (outs IntRegs:$dst), (ins IntRegs:$b, IntRegs:$c),
179 !strconcat(OpcStr, " $b, $c, $dst"),
180 [(set IntRegs:$dst, (OpNode IntRegs:$b, IntRegs:$c))]>;
181 def ri : F3_2<2, Op3Val,
182 (outs IntRegs:$dst), (ins IntRegs:$b, i32imm:$c),
183 !strconcat(OpcStr, " $b, $c, $dst"),
184 [(set IntRegs:$dst, (OpNode IntRegs:$b, simm13:$c))]>;
187 /// F3_12np multiclass - Define a normal F3_1/F3_2 pattern in one shot, with no
189 multiclass F3_12np<string OpcStr, bits<6> Op3Val> {
190 def rr : F3_1<2, Op3Val,
191 (outs IntRegs:$dst), (ins IntRegs:$b, IntRegs:$c),
192 !strconcat(OpcStr, " $b, $c, $dst"), []>;
193 def ri : F3_2<2, Op3Val,
194 (outs IntRegs:$dst), (ins IntRegs:$b, i32imm:$c),
195 !strconcat(OpcStr, " $b, $c, $dst"), []>;
198 //===----------------------------------------------------------------------===//
200 //===----------------------------------------------------------------------===//
202 // Pseudo instructions.
203 class Pseudo<dag outs, dag ins, string asmstr, list<dag> pattern>
204 : InstSP<outs, ins, asmstr, pattern>;
207 let Defs = [O7], Uses = [O7] in {
208 def GETPCX : Pseudo<(outs getPCX:$getpcseq), (ins), "$getpcseq", [] >;
211 let Defs = [O6], Uses = [O6] in {
212 def ADJCALLSTACKDOWN : Pseudo<(outs), (ins i32imm:$amt),
213 "!ADJCALLSTACKDOWN $amt",
214 [(callseq_start timm:$amt)]>;
215 def ADJCALLSTACKUP : Pseudo<(outs), (ins i32imm:$amt1, i32imm:$amt2),
216 "!ADJCALLSTACKUP $amt1",
217 [(callseq_end timm:$amt1, timm:$amt2)]>;
220 // FpMOVD/FpNEGD/FpABSD - These are lowered to single-precision ops by the
222 let Predicates = [HasNoV9] in { // Only emit these in V8 mode.
223 def FpMOVD : Pseudo<(outs DFPRegs:$dst), (ins DFPRegs:$src),
224 "!FpMOVD $src, $dst", []>;
225 def FpNEGD : Pseudo<(outs DFPRegs:$dst), (ins DFPRegs:$src),
226 "!FpNEGD $src, $dst",
227 [(set DFPRegs:$dst, (fneg DFPRegs:$src))]>;
228 def FpABSD : Pseudo<(outs DFPRegs:$dst), (ins DFPRegs:$src),
229 "!FpABSD $src, $dst",
230 [(set DFPRegs:$dst, (fabs DFPRegs:$src))]>;
233 // SELECT_CC_* - Used to implement the SELECT_CC DAG operation. Expanded after
234 // instruction selection into a branch sequence. This has to handle all
235 // permutations of selection between i32/f32/f64 on ICC and FCC.
237 usesCustomInserter = 1 in { // Expanded after instruction selection.
238 def SELECT_CC_Int_ICC
239 : Pseudo<(outs IntRegs:$dst), (ins IntRegs:$T, IntRegs:$F, i32imm:$Cond),
240 "; SELECT_CC_Int_ICC PSEUDO!",
241 [(set IntRegs:$dst, (SPselecticc IntRegs:$T, IntRegs:$F,
243 def SELECT_CC_Int_FCC
244 : Pseudo<(outs IntRegs:$dst), (ins IntRegs:$T, IntRegs:$F, i32imm:$Cond),
245 "; SELECT_CC_Int_FCC PSEUDO!",
246 [(set IntRegs:$dst, (SPselectfcc IntRegs:$T, IntRegs:$F,
250 let usesCustomInserter = 1, Uses = [FCC] in {
252 : Pseudo<(outs FPRegs:$dst), (ins FPRegs:$T, FPRegs:$F, i32imm:$Cond),
253 "; SELECT_CC_FP_ICC PSEUDO!",
254 [(set FPRegs:$dst, (SPselecticc FPRegs:$T, FPRegs:$F,
257 : Pseudo<(outs FPRegs:$dst), (ins FPRegs:$T, FPRegs:$F, i32imm:$Cond),
258 "; SELECT_CC_FP_FCC PSEUDO!",
259 [(set FPRegs:$dst, (SPselectfcc FPRegs:$T, FPRegs:$F,
261 def SELECT_CC_DFP_ICC
262 : Pseudo<(outs DFPRegs:$dst), (ins DFPRegs:$T, DFPRegs:$F, i32imm:$Cond),
263 "; SELECT_CC_DFP_ICC PSEUDO!",
264 [(set DFPRegs:$dst, (SPselecticc DFPRegs:$T, DFPRegs:$F,
266 def SELECT_CC_DFP_FCC
267 : Pseudo<(outs DFPRegs:$dst), (ins DFPRegs:$T, DFPRegs:$F, i32imm:$Cond),
268 "; SELECT_CC_DFP_FCC PSEUDO!",
269 [(set DFPRegs:$dst, (SPselectfcc DFPRegs:$T, DFPRegs:$F,
274 // Section A.3 - Synthetic Instructions, p. 85
275 // special cases of JMPL:
276 let isReturn = 1, isTerminator = 1, hasDelaySlot = 1, isBarrier = 1 in {
277 let rd = O7.Num, rs1 = G0.Num, simm13 = 8 in
278 def RETL: F3_2<2, 0b111000, (outs), (ins), "retl", [(retflag)]>;
281 // Section B.1 - Load Integer Instructions, p. 90
282 def LDSBrr : F3_1<3, 0b001001,
283 (outs IntRegs:$dst), (ins MEMrr:$addr),
284 "ldsb [$addr], $dst",
285 [(set IntRegs:$dst, (sextloadi8 ADDRrr:$addr))]>;
286 def LDSBri : F3_2<3, 0b001001,
287 (outs IntRegs:$dst), (ins MEMri:$addr),
288 "ldsb [$addr], $dst",
289 [(set IntRegs:$dst, (sextloadi8 ADDRri:$addr))]>;
290 def LDSHrr : F3_1<3, 0b001010,
291 (outs IntRegs:$dst), (ins MEMrr:$addr),
292 "ldsh [$addr], $dst",
293 [(set IntRegs:$dst, (sextloadi16 ADDRrr:$addr))]>;
294 def LDSHri : F3_2<3, 0b001010,
295 (outs IntRegs:$dst), (ins MEMri:$addr),
296 "ldsh [$addr], $dst",
297 [(set IntRegs:$dst, (sextloadi16 ADDRri:$addr))]>;
298 def LDUBrr : F3_1<3, 0b000001,
299 (outs IntRegs:$dst), (ins MEMrr:$addr),
300 "ldub [$addr], $dst",
301 [(set IntRegs:$dst, (zextloadi8 ADDRrr:$addr))]>;
302 def LDUBri : F3_2<3, 0b000001,
303 (outs IntRegs:$dst), (ins MEMri:$addr),
304 "ldub [$addr], $dst",
305 [(set IntRegs:$dst, (zextloadi8 ADDRri:$addr))]>;
306 def LDUHrr : F3_1<3, 0b000010,
307 (outs IntRegs:$dst), (ins MEMrr:$addr),
308 "lduh [$addr], $dst",
309 [(set IntRegs:$dst, (zextloadi16 ADDRrr:$addr))]>;
310 def LDUHri : F3_2<3, 0b000010,
311 (outs IntRegs:$dst), (ins MEMri:$addr),
312 "lduh [$addr], $dst",
313 [(set IntRegs:$dst, (zextloadi16 ADDRri:$addr))]>;
314 def LDrr : F3_1<3, 0b000000,
315 (outs IntRegs:$dst), (ins MEMrr:$addr),
317 [(set IntRegs:$dst, (load ADDRrr:$addr))]>;
318 def LDri : F3_2<3, 0b000000,
319 (outs IntRegs:$dst), (ins MEMri:$addr),
321 [(set IntRegs:$dst, (load ADDRri:$addr))]>;
323 // Section B.2 - Load Floating-point Instructions, p. 92
324 def LDFrr : F3_1<3, 0b100000,
325 (outs FPRegs:$dst), (ins MEMrr:$addr),
327 [(set FPRegs:$dst, (load ADDRrr:$addr))]>;
328 def LDFri : F3_2<3, 0b100000,
329 (outs FPRegs:$dst), (ins MEMri:$addr),
331 [(set FPRegs:$dst, (load ADDRri:$addr))]>;
332 def LDDFrr : F3_1<3, 0b100011,
333 (outs DFPRegs:$dst), (ins MEMrr:$addr),
335 [(set DFPRegs:$dst, (load ADDRrr:$addr))]>;
336 def LDDFri : F3_2<3, 0b100011,
337 (outs DFPRegs:$dst), (ins MEMri:$addr),
339 [(set DFPRegs:$dst, (load ADDRri:$addr))]>;
341 // Section B.4 - Store Integer Instructions, p. 95
342 def STBrr : F3_1<3, 0b000101,
343 (outs), (ins MEMrr:$addr, IntRegs:$src),
345 [(truncstorei8 IntRegs:$src, ADDRrr:$addr)]>;
346 def STBri : F3_2<3, 0b000101,
347 (outs), (ins MEMri:$addr, IntRegs:$src),
349 [(truncstorei8 IntRegs:$src, ADDRri:$addr)]>;
350 def STHrr : F3_1<3, 0b000110,
351 (outs), (ins MEMrr:$addr, IntRegs:$src),
353 [(truncstorei16 IntRegs:$src, ADDRrr:$addr)]>;
354 def STHri : F3_2<3, 0b000110,
355 (outs), (ins MEMri:$addr, IntRegs:$src),
357 [(truncstorei16 IntRegs:$src, ADDRri:$addr)]>;
358 def STrr : F3_1<3, 0b000100,
359 (outs), (ins MEMrr:$addr, IntRegs:$src),
361 [(store IntRegs:$src, ADDRrr:$addr)]>;
362 def STri : F3_2<3, 0b000100,
363 (outs), (ins MEMri:$addr, IntRegs:$src),
365 [(store IntRegs:$src, ADDRri:$addr)]>;
367 // Section B.5 - Store Floating-point Instructions, p. 97
368 def STFrr : F3_1<3, 0b100100,
369 (outs), (ins MEMrr:$addr, FPRegs:$src),
371 [(store FPRegs:$src, ADDRrr:$addr)]>;
372 def STFri : F3_2<3, 0b100100,
373 (outs), (ins MEMri:$addr, FPRegs:$src),
375 [(store FPRegs:$src, ADDRri:$addr)]>;
376 def STDFrr : F3_1<3, 0b100111,
377 (outs), (ins MEMrr:$addr, DFPRegs:$src),
379 [(store DFPRegs:$src, ADDRrr:$addr)]>;
380 def STDFri : F3_2<3, 0b100111,
381 (outs), (ins MEMri:$addr, DFPRegs:$src),
383 [(store DFPRegs:$src, ADDRri:$addr)]>;
385 // Section B.9 - SETHI Instruction, p. 104
386 def SETHIi: F2_1<0b100,
387 (outs IntRegs:$dst), (ins i32imm:$src),
389 [(set IntRegs:$dst, SETHIimm:$src)]>;
391 // Section B.10 - NOP Instruction, p. 105
392 // (It's a special case of SETHI)
393 let rd = 0, imm22 = 0 in
394 def NOP : F2_1<0b100, (outs), (ins), "nop", []>;
396 // Section B.11 - Logical Instructions, p. 106
397 defm AND : F3_12<"and", 0b000001, and>;
399 def ANDNrr : F3_1<2, 0b000101,
400 (outs IntRegs:$dst), (ins IntRegs:$b, IntRegs:$c),
402 [(set IntRegs:$dst, (and IntRegs:$b, (not IntRegs:$c)))]>;
403 def ANDNri : F3_2<2, 0b000101,
404 (outs IntRegs:$dst), (ins IntRegs:$b, i32imm:$c),
405 "andn $b, $c, $dst", []>;
407 defm OR : F3_12<"or", 0b000010, or>;
409 def ORNrr : F3_1<2, 0b000110,
410 (outs IntRegs:$dst), (ins IntRegs:$b, IntRegs:$c),
412 [(set IntRegs:$dst, (or IntRegs:$b, (not IntRegs:$c)))]>;
413 def ORNri : F3_2<2, 0b000110,
414 (outs IntRegs:$dst), (ins IntRegs:$b, i32imm:$c),
415 "orn $b, $c, $dst", []>;
416 defm XOR : F3_12<"xor", 0b000011, xor>;
418 def XNORrr : F3_1<2, 0b000111,
419 (outs IntRegs:$dst), (ins IntRegs:$b, IntRegs:$c),
421 [(set IntRegs:$dst, (not (xor IntRegs:$b, IntRegs:$c)))]>;
422 def XNORri : F3_2<2, 0b000111,
423 (outs IntRegs:$dst), (ins IntRegs:$b, i32imm:$c),
424 "xnor $b, $c, $dst", []>;
426 // Section B.12 - Shift Instructions, p. 107
427 defm SLL : F3_12<"sll", 0b100101, shl>;
428 defm SRL : F3_12<"srl", 0b100110, srl>;
429 defm SRA : F3_12<"sra", 0b100111, sra>;
431 // Section B.13 - Add Instructions, p. 108
432 defm ADD : F3_12<"add", 0b000000, add>;
434 // "LEA" forms of add (patterns to make tblgen happy)
435 def LEA_ADDri : F3_2<2, 0b000000,
436 (outs IntRegs:$dst), (ins MEMri:$addr),
437 "add ${addr:arith}, $dst",
438 [(set IntRegs:$dst, ADDRri:$addr)]>;
441 defm ADDCC : F3_12<"addcc", 0b010000, addc>;
443 defm ADDX : F3_12<"addx", 0b001000, adde>;
445 // Section B.15 - Subtract Instructions, p. 110
446 defm SUB : F3_12 <"sub" , 0b000100, sub>;
448 defm SUBX : F3_12 <"subx" , 0b001100, sube>;
451 defm SUBCC : F3_12 <"subcc", 0b010100, SPcmpicc>;
453 let Uses = [ICC], Defs = [ICC] in
454 def SUBXCCrr: F3_1<2, 0b011100,
455 (outs IntRegs:$dst), (ins IntRegs:$b, IntRegs:$c),
456 "subxcc $b, $c, $dst", []>;
459 // Section B.18 - Multiply Instructions, p. 113
461 defm UMUL : F3_12np<"umul", 0b001010>;
462 defm SMUL : F3_12 <"smul", 0b001011, mul>;
465 // Section B.19 - Divide Instructions, p. 115
467 defm UDIV : F3_12np<"udiv", 0b001110>;
468 defm SDIV : F3_12np<"sdiv", 0b001111>;
471 // Section B.20 - SAVE and RESTORE, p. 117
472 defm SAVE : F3_12np<"save" , 0b111100>;
473 defm RESTORE : F3_12np<"restore", 0b111101>;
475 // Section B.21 - Branch on Integer Condition Codes Instructions, p. 119
477 // conditional branch class:
478 class BranchSP<bits<4> cc, dag ins, string asmstr, list<dag> pattern>
479 : F2_2<cc, 0b010, (outs), ins, asmstr, pattern> {
481 let isTerminator = 1;
482 let hasDelaySlot = 1;
486 def BA : BranchSP<0b1000, (ins brtarget:$dst),
490 // FIXME: the encoding for the JIT should look at the condition field.
492 def BCOND : BranchSP<0, (ins brtarget:$dst, CCOp:$cc),
494 [(SPbricc bb:$dst, imm:$cc)]>;
497 // Section B.22 - Branch on Floating-point Condition Codes Instructions, p. 121
499 // floating-point conditional branch class:
500 class FPBranchSP<bits<4> cc, dag ins, string asmstr, list<dag> pattern>
501 : F2_2<cc, 0b110, (outs), ins, asmstr, pattern> {
503 let isTerminator = 1;
504 let hasDelaySlot = 1;
507 // FIXME: the encoding for the JIT should look at the condition field.
509 def FBCOND : FPBranchSP<0, (ins brtarget:$dst, CCOp:$cc),
511 [(SPbrfcc bb:$dst, imm:$cc)]>;
514 // Section B.24 - Call and Link Instruction, p. 125
515 // This is the only Format 1 instruction
516 let Uses = [O0, O1, O2, O3, O4, O5],
517 hasDelaySlot = 1, isCall = 1,
518 Defs = [O0, O1, O2, O3, O4, O5, O7, G1, G2, G3, G4, G5, G6, G7,
519 D0, D1, D2, D3, D4, D5, D6, D7, D8, D9, D10, D11, D12, D13, D14, D15] in {
520 def CALL : InstSP<(outs), (ins calltarget:$dst),
524 let Inst{29-0} = disp;
528 def JMPLrr : F3_1<2, 0b111000,
529 (outs), (ins MEMrr:$ptr),
531 [(call ADDRrr:$ptr)]>;
532 def JMPLri : F3_2<2, 0b111000,
533 (outs), (ins MEMri:$ptr),
535 [(call ADDRri:$ptr)]>;
538 // Section B.28 - Read State Register Instructions
540 def RDY : F3_1<2, 0b101000,
541 (outs IntRegs:$dst), (ins),
544 // Section B.29 - Write State Register Instructions
546 def WRYrr : F3_1<2, 0b110000,
547 (outs), (ins IntRegs:$b, IntRegs:$c),
548 "wr $b, $c, %y", []>;
549 def WRYri : F3_2<2, 0b110000,
550 (outs), (ins IntRegs:$b, i32imm:$c),
551 "wr $b, $c, %y", []>;
553 // Convert Integer to Floating-point Instructions, p. 141
554 def FITOS : F3_3<2, 0b110100, 0b011000100,
555 (outs FPRegs:$dst), (ins FPRegs:$src),
557 [(set FPRegs:$dst, (SPitof FPRegs:$src))]>;
558 def FITOD : F3_3<2, 0b110100, 0b011001000,
559 (outs DFPRegs:$dst), (ins FPRegs:$src),
561 [(set DFPRegs:$dst, (SPitof FPRegs:$src))]>;
563 // Convert Floating-point to Integer Instructions, p. 142
564 def FSTOI : F3_3<2, 0b110100, 0b011010001,
565 (outs FPRegs:$dst), (ins FPRegs:$src),
567 [(set FPRegs:$dst, (SPftoi FPRegs:$src))]>;
568 def FDTOI : F3_3<2, 0b110100, 0b011010010,
569 (outs FPRegs:$dst), (ins DFPRegs:$src),
571 [(set FPRegs:$dst, (SPftoi DFPRegs:$src))]>;
573 // Convert between Floating-point Formats Instructions, p. 143
574 def FSTOD : F3_3<2, 0b110100, 0b011001001,
575 (outs DFPRegs:$dst), (ins FPRegs:$src),
577 [(set DFPRegs:$dst, (fextend FPRegs:$src))]>;
578 def FDTOS : F3_3<2, 0b110100, 0b011000110,
579 (outs FPRegs:$dst), (ins DFPRegs:$src),
581 [(set FPRegs:$dst, (fround DFPRegs:$src))]>;
583 // Floating-point Move Instructions, p. 144
584 def FMOVS : F3_3<2, 0b110100, 0b000000001,
585 (outs FPRegs:$dst), (ins FPRegs:$src),
586 "fmovs $src, $dst", []>;
587 def FNEGS : F3_3<2, 0b110100, 0b000000101,
588 (outs FPRegs:$dst), (ins FPRegs:$src),
590 [(set FPRegs:$dst, (fneg FPRegs:$src))]>;
591 def FABSS : F3_3<2, 0b110100, 0b000001001,
592 (outs FPRegs:$dst), (ins FPRegs:$src),
594 [(set FPRegs:$dst, (fabs FPRegs:$src))]>;
597 // Floating-point Square Root Instructions, p.145
598 def FSQRTS : F3_3<2, 0b110100, 0b000101001,
599 (outs FPRegs:$dst), (ins FPRegs:$src),
601 [(set FPRegs:$dst, (fsqrt FPRegs:$src))]>;
602 def FSQRTD : F3_3<2, 0b110100, 0b000101010,
603 (outs DFPRegs:$dst), (ins DFPRegs:$src),
605 [(set DFPRegs:$dst, (fsqrt DFPRegs:$src))]>;
609 // Floating-point Add and Subtract Instructions, p. 146
610 def FADDS : F3_3<2, 0b110100, 0b001000001,
611 (outs FPRegs:$dst), (ins FPRegs:$src1, FPRegs:$src2),
612 "fadds $src1, $src2, $dst",
613 [(set FPRegs:$dst, (fadd FPRegs:$src1, FPRegs:$src2))]>;
614 def FADDD : F3_3<2, 0b110100, 0b001000010,
615 (outs DFPRegs:$dst), (ins DFPRegs:$src1, DFPRegs:$src2),
616 "faddd $src1, $src2, $dst",
617 [(set DFPRegs:$dst, (fadd DFPRegs:$src1, DFPRegs:$src2))]>;
618 def FSUBS : F3_3<2, 0b110100, 0b001000101,
619 (outs FPRegs:$dst), (ins FPRegs:$src1, FPRegs:$src2),
620 "fsubs $src1, $src2, $dst",
621 [(set FPRegs:$dst, (fsub FPRegs:$src1, FPRegs:$src2))]>;
622 def FSUBD : F3_3<2, 0b110100, 0b001000110,
623 (outs DFPRegs:$dst), (ins DFPRegs:$src1, DFPRegs:$src2),
624 "fsubd $src1, $src2, $dst",
625 [(set DFPRegs:$dst, (fsub DFPRegs:$src1, DFPRegs:$src2))]>;
627 // Floating-point Multiply and Divide Instructions, p. 147
628 def FMULS : F3_3<2, 0b110100, 0b001001001,
629 (outs FPRegs:$dst), (ins FPRegs:$src1, FPRegs:$src2),
630 "fmuls $src1, $src2, $dst",
631 [(set FPRegs:$dst, (fmul FPRegs:$src1, FPRegs:$src2))]>;
632 def FMULD : F3_3<2, 0b110100, 0b001001010,
633 (outs DFPRegs:$dst), (ins DFPRegs:$src1, DFPRegs:$src2),
634 "fmuld $src1, $src2, $dst",
635 [(set DFPRegs:$dst, (fmul DFPRegs:$src1, DFPRegs:$src2))]>;
636 def FSMULD : F3_3<2, 0b110100, 0b001101001,
637 (outs DFPRegs:$dst), (ins FPRegs:$src1, FPRegs:$src2),
638 "fsmuld $src1, $src2, $dst",
639 [(set DFPRegs:$dst, (fmul (fextend FPRegs:$src1),
640 (fextend FPRegs:$src2)))]>;
641 def FDIVS : F3_3<2, 0b110100, 0b001001101,
642 (outs FPRegs:$dst), (ins FPRegs:$src1, FPRegs:$src2),
643 "fdivs $src1, $src2, $dst",
644 [(set FPRegs:$dst, (fdiv FPRegs:$src1, FPRegs:$src2))]>;
645 def FDIVD : F3_3<2, 0b110100, 0b001001110,
646 (outs DFPRegs:$dst), (ins DFPRegs:$src1, DFPRegs:$src2),
647 "fdivd $src1, $src2, $dst",
648 [(set DFPRegs:$dst, (fdiv DFPRegs:$src1, DFPRegs:$src2))]>;
650 // Floating-point Compare Instructions, p. 148
651 // Note: the 2nd template arg is different for these guys.
652 // Note 2: the result of a FCMP is not available until the 2nd cycle
653 // after the instr is retired, but there is no interlock. This behavior
654 // is modelled with a forced noop after the instruction.
655 let Defs = [FCC] in {
656 def FCMPS : F3_3<2, 0b110101, 0b001010001,
657 (outs), (ins FPRegs:$src1, FPRegs:$src2),
658 "fcmps $src1, $src2\n\tnop",
659 [(SPcmpfcc FPRegs:$src1, FPRegs:$src2)]>;
660 def FCMPD : F3_3<2, 0b110101, 0b001010010,
661 (outs), (ins DFPRegs:$src1, DFPRegs:$src2),
662 "fcmpd $src1, $src2\n\tnop",
663 [(SPcmpfcc DFPRegs:$src1, DFPRegs:$src2)]>;
666 //===----------------------------------------------------------------------===//
668 //===----------------------------------------------------------------------===//
670 // V9 Conditional Moves.
671 let Predicates = [HasV9], Constraints = "$T = $dst" in {
672 // Move Integer Register on Condition (MOVcc) p. 194 of the V9 manual.
673 // FIXME: Add instruction encodings for the JIT some day.
675 : Pseudo<(outs IntRegs:$dst), (ins IntRegs:$T, IntRegs:$F, CCOp:$cc),
676 "mov$cc %icc, $F, $dst",
678 (SPselecticc IntRegs:$F, IntRegs:$T, imm:$cc))]>;
680 : Pseudo<(outs IntRegs:$dst), (ins IntRegs:$T, i32imm:$F, CCOp:$cc),
681 "mov$cc %icc, $F, $dst",
683 (SPselecticc simm11:$F, IntRegs:$T, imm:$cc))]>;
686 : Pseudo<(outs IntRegs:$dst), (ins IntRegs:$T, IntRegs:$F, CCOp:$cc),
687 "mov$cc %fcc0, $F, $dst",
689 (SPselectfcc IntRegs:$F, IntRegs:$T, imm:$cc))]>;
691 : Pseudo<(outs IntRegs:$dst), (ins IntRegs:$T, i32imm:$F, CCOp:$cc),
692 "mov$cc %fcc0, $F, $dst",
694 (SPselectfcc simm11:$F, IntRegs:$T, imm:$cc))]>;
697 : Pseudo<(outs FPRegs:$dst), (ins FPRegs:$T, FPRegs:$F, CCOp:$cc),
698 "fmovs$cc %icc, $F, $dst",
700 (SPselecticc FPRegs:$F, FPRegs:$T, imm:$cc))]>;
702 : Pseudo<(outs DFPRegs:$dst), (ins DFPRegs:$T, DFPRegs:$F, CCOp:$cc),
703 "fmovd$cc %icc, $F, $dst",
705 (SPselecticc DFPRegs:$F, DFPRegs:$T, imm:$cc))]>;
707 : Pseudo<(outs FPRegs:$dst), (ins FPRegs:$T, FPRegs:$F, CCOp:$cc),
708 "fmovs$cc %fcc0, $F, $dst",
710 (SPselectfcc FPRegs:$F, FPRegs:$T, imm:$cc))]>;
712 : Pseudo<(outs DFPRegs:$dst), (ins DFPRegs:$T, DFPRegs:$F, CCOp:$cc),
713 "fmovd$cc %fcc0, $F, $dst",
715 (SPselectfcc DFPRegs:$F, DFPRegs:$T, imm:$cc))]>;
719 // Floating-Point Move Instructions, p. 164 of the V9 manual.
720 let Predicates = [HasV9] in {
721 def FMOVD : F3_3<2, 0b110100, 0b000000010,
722 (outs DFPRegs:$dst), (ins DFPRegs:$src),
723 "fmovd $src, $dst", []>;
724 def FNEGD : F3_3<2, 0b110100, 0b000000110,
725 (outs DFPRegs:$dst), (ins DFPRegs:$src),
727 [(set DFPRegs:$dst, (fneg DFPRegs:$src))]>;
728 def FABSD : F3_3<2, 0b110100, 0b000001010,
729 (outs DFPRegs:$dst), (ins DFPRegs:$src),
731 [(set DFPRegs:$dst, (fabs DFPRegs:$src))]>;
734 // POPCrr - This does a ctpop of a 64-bit register. As such, we have to clear
735 // the top 32-bits before using it. To do this clearing, we use a SLLri X,0.
736 def POPCrr : F3_1<2, 0b101110,
737 (outs IntRegs:$dst), (ins IntRegs:$src),
738 "popc $src, $dst", []>, Requires<[HasV9]>;
739 def : Pat<(ctpop IntRegs:$src),
740 (POPCrr (SLLri IntRegs:$src, 0))>;
742 //===----------------------------------------------------------------------===//
743 // Non-Instruction Patterns
744 //===----------------------------------------------------------------------===//
747 def : Pat<(i32 simm13:$val),
748 (ORri G0, imm:$val)>;
749 // Arbitrary immediates.
750 def : Pat<(i32 imm:$val),
751 (ORri (SETHIi (HI22 imm:$val)), (LO10 imm:$val))>;
754 def : Pat<(subc IntRegs:$b, IntRegs:$c),
755 (SUBCCrr IntRegs:$b, IntRegs:$c)>;
756 def : Pat<(subc IntRegs:$b, simm13:$val),
757 (SUBCCri IntRegs:$b, imm:$val)>;
759 // Global addresses, constant pool entries
760 def : Pat<(SPhi tglobaladdr:$in), (SETHIi tglobaladdr:$in)>;
761 def : Pat<(SPlo tglobaladdr:$in), (ORri G0, tglobaladdr:$in)>;
762 def : Pat<(SPhi tconstpool:$in), (SETHIi tconstpool:$in)>;
763 def : Pat<(SPlo tconstpool:$in), (ORri G0, tconstpool:$in)>;
765 // Add reg, lo. This is used when taking the addr of a global/constpool entry.
766 def : Pat<(add IntRegs:$r, (SPlo tglobaladdr:$in)),
767 (ADDri IntRegs:$r, tglobaladdr:$in)>;
768 def : Pat<(add IntRegs:$r, (SPlo tconstpool:$in)),
769 (ADDri IntRegs:$r, tconstpool:$in)>;
772 def : Pat<(call tglobaladdr:$dst),
773 (CALL tglobaladdr:$dst)>;
774 def : Pat<(call texternalsym:$dst),
775 (CALL texternalsym:$dst)>;
777 // Map integer extload's to zextloads.
778 def : Pat<(i32 (extloadi1 ADDRrr:$src)), (LDUBrr ADDRrr:$src)>;
779 def : Pat<(i32 (extloadi1 ADDRri:$src)), (LDUBri ADDRri:$src)>;
780 def : Pat<(i32 (extloadi8 ADDRrr:$src)), (LDUBrr ADDRrr:$src)>;
781 def : Pat<(i32 (extloadi8 ADDRri:$src)), (LDUBri ADDRri:$src)>;
782 def : Pat<(i32 (extloadi16 ADDRrr:$src)), (LDUHrr ADDRrr:$src)>;
783 def : Pat<(i32 (extloadi16 ADDRri:$src)), (LDUHri ADDRri:$src)>;
785 // zextload bool -> zextload byte
786 def : Pat<(i32 (zextloadi1 ADDRrr:$src)), (LDUBrr ADDRrr:$src)>;
787 def : Pat<(i32 (zextloadi1 ADDRri:$src)), (LDUBri ADDRri:$src)>;