1 //===- SparcInstrInfo.cpp - Sparc Instruction Information -------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the Sparc implementation of the TargetInstrInfo class.
12 //===----------------------------------------------------------------------===//
14 #include "SparcInstrInfo.h"
15 #include "SparcSubtarget.h"
17 #include "llvm/ADT/STLExtras.h"
18 #include "llvm/ADT/SmallVector.h"
19 #include "llvm/CodeGen/MachineInstrBuilder.h"
20 #include "llvm/CodeGen/MachineRegisterInfo.h"
21 #include "llvm/Support/ErrorHandling.h"
22 #include "SparcGenInstrInfo.inc"
23 #include "SparcMachineFunctionInfo.h"
26 SparcInstrInfo::SparcInstrInfo(SparcSubtarget &ST)
27 : TargetInstrInfoImpl(SparcInsts, array_lengthof(SparcInsts)),
28 RI(ST, *this), Subtarget(ST) {
31 static bool isZeroImm(const MachineOperand &op) {
32 return op.isImm() && op.getImm() == 0;
35 /// Return true if the instruction is a register to register move and
36 /// leave the source and dest operands in the passed parameters.
38 bool SparcInstrInfo::isMoveInstr(const MachineInstr &MI,
39 unsigned &SrcReg, unsigned &DstReg,
40 unsigned &SrcSR, unsigned &DstSR) const {
41 SrcSR = DstSR = 0; // No sub-registers.
43 // We look for 3 kinds of patterns here:
46 // fmovs or FpMOVD (pseudo double move).
47 if (MI.getOpcode() == SP::ORrr || MI.getOpcode() == SP::ADDrr) {
48 if (MI.getOperand(1).getReg() == SP::G0) {
49 DstReg = MI.getOperand(0).getReg();
50 SrcReg = MI.getOperand(2).getReg();
52 } else if (MI.getOperand(2).getReg() == SP::G0) {
53 DstReg = MI.getOperand(0).getReg();
54 SrcReg = MI.getOperand(1).getReg();
57 } else if ((MI.getOpcode() == SP::ORri || MI.getOpcode() == SP::ADDri) &&
58 isZeroImm(MI.getOperand(2)) && MI.getOperand(1).isReg()) {
59 DstReg = MI.getOperand(0).getReg();
60 SrcReg = MI.getOperand(1).getReg();
62 } else if (MI.getOpcode() == SP::FMOVS || MI.getOpcode() == SP::FpMOVD ||
63 MI.getOpcode() == SP::FMOVD) {
64 SrcReg = MI.getOperand(1).getReg();
65 DstReg = MI.getOperand(0).getReg();
71 /// isLoadFromStackSlot - If the specified machine instruction is a direct
72 /// load from a stack slot, return the virtual or physical register number of
73 /// the destination along with the FrameIndex of the loaded stack slot. If
74 /// not, return 0. This predicate must return 0 if the instruction has
75 /// any side effects other than loading from the stack slot.
76 unsigned SparcInstrInfo::isLoadFromStackSlot(const MachineInstr *MI,
77 int &FrameIndex) const {
78 if (MI->getOpcode() == SP::LDri ||
79 MI->getOpcode() == SP::LDFri ||
80 MI->getOpcode() == SP::LDDFri) {
81 if (MI->getOperand(1).isFI() && MI->getOperand(2).isImm() &&
82 MI->getOperand(2).getImm() == 0) {
83 FrameIndex = MI->getOperand(1).getIndex();
84 return MI->getOperand(0).getReg();
90 /// isStoreToStackSlot - If the specified machine instruction is a direct
91 /// store to a stack slot, return the virtual or physical register number of
92 /// the source reg along with the FrameIndex of the loaded stack slot. If
93 /// not, return 0. This predicate must return 0 if the instruction has
94 /// any side effects other than storing to the stack slot.
95 unsigned SparcInstrInfo::isStoreToStackSlot(const MachineInstr *MI,
96 int &FrameIndex) const {
97 if (MI->getOpcode() == SP::STri ||
98 MI->getOpcode() == SP::STFri ||
99 MI->getOpcode() == SP::STDFri) {
100 if (MI->getOperand(0).isFI() && MI->getOperand(1).isImm() &&
101 MI->getOperand(1).getImm() == 0) {
102 FrameIndex = MI->getOperand(0).getIndex();
103 return MI->getOperand(2).getReg();
110 SparcInstrInfo::InsertBranch(MachineBasicBlock &MBB,MachineBasicBlock *TBB,
111 MachineBasicBlock *FBB,
112 const SmallVectorImpl<MachineOperand> &Cond,
114 // Can only insert uncond branches so far.
115 assert(Cond.empty() && !FBB && TBB && "Can only handle uncond branches!");
116 BuildMI(&MBB, DL, get(SP::BA)).addMBB(TBB);
120 bool SparcInstrInfo::copyRegToReg(MachineBasicBlock &MBB,
121 MachineBasicBlock::iterator I,
122 unsigned DestReg, unsigned SrcReg,
123 const TargetRegisterClass *DestRC,
124 const TargetRegisterClass *SrcRC,
126 if (DestRC != SrcRC) {
127 // Not yet supported!
131 if (DestRC == SP::IntRegsRegisterClass)
132 BuildMI(MBB, I, DL, get(SP::ORrr), DestReg).addReg(SP::G0).addReg(SrcReg);
133 else if (DestRC == SP::FPRegsRegisterClass)
134 BuildMI(MBB, I, DL, get(SP::FMOVS), DestReg).addReg(SrcReg);
135 else if (DestRC == SP::DFPRegsRegisterClass)
136 BuildMI(MBB, I, DL, get(Subtarget.isV9() ? SP::FMOVD : SP::FpMOVD),DestReg)
139 // Can't copy this register
145 void SparcInstrInfo::
146 storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
147 unsigned SrcReg, bool isKill, int FI,
148 const TargetRegisterClass *RC,
149 const TargetRegisterInfo *TRI) const {
151 if (I != MBB.end()) DL = I->getDebugLoc();
153 // On the order of operands here: think "[FrameIdx + 0] = SrcReg".
154 if (RC == SP::IntRegsRegisterClass)
155 BuildMI(MBB, I, DL, get(SP::STri)).addFrameIndex(FI).addImm(0)
156 .addReg(SrcReg, getKillRegState(isKill));
157 else if (RC == SP::FPRegsRegisterClass)
158 BuildMI(MBB, I, DL, get(SP::STFri)).addFrameIndex(FI).addImm(0)
159 .addReg(SrcReg, getKillRegState(isKill));
160 else if (RC == SP::DFPRegsRegisterClass)
161 BuildMI(MBB, I, DL, get(SP::STDFri)).addFrameIndex(FI).addImm(0)
162 .addReg(SrcReg, getKillRegState(isKill));
164 llvm_unreachable("Can't store this register to stack slot");
167 void SparcInstrInfo::
168 loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
169 unsigned DestReg, int FI,
170 const TargetRegisterClass *RC,
171 const TargetRegisterInfo *TRI) const {
173 if (I != MBB.end()) DL = I->getDebugLoc();
175 if (RC == SP::IntRegsRegisterClass)
176 BuildMI(MBB, I, DL, get(SP::LDri), DestReg).addFrameIndex(FI).addImm(0);
177 else if (RC == SP::FPRegsRegisterClass)
178 BuildMI(MBB, I, DL, get(SP::LDFri), DestReg).addFrameIndex(FI).addImm(0);
179 else if (RC == SP::DFPRegsRegisterClass)
180 BuildMI(MBB, I, DL, get(SP::LDDFri), DestReg).addFrameIndex(FI).addImm(0);
182 llvm_unreachable("Can't load this register from stack slot");
185 MachineInstr *SparcInstrInfo::foldMemoryOperandImpl(MachineFunction &MF,
187 const SmallVectorImpl<unsigned> &Ops,
189 if (Ops.size() != 1) return NULL;
191 unsigned OpNum = Ops[0];
192 bool isFloat = false;
193 MachineInstr *NewMI = NULL;
194 switch (MI->getOpcode()) {
196 if (MI->getOperand(1).isReg() && MI->getOperand(1).getReg() == SP::G0&&
197 MI->getOperand(0).isReg() && MI->getOperand(2).isReg()) {
198 if (OpNum == 0) // COPY -> STORE
199 NewMI = BuildMI(MF, MI->getDebugLoc(), get(SP::STri))
202 .addReg(MI->getOperand(2).getReg());
204 NewMI = BuildMI(MF, MI->getDebugLoc(), get(SP::LDri),
205 MI->getOperand(0).getReg())
214 if (OpNum == 0) { // COPY -> STORE
215 unsigned SrcReg = MI->getOperand(1).getReg();
216 bool isKill = MI->getOperand(1).isKill();
217 bool isUndef = MI->getOperand(1).isUndef();
218 NewMI = BuildMI(MF, MI->getDebugLoc(),
219 get(isFloat ? SP::STFri : SP::STDFri))
222 .addReg(SrcReg, getKillRegState(isKill) | getUndefRegState(isUndef));
223 } else { // COPY -> LOAD
224 unsigned DstReg = MI->getOperand(0).getReg();
225 bool isDead = MI->getOperand(0).isDead();
226 bool isUndef = MI->getOperand(0).isUndef();
227 NewMI = BuildMI(MF, MI->getDebugLoc(),
228 get(isFloat ? SP::LDFri : SP::LDDFri))
229 .addReg(DstReg, RegState::Define |
230 getDeadRegState(isDead) | getUndefRegState(isUndef))
240 unsigned SparcInstrInfo::getGlobalBaseReg(MachineFunction *MF) const
242 SparcMachineFunctionInfo *SparcFI = MF->getInfo<SparcMachineFunctionInfo>();
243 unsigned GlobalBaseReg = SparcFI->getGlobalBaseReg();
244 if (GlobalBaseReg != 0)
245 return GlobalBaseReg;
247 // Insert the set of GlobalBaseReg into the first MBB of the function
248 MachineBasicBlock &FirstMBB = MF->front();
249 MachineBasicBlock::iterator MBBI = FirstMBB.begin();
250 MachineRegisterInfo &RegInfo = MF->getRegInfo();
252 GlobalBaseReg = RegInfo.createVirtualRegister(&SP::IntRegsRegClass);
257 BuildMI(FirstMBB, MBBI, dl, get(SP::GETPCX), GlobalBaseReg);
258 SparcFI->setGlobalBaseReg(GlobalBaseReg);
259 return GlobalBaseReg;