1 //===- SparcInstrInfo.cpp - Sparc Instruction Information -------*- C++ -*-===//
3 // The LLVM Compiler Infrastructure
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
8 //===----------------------------------------------------------------------===//
10 // This file contains the Sparc implementation of the TargetInstrInfo class.
12 //===----------------------------------------------------------------------===//
14 #include "SparcInstrInfo.h"
15 #include "SparcSubtarget.h"
17 #include "llvm/ADT/STLExtras.h"
18 #include "llvm/ADT/SmallVector.h"
19 #include "llvm/CodeGen/MachineInstrBuilder.h"
20 #include "llvm/Support/ErrorHandling.h"
21 #include "SparcGenInstrInfo.inc"
24 SparcInstrInfo::SparcInstrInfo(SparcSubtarget &ST)
25 : TargetInstrInfoImpl(SparcInsts, array_lengthof(SparcInsts)),
26 RI(ST, *this), Subtarget(ST) {
29 static bool isZeroImm(const MachineOperand &op) {
30 return op.isImm() && op.getImm() == 0;
33 /// Return true if the instruction is a register to register move and
34 /// leave the source and dest operands in the passed parameters.
36 bool SparcInstrInfo::isMoveInstr(const MachineInstr &MI,
37 unsigned &SrcReg, unsigned &DstReg,
38 unsigned &SrcSR, unsigned &DstSR) const {
39 SrcSR = DstSR = 0; // No sub-registers.
41 // We look for 3 kinds of patterns here:
44 // fmovs or FpMOVD (pseudo double move).
45 if (MI.getOpcode() == SP::ORrr || MI.getOpcode() == SP::ADDrr) {
46 if (MI.getOperand(1).getReg() == SP::G0) {
47 DstReg = MI.getOperand(0).getReg();
48 SrcReg = MI.getOperand(2).getReg();
50 } else if (MI.getOperand(2).getReg() == SP::G0) {
51 DstReg = MI.getOperand(0).getReg();
52 SrcReg = MI.getOperand(1).getReg();
55 } else if ((MI.getOpcode() == SP::ORri || MI.getOpcode() == SP::ADDri) &&
56 isZeroImm(MI.getOperand(2)) && MI.getOperand(1).isReg()) {
57 DstReg = MI.getOperand(0).getReg();
58 SrcReg = MI.getOperand(1).getReg();
60 } else if (MI.getOpcode() == SP::FMOVS || MI.getOpcode() == SP::FpMOVD ||
61 MI.getOpcode() == SP::FMOVD) {
62 SrcReg = MI.getOperand(1).getReg();
63 DstReg = MI.getOperand(0).getReg();
69 /// isLoadFromStackSlot - If the specified machine instruction is a direct
70 /// load from a stack slot, return the virtual or physical register number of
71 /// the destination along with the FrameIndex of the loaded stack slot. If
72 /// not, return 0. This predicate must return 0 if the instruction has
73 /// any side effects other than loading from the stack slot.
74 unsigned SparcInstrInfo::isLoadFromStackSlot(const MachineInstr *MI,
75 int &FrameIndex) const {
76 if (MI->getOpcode() == SP::LDri ||
77 MI->getOpcode() == SP::LDFri ||
78 MI->getOpcode() == SP::LDDFri) {
79 if (MI->getOperand(1).isFI() && MI->getOperand(2).isImm() &&
80 MI->getOperand(2).getImm() == 0) {
81 FrameIndex = MI->getOperand(1).getIndex();
82 return MI->getOperand(0).getReg();
88 /// isStoreToStackSlot - If the specified machine instruction is a direct
89 /// store to a stack slot, return the virtual or physical register number of
90 /// the source reg along with the FrameIndex of the loaded stack slot. If
91 /// not, return 0. This predicate must return 0 if the instruction has
92 /// any side effects other than storing to the stack slot.
93 unsigned SparcInstrInfo::isStoreToStackSlot(const MachineInstr *MI,
94 int &FrameIndex) const {
95 if (MI->getOpcode() == SP::STri ||
96 MI->getOpcode() == SP::STFri ||
97 MI->getOpcode() == SP::STDFri) {
98 if (MI->getOperand(0).isFI() && MI->getOperand(1).isImm() &&
99 MI->getOperand(1).getImm() == 0) {
100 FrameIndex = MI->getOperand(0).getIndex();
101 return MI->getOperand(2).getReg();
108 SparcInstrInfo::InsertBranch(MachineBasicBlock &MBB,MachineBasicBlock *TBB,
109 MachineBasicBlock *FBB,
110 const SmallVectorImpl<MachineOperand> &Cond)const{
111 // FIXME this should probably take a DebugLoc argument
112 DebugLoc dl = DebugLoc::getUnknownLoc();
113 // Can only insert uncond branches so far.
114 assert(Cond.empty() && !FBB && TBB && "Can only handle uncond branches!");
115 BuildMI(&MBB, dl, get(SP::BA)).addMBB(TBB);
119 bool SparcInstrInfo::copyRegToReg(MachineBasicBlock &MBB,
120 MachineBasicBlock::iterator I,
121 unsigned DestReg, unsigned SrcReg,
122 const TargetRegisterClass *DestRC,
123 const TargetRegisterClass *SrcRC) const {
124 if (DestRC != SrcRC) {
125 // Not yet supported!
129 DebugLoc DL = DebugLoc::getUnknownLoc();
130 if (I != MBB.end()) DL = I->getDebugLoc();
132 if (DestRC == SP::IntRegsRegisterClass)
133 BuildMI(MBB, I, DL, get(SP::ORrr), DestReg).addReg(SP::G0).addReg(SrcReg);
134 else if (DestRC == SP::FPRegsRegisterClass)
135 BuildMI(MBB, I, DL, get(SP::FMOVS), DestReg).addReg(SrcReg);
136 else if (DestRC == SP::DFPRegsRegisterClass)
137 BuildMI(MBB, I, DL, get(Subtarget.isV9() ? SP::FMOVD : SP::FpMOVD),DestReg)
140 // Can't copy this register
146 void SparcInstrInfo::
147 storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
148 unsigned SrcReg, bool isKill, int FI,
149 const TargetRegisterClass *RC) const {
150 DebugLoc DL = DebugLoc::getUnknownLoc();
151 if (I != MBB.end()) DL = I->getDebugLoc();
153 // On the order of operands here: think "[FrameIdx + 0] = SrcReg".
154 if (RC == SP::IntRegsRegisterClass)
155 BuildMI(MBB, I, DL, get(SP::STri)).addFrameIndex(FI).addImm(0)
156 .addReg(SrcReg, getKillRegState(isKill));
157 else if (RC == SP::FPRegsRegisterClass)
158 BuildMI(MBB, I, DL, get(SP::STFri)).addFrameIndex(FI).addImm(0)
159 .addReg(SrcReg, getKillRegState(isKill));
160 else if (RC == SP::DFPRegsRegisterClass)
161 BuildMI(MBB, I, DL, get(SP::STDFri)).addFrameIndex(FI).addImm(0)
162 .addReg(SrcReg, getKillRegState(isKill));
164 llvm_unreachable("Can't store this register to stack slot");
167 void SparcInstrInfo::storeRegToAddr(MachineFunction &MF, unsigned SrcReg,
169 SmallVectorImpl<MachineOperand> &Addr,
170 const TargetRegisterClass *RC,
171 SmallVectorImpl<MachineInstr*> &NewMIs) const {
173 DebugLoc DL = DebugLoc::getUnknownLoc();
174 if (RC == SP::IntRegsRegisterClass)
176 else if (RC == SP::FPRegsRegisterClass)
178 else if (RC == SP::DFPRegsRegisterClass)
181 llvm_unreachable("Can't load this register");
182 MachineInstrBuilder MIB = BuildMI(MF, DL, get(Opc));
183 for (unsigned i = 0, e = Addr.size(); i != e; ++i)
184 MIB.addOperand(Addr[i]);
185 MIB.addReg(SrcReg, getKillRegState(isKill));
186 NewMIs.push_back(MIB);
190 void SparcInstrInfo::
191 loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
192 unsigned DestReg, int FI,
193 const TargetRegisterClass *RC) const {
194 DebugLoc DL = DebugLoc::getUnknownLoc();
195 if (I != MBB.end()) DL = I->getDebugLoc();
197 if (RC == SP::IntRegsRegisterClass)
198 BuildMI(MBB, I, DL, get(SP::LDri), DestReg).addFrameIndex(FI).addImm(0);
199 else if (RC == SP::FPRegsRegisterClass)
200 BuildMI(MBB, I, DL, get(SP::LDFri), DestReg).addFrameIndex(FI).addImm(0);
201 else if (RC == SP::DFPRegsRegisterClass)
202 BuildMI(MBB, I, DL, get(SP::LDDFri), DestReg).addFrameIndex(FI).addImm(0);
204 llvm_unreachable("Can't load this register from stack slot");
207 void SparcInstrInfo::loadRegFromAddr(MachineFunction &MF, unsigned DestReg,
208 SmallVectorImpl<MachineOperand> &Addr,
209 const TargetRegisterClass *RC,
210 SmallVectorImpl<MachineInstr*> &NewMIs) const {
212 if (RC == SP::IntRegsRegisterClass)
214 else if (RC == SP::FPRegsRegisterClass)
216 else if (RC == SP::DFPRegsRegisterClass)
219 llvm_unreachable("Can't load this register");
220 DebugLoc DL = DebugLoc::getUnknownLoc();
221 MachineInstrBuilder MIB = BuildMI(MF, DL, get(Opc), DestReg);
222 for (unsigned i = 0, e = Addr.size(); i != e; ++i)
223 MIB.addOperand(Addr[i]);
224 NewMIs.push_back(MIB);
228 MachineInstr *SparcInstrInfo::foldMemoryOperandImpl(MachineFunction &MF,
230 const SmallVectorImpl<unsigned> &Ops,
232 if (Ops.size() != 1) return NULL;
234 unsigned OpNum = Ops[0];
235 bool isFloat = false;
236 MachineInstr *NewMI = NULL;
237 switch (MI->getOpcode()) {
239 if (MI->getOperand(1).isReg() && MI->getOperand(1).getReg() == SP::G0&&
240 MI->getOperand(0).isReg() && MI->getOperand(2).isReg()) {
241 if (OpNum == 0) // COPY -> STORE
242 NewMI = BuildMI(MF, MI->getDebugLoc(), get(SP::STri))
245 .addReg(MI->getOperand(2).getReg());
247 NewMI = BuildMI(MF, MI->getDebugLoc(), get(SP::LDri),
248 MI->getOperand(0).getReg())
257 if (OpNum == 0) { // COPY -> STORE
258 unsigned SrcReg = MI->getOperand(1).getReg();
259 bool isKill = MI->getOperand(1).isKill();
260 bool isUndef = MI->getOperand(1).isUndef();
261 NewMI = BuildMI(MF, MI->getDebugLoc(),
262 get(isFloat ? SP::STFri : SP::STDFri))
265 .addReg(SrcReg, getKillRegState(isKill) | getUndefRegState(isUndef));
266 } else { // COPY -> LOAD
267 unsigned DstReg = MI->getOperand(0).getReg();
268 bool isDead = MI->getOperand(0).isDead();
269 bool isUndef = MI->getOperand(0).isUndef();
270 NewMI = BuildMI(MF, MI->getDebugLoc(),
271 get(isFloat ? SP::LDFri : SP::LDDFri))
272 .addReg(DstReg, RegState::Define |
273 getDeadRegState(isDead) | getUndefRegState(isUndef))